1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/mux/ti-serdes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-am642.dtsi" 14 15/ { 16 compatible = "ti,am642-evm", "ti,am642"; 17 model = "Texas Instruments AM642 EVM"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 2G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 28 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 rtos_ipc_memory_region: ipc-memories@a5000000 { 91 reg = <0x00 0xa5000000 0x00 0x00800000>; 92 alignment = <0x1000>; 93 no-map; 94 }; 95 }; 96 97 evm_12v0: regulator-0 { 98 /* main DC jack */ 99 compatible = "regulator-fixed"; 100 regulator-name = "evm_12v0"; 101 regulator-min-microvolt = <12000000>; 102 regulator-max-microvolt = <12000000>; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106 107 vsys_5v0: regulator-1 { 108 /* output of LM5140 */ 109 compatible = "regulator-fixed"; 110 regulator-name = "vsys_5v0"; 111 regulator-min-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>; 113 vin-supply = <&evm_12v0>; 114 regulator-always-on; 115 regulator-boot-on; 116 }; 117 118 vsys_3v3: regulator-2 { 119 /* output of LM5140 */ 120 compatible = "regulator-fixed"; 121 regulator-name = "vsys_3v3"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 vin-supply = <&evm_12v0>; 125 regulator-always-on; 126 regulator-boot-on; 127 }; 128 129 vdd_mmc1: regulator-3 { 130 /* TPS2051BD */ 131 compatible = "regulator-fixed"; 132 regulator-name = "vdd_mmc1"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 regulator-boot-on; 136 enable-active-high; 137 vin-supply = <&vsys_3v3>; 138 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; 139 }; 140 141 vddb: regulator-4 { 142 compatible = "regulator-fixed"; 143 regulator-name = "vddb_3v3_display"; 144 regulator-min-microvolt = <3300000>; 145 regulator-max-microvolt = <3300000>; 146 vin-supply = <&vsys_3v3>; 147 regulator-always-on; 148 regulator-boot-on; 149 }; 150 151 vtt_supply: regulator-5 { 152 compatible = "regulator-fixed"; 153 regulator-name = "vtt"; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&ddr_vtt_pins_default>; 156 regulator-min-microvolt = <3300000>; 157 regulator-max-microvolt = <3300000>; 158 gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; 159 vin-supply = <&vsys_3v3>; 160 enable-active-high; 161 regulator-always-on; 162 regulator-boot-on; 163 }; 164 165 leds { 166 compatible = "gpio-leds"; 167 168 led-0 { 169 label = "am64-evm:red:heartbeat"; 170 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; 171 linux,default-trigger = "heartbeat"; 172 function = LED_FUNCTION_HEARTBEAT; 173 default-state = "off"; 174 }; 175 }; 176 177 mdio_mux: mux-controller { 178 compatible = "gpio-mux"; 179 #mux-control-cells = <0>; 180 181 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; 182 }; 183 184 mdio-mux-1 { 185 compatible = "mdio-mux-multiplexer"; 186 mux-controls = <&mdio_mux>; 187 mdio-parent-bus = <&cpsw3g_mdio>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 191 mdio@1 { 192 reg = <0x1>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 196 cpsw3g_phy3: ethernet-phy@3 { 197 reg = <3>; 198 }; 199 }; 200 }; 201 202 transceiver1: can-phy0 { 203 compatible = "ti,tcan1042"; 204 #phy-cells = <0>; 205 max-bitrate = <5000000>; 206 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; 207 }; 208 209 transceiver2: can-phy1 { 210 compatible = "ti,tcan1042"; 211 #phy-cells = <0>; 212 max-bitrate = <5000000>; 213 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; 214 }; 215}; 216 217&main_pmx0 { 218 main_mmc1_pins_default: main-mmc1-pins-default { 219 pinctrl-single,pins = < 220 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 221 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 222 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 223 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 224 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 225 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 226 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 227 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ 228 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ 229 >; 230 }; 231 232 main_uart1_pins_default: main-uart1-pins-default { 233 pinctrl-single,pins = < 234 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 235 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 236 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 237 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 238 >; 239 }; 240 241 main_uart0_pins_default: main-uart0-pins-default { 242 pinctrl-single,pins = < 243 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 244 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 245 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 246 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 247 >; 248 }; 249 250 main_spi0_pins_default: main-spi0-pins-default { 251 pinctrl-single,pins = < 252 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ 253 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ 254 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ 255 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ 256 >; 257 }; 258 259 main_i2c0_pins_default: main-i2c0-pins-default { 260 pinctrl-single,pins = < 261 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ 262 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ 263 >; 264 }; 265 266 main_i2c1_pins_default: main-i2c1-pins-default { 267 pinctrl-single,pins = < 268 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 269 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 270 >; 271 }; 272 273 mdio1_pins_default: mdio1-pins-default { 274 pinctrl-single,pins = < 275 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 276 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 277 >; 278 }; 279 280 rgmii1_pins_default: rgmii1-pins-default { 281 pinctrl-single,pins = < 282 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 283 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 284 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 285 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 286 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 287 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 288 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 289 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 290 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 291 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 292 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 293 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 294 >; 295 }; 296 297 rgmii2_pins_default: rgmii2-pins-default { 298 pinctrl-single,pins = < 299 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 300 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 301 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 302 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 303 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 304 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 305 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 306 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 307 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 308 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 309 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 310 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 311 >; 312 }; 313 314 main_usb0_pins_default: main-usb0-pins-default { 315 pinctrl-single,pins = < 316 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 317 >; 318 }; 319 320 ospi0_pins_default: ospi0-pins-default { 321 pinctrl-single,pins = < 322 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 323 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 324 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 325 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 326 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 327 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 328 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 329 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 330 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 331 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 332 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 333 >; 334 }; 335 336 main_ecap0_pins_default: main-ecap0-pins-default { 337 pinctrl-single,pins = < 338 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 339 >; 340 }; 341 342 main_mcan0_pins_default: main-mcan0-pins-default { 343 pinctrl-single,pins = < 344 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ 345 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ 346 >; 347 }; 348 349 main_mcan1_pins_default: main-mcan1-pins-default { 350 pinctrl-single,pins = < 351 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ 352 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ 353 >; 354 }; 355 356 ddr_vtt_pins_default: ddr-vtt-pins-default { 357 pinctrl-single,pins = < 358 AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ 359 >; 360 }; 361}; 362 363&main_uart0 { 364 status = "okay"; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&main_uart0_pins_default>; 367}; 368 369/* main_uart1 is reserved for firmware usage */ 370&main_uart1 { 371 status = "reserved"; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&main_uart1_pins_default>; 374}; 375 376&main_i2c0 { 377 status = "okay"; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&main_i2c0_pins_default>; 380 clock-frequency = <400000>; 381 382 eeprom@50 { 383 /* AT24CM01 */ 384 compatible = "atmel,24c1024"; 385 reg = <0x50>; 386 }; 387}; 388 389&main_i2c1 { 390 status = "okay"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&main_i2c1_pins_default>; 393 clock-frequency = <400000>; 394 395 exp1: gpio@22 { 396 compatible = "ti,tca6424"; 397 reg = <0x22>; 398 gpio-controller; 399 #gpio-cells = <2>; 400 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", 401 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", 402 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", 403 "MMC1_SD_EN", "FSI_FET_SEL", 404 "MCAN0_STB_3V3", "MCAN1_STB_3V3", 405 "CPSW_FET_SEL", "CPSW_FET2_SEL", 406 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", 407 "GPIO_OLED_RESETn", "VPP_LDO_EN", 408 "TEST_LED1", "TP92", "TP90", "TP88", 409 "TP87", "TP86", "TP89", "TP91"; 410 }; 411 412 /* osd9616p0899-10 */ 413 display@3c { 414 compatible = "solomon,ssd1306fb-i2c"; 415 reg = <0x3c>; 416 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; 417 vbat-supply = <&vddb>; 418 solomon,height = <16>; 419 solomon,width = <96>; 420 solomon,com-seq; 421 solomon,com-invdir; 422 solomon,page-offset = <0>; 423 solomon,prechargep1 = <2>; 424 solomon,prechargep2 = <13>; 425 }; 426}; 427 428/* mcu_gpio0 is reserved for mcu firmware usage */ 429&mcu_gpio0 { 430 status = "reserved"; 431}; 432 433&main_spi0 { 434 status = "okay"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&main_spi0_pins_default>; 437 ti,pindir-d0-out-d1-in; 438 eeprom@0 { 439 compatible = "microchip,93lc46b"; 440 reg = <0>; 441 spi-max-frequency = <1000000>; 442 spi-cs-high; 443 data-size = <16>; 444 }; 445}; 446 447&sdhci0 { 448 /* emmc */ 449 bus-width = <8>; 450 non-removable; 451 ti,driver-strength-ohm = <50>; 452 disable-wp; 453}; 454 455&sdhci1 { 456 /* SD/MMC */ 457 vmmc-supply = <&vdd_mmc1>; 458 pinctrl-names = "default"; 459 bus-width = <4>; 460 pinctrl-0 = <&main_mmc1_pins_default>; 461 ti,driver-strength-ohm = <50>; 462 disable-wp; 463}; 464 465&usbss0 { 466 ti,vbus-divider; 467 ti,usb2-only; 468}; 469 470&usb0 { 471 dr_mode = "otg"; 472 maximum-speed = "high-speed"; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&main_usb0_pins_default>; 475}; 476 477&cpsw3g { 478 pinctrl-names = "default"; 479 pinctrl-0 = <&rgmii1_pins_default 480 &rgmii2_pins_default>; 481}; 482 483&cpsw_port1 { 484 phy-mode = "rgmii-rxid"; 485 phy-handle = <&cpsw3g_phy0>; 486}; 487 488&cpsw_port2 { 489 phy-mode = "rgmii-rxid"; 490 phy-handle = <&cpsw3g_phy3>; 491}; 492 493&cpsw3g_mdio { 494 status = "okay"; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&mdio1_pins_default>; 497 498 cpsw3g_phy0: ethernet-phy@0 { 499 reg = <0>; 500 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 501 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 502 }; 503}; 504 505&tscadc0 { 506 /* ADC is reserved for R5 usage */ 507 status = "reserved"; 508}; 509 510&ospi0 { 511 pinctrl-names = "default"; 512 pinctrl-0 = <&ospi0_pins_default>; 513 514 flash@0 { 515 compatible = "jedec,spi-nor"; 516 reg = <0x0>; 517 spi-tx-bus-width = <8>; 518 spi-rx-bus-width = <8>; 519 spi-max-frequency = <25000000>; 520 cdns,tshsl-ns = <60>; 521 cdns,tsd2d-ns = <60>; 522 cdns,tchsh-ns = <60>; 523 cdns,tslch-ns = <60>; 524 cdns,read-delay = <4>; 525 }; 526}; 527 528&mailbox0_cluster2 { 529 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 530 ti,mbox-rx = <0 0 2>; 531 ti,mbox-tx = <1 0 2>; 532 }; 533 534 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 535 ti,mbox-rx = <2 0 2>; 536 ti,mbox-tx = <3 0 2>; 537 }; 538}; 539 540&mailbox0_cluster3 { 541 status = "disabled"; 542}; 543 544&mailbox0_cluster4 { 545 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 546 ti,mbox-rx = <0 0 2>; 547 ti,mbox-tx = <1 0 2>; 548 }; 549 550 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 551 ti,mbox-rx = <2 0 2>; 552 ti,mbox-tx = <3 0 2>; 553 }; 554}; 555 556&mailbox0_cluster5 { 557 status = "disabled"; 558}; 559 560&mailbox0_cluster6 { 561 mbox_m4_0: mbox-m4-0 { 562 ti,mbox-rx = <0 0 2>; 563 ti,mbox-tx = <1 0 2>; 564 }; 565}; 566 567&mailbox0_cluster7 { 568 status = "disabled"; 569}; 570 571&main_r5fss0_core0 { 572 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 573 memory-region = <&main_r5fss0_core0_dma_memory_region>, 574 <&main_r5fss0_core0_memory_region>; 575}; 576 577&main_r5fss0_core1 { 578 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 579 memory-region = <&main_r5fss0_core1_dma_memory_region>, 580 <&main_r5fss0_core1_memory_region>; 581}; 582 583&main_r5fss1_core0 { 584 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 585 memory-region = <&main_r5fss1_core0_dma_memory_region>, 586 <&main_r5fss1_core0_memory_region>; 587}; 588 589&main_r5fss1_core1 { 590 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 591 memory-region = <&main_r5fss1_core1_dma_memory_region>, 592 <&main_r5fss1_core1_memory_region>; 593}; 594 595&serdes_ln_ctrl { 596 idle-states = <AM64_SERDES0_LANE0_PCIE0>; 597}; 598 599&serdes0 { 600 serdes0_pcie_link: phy@0 { 601 reg = <0>; 602 cdns,num-lanes = <1>; 603 #phy-cells = <0>; 604 cdns,phy-type = <PHY_TYPE_PCIE>; 605 resets = <&serdes_wiz0 1>; 606 }; 607}; 608 609&pcie0_rc { 610 status = "okay"; 611 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 612 phys = <&serdes0_pcie_link>; 613 phy-names = "pcie-phy"; 614 num-lanes = <1>; 615}; 616 617&pcie0_ep { 618 phys = <&serdes0_pcie_link>; 619 phy-names = "pcie-phy"; 620 num-lanes = <1>; 621}; 622 623&ecap0 { 624 status = "okay"; 625 /* PWM is available on Pin 1 of header J12 */ 626 pinctrl-names = "default"; 627 pinctrl-0 = <&main_ecap0_pins_default>; 628}; 629 630&main_mcan0 { 631 status = "okay"; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&main_mcan0_pins_default>; 634 phys = <&transceiver1>; 635}; 636 637&main_mcan1 { 638 status = "okay"; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&main_mcan1_pins_default>; 641 phys = <&transceiver2>; 642}; 643