1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/mux/ti-serdes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-am642.dtsi" 14 15/ { 16 compatible = "ti,am642-evm", "ti,am642"; 17 model = "Texas Instruments AM642 EVM"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 2G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 28 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 38 alignment = <0x1000>; 39 no-map; 40 }; 41 }; 42 43 evm_12v0: fixedregulator-evm12v0 { 44 /* main DC jack */ 45 compatible = "regulator-fixed"; 46 regulator-name = "evm_12v0"; 47 regulator-min-microvolt = <12000000>; 48 regulator-max-microvolt = <12000000>; 49 regulator-always-on; 50 regulator-boot-on; 51 }; 52 53 vsys_5v0: fixedregulator-vsys5v0 { 54 /* output of LM5140 */ 55 compatible = "regulator-fixed"; 56 regulator-name = "vsys_5v0"; 57 regulator-min-microvolt = <5000000>; 58 regulator-max-microvolt = <5000000>; 59 vin-supply = <&evm_12v0>; 60 regulator-always-on; 61 regulator-boot-on; 62 }; 63 64 vsys_3v3: fixedregulator-vsys3v3 { 65 /* output of LM5140 */ 66 compatible = "regulator-fixed"; 67 regulator-name = "vsys_3v3"; 68 regulator-min-microvolt = <3300000>; 69 regulator-max-microvolt = <3300000>; 70 vin-supply = <&evm_12v0>; 71 regulator-always-on; 72 regulator-boot-on; 73 }; 74 75 vdd_mmc1: fixed-regulator-sd { 76 /* TPS2051BD */ 77 compatible = "regulator-fixed"; 78 regulator-name = "vdd_mmc1"; 79 regulator-min-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>; 81 regulator-boot-on; 82 enable-active-high; 83 vin-supply = <&vsys_3v3>; 84 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; 85 }; 86 87 vddb: fixedregulator-vddb { 88 compatible = "regulator-fixed"; 89 regulator-name = "vddb_3v3_display"; 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 vin-supply = <&vsys_3v3>; 93 regulator-always-on; 94 regulator-boot-on; 95 }; 96 97 leds { 98 compatible = "gpio-leds"; 99 100 led-0 { 101 label = "am64-evm:red:heartbeat"; 102 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; 103 linux,default-trigger = "heartbeat"; 104 function = LED_FUNCTION_HEARTBEAT; 105 default-state = "off"; 106 }; 107 }; 108 109 mdio_mux: mux-controller { 110 compatible = "gpio-mux"; 111 #mux-control-cells = <0>; 112 113 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; 114 }; 115 116 mdio-mux-1 { 117 compatible = "mdio-mux-multiplexer"; 118 mux-controls = <&mdio_mux>; 119 mdio-parent-bus = <&cpsw3g_mdio>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 mdio@1 { 124 reg = <0x1>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 128 cpsw3g_phy3: ethernet-phy@3 { 129 reg = <3>; 130 }; 131 }; 132 }; 133}; 134 135&main_pmx0 { 136 main_mmc1_pins_default: main-mmc1-pins-default { 137 pinctrl-single,pins = < 138 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 139 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 140 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 141 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 142 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 143 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 144 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 145 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ 146 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ 147 >; 148 }; 149 150 main_uart0_pins_default: main-uart0-pins-default { 151 pinctrl-single,pins = < 152 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 153 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 154 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 155 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 156 >; 157 }; 158 159 main_spi0_pins_default: main-spi0-pins-default { 160 pinctrl-single,pins = < 161 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ 162 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ 163 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ 164 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ 165 >; 166 }; 167 168 main_i2c1_pins_default: main-i2c1-pins-default { 169 pinctrl-single,pins = < 170 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 171 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 172 >; 173 }; 174 175 mdio1_pins_default: mdio1-pins-default { 176 pinctrl-single,pins = < 177 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 178 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 179 >; 180 }; 181 182 rgmii1_pins_default: rgmii1-pins-default { 183 pinctrl-single,pins = < 184 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 185 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 186 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 187 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 188 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 189 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 190 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 191 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 192 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 193 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 194 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 195 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 196 >; 197 }; 198 199 rgmii2_pins_default: rgmii2-pins-default { 200 pinctrl-single,pins = < 201 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 202 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 203 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 204 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 205 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 206 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 207 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 208 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 209 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 210 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 211 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 212 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 213 >; 214 }; 215 216 main_usb0_pins_default: main-usb0-pins-default { 217 pinctrl-single,pins = < 218 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 219 >; 220 }; 221 222 ospi0_pins_default: ospi0-pins-default { 223 pinctrl-single,pins = < 224 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 225 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 226 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 227 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 228 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 229 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 230 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 231 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 232 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 233 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 234 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 235 >; 236 }; 237}; 238 239&main_uart0 { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&main_uart0_pins_default>; 242}; 243 244/* main_uart1 is reserved for firmware usage */ 245&main_uart1 { 246 status = "reserved"; 247}; 248 249&main_uart2 { 250 status = "disabled"; 251}; 252 253&main_uart3 { 254 status = "disabled"; 255}; 256 257&main_uart4 { 258 status = "disabled"; 259}; 260 261&main_uart5 { 262 status = "disabled"; 263}; 264 265&main_uart6 { 266 status = "disabled"; 267}; 268 269&mcu_uart0 { 270 status = "disabled"; 271}; 272 273&mcu_uart1 { 274 status = "disabled"; 275}; 276 277&main_i2c1 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&main_i2c1_pins_default>; 280 clock-frequency = <400000>; 281 282 exp1: gpio@22 { 283 compatible = "ti,tca6424"; 284 reg = <0x22>; 285 gpio-controller; 286 #gpio-cells = <2>; 287 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", 288 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", 289 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", 290 "MMC1_SD_EN", "FSI_FET_SEL", 291 "MCAN0_STB_3V3", "MCAN1_STB_3V3", 292 "CPSW_FET_SEL", "CPSW_FET2_SEL", 293 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", 294 "GPIO_OLED_RESETn", "VPP_LDO_EN", 295 "TEST_LED1", "TP92", "TP90", "TP88", 296 "TP87", "TP86", "TP89", "TP91"; 297 }; 298 299 /* osd9616p0899-10 */ 300 display@3c { 301 compatible = "solomon,ssd1306fb-i2c"; 302 reg = <0x3c>; 303 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; 304 vbat-supply = <&vddb>; 305 solomon,height = <16>; 306 solomon,width = <96>; 307 solomon,com-seq; 308 solomon,com-invdir; 309 solomon,page-offset = <0>; 310 solomon,prechargep1 = <2>; 311 solomon,prechargep2 = <13>; 312 }; 313}; 314 315/* mcu_gpio0 is reserved for mcu firmware usage */ 316&mcu_gpio0 { 317 status = "reserved"; 318}; 319 320&mcu_i2c0 { 321 status = "disabled"; 322}; 323 324&mcu_i2c1 { 325 status = "disabled"; 326}; 327 328&mcu_spi0 { 329 status = "disabled"; 330}; 331 332&mcu_spi1 { 333 status = "disabled"; 334}; 335 336&main_spi0 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&main_spi0_pins_default>; 339 ti,pindir-d0-out-d1-in; 340 eeprom@0 { 341 compatible = "microchip,93lc46b"; 342 reg = <0>; 343 spi-max-frequency = <1000000>; 344 spi-cs-high; 345 data-size = <16>; 346 }; 347}; 348 349&sdhci0 { 350 /* emmc */ 351 bus-width = <8>; 352 non-removable; 353 ti,driver-strength-ohm = <50>; 354 disable-wp; 355}; 356 357&sdhci1 { 358 /* SD/MMC */ 359 vmmc-supply = <&vdd_mmc1>; 360 pinctrl-names = "default"; 361 bus-width = <4>; 362 pinctrl-0 = <&main_mmc1_pins_default>; 363 ti,driver-strength-ohm = <50>; 364 disable-wp; 365}; 366 367&usbss0 { 368 ti,vbus-divider; 369 ti,usb2-only; 370}; 371 372&usb0 { 373 dr_mode = "otg"; 374 maximum-speed = "high-speed"; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&main_usb0_pins_default>; 377}; 378 379&cpsw3g { 380 pinctrl-names = "default"; 381 pinctrl-0 = <&mdio1_pins_default 382 &rgmii1_pins_default 383 &rgmii2_pins_default>; 384}; 385 386&cpsw_port1 { 387 phy-mode = "rgmii-rxid"; 388 phy-handle = <&cpsw3g_phy0>; 389}; 390 391&cpsw_port2 { 392 phy-mode = "rgmii-rxid"; 393 phy-handle = <&cpsw3g_phy3>; 394}; 395 396&cpsw3g_mdio { 397 cpsw3g_phy0: ethernet-phy@0 { 398 reg = <0>; 399 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 400 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 401 }; 402}; 403 404&tscadc0 { 405 /* ADC is reserved for R5 usage */ 406 status = "reserved"; 407}; 408 409&ospi0 { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&ospi0_pins_default>; 412 413 flash@0{ 414 compatible = "jedec,spi-nor"; 415 reg = <0x0>; 416 spi-tx-bus-width = <8>; 417 spi-rx-bus-width = <8>; 418 spi-max-frequency = <25000000>; 419 cdns,tshsl-ns = <60>; 420 cdns,tsd2d-ns = <60>; 421 cdns,tchsh-ns = <60>; 422 cdns,tslch-ns = <60>; 423 cdns,read-delay = <4>; 424 #address-cells = <1>; 425 #size-cells = <1>; 426 }; 427}; 428 429&mailbox0_cluster2 { 430 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 431 ti,mbox-rx = <0 0 2>; 432 ti,mbox-tx = <1 0 2>; 433 }; 434 435 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 436 ti,mbox-rx = <2 0 2>; 437 ti,mbox-tx = <3 0 2>; 438 }; 439}; 440 441&mailbox0_cluster3 { 442 status = "disabled"; 443}; 444 445&mailbox0_cluster4 { 446 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 447 ti,mbox-rx = <0 0 2>; 448 ti,mbox-tx = <1 0 2>; 449 }; 450 451 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 452 ti,mbox-rx = <2 0 2>; 453 ti,mbox-tx = <3 0 2>; 454 }; 455}; 456 457&mailbox0_cluster5 { 458 status = "disabled"; 459}; 460 461&mailbox0_cluster6 { 462 mbox_m4_0: mbox-m4-0 { 463 ti,mbox-rx = <0 0 2>; 464 ti,mbox-tx = <1 0 2>; 465 }; 466}; 467 468&mailbox0_cluster7 { 469 status = "disabled"; 470}; 471 472&main_r5fss0_core0 { 473 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 474}; 475 476&main_r5fss0_core1 { 477 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 478}; 479 480&main_r5fss1_core0 { 481 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 482}; 483 484&main_r5fss1_core1 { 485 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 486}; 487 488&serdes_ln_ctrl { 489 idle-states = <AM64_SERDES0_LANE0_PCIE0>; 490}; 491 492&serdes0 { 493 serdes0_pcie_link: phy@0 { 494 reg = <0>; 495 cdns,num-lanes = <1>; 496 #phy-cells = <0>; 497 cdns,phy-type = <PHY_TYPE_PCIE>; 498 resets = <&serdes_wiz0 1>; 499 }; 500}; 501 502&pcie0_rc { 503 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 504 phys = <&serdes0_pcie_link>; 505 phy-names = "pcie-phy"; 506 num-lanes = <1>; 507}; 508 509&pcie0_ep { 510 phys = <&serdes0_pcie_link>; 511 phy-names = "pcie-phy"; 512 num-lanes = <1>; 513 status = "disabled"; 514}; 515