1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree file for the AM62P main domain peripherals
4 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
5 */
6
7&cbass_main {
8	oc_sram: sram@70000000 {
9		compatible = "mmio-sram";
10		reg = <0x00 0x70000000 0x00 0x10000>;
11		#address-cells = <1>;
12		#size-cells = <1>;
13		ranges = <0x00 0x00 0x70000000 0x10000>;
14	};
15
16	gic500: interrupt-controller@1800000 {
17		compatible = "arm,gic-v3";
18		#address-cells = <2>;
19		#size-cells = <2>;
20		ranges;
21		#interrupt-cells = <3>;
22		interrupt-controller;
23		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
24		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */
25		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */
26		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */
27		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */
28		/*
29		 * vcpumntirq:
30		 * virtual CPU interface maintenance interrupt
31		 */
32		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
33
34		gic_its: msi-controller@1820000 {
35			compatible = "arm,gic-v3-its";
36			reg = <0x00 0x01820000 0x00 0x10000>;
37			socionext,synquacer-pre-its = <0x1000000 0x400000>;
38			msi-controller;
39			#msi-cells = <1>;
40		};
41	};
42
43	dmss: bus@48000000 {
44		bootph-all;
45		compatible = "simple-mfd";
46		#address-cells = <2>;
47		#size-cells = <2>;
48		dma-ranges;
49		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
50
51		ti,sci-dev-id = <25>;
52
53		secure_proxy_main: mailbox@4d000000 {
54			bootph-all;
55			compatible = "ti,am654-secure-proxy";
56			#mbox-cells = <1>;
57			reg-names = "target_data", "rt", "scfg";
58			reg = <0x00 0x4d000000 0x00 0x80000>,
59			      <0x00 0x4a600000 0x00 0x80000>,
60			      <0x00 0x4a400000 0x00 0x80000>;
61			interrupt-names = "rx_012";
62			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
63		};
64	};
65
66	dmsc: system-controller@44043000 {
67		bootph-all;
68		compatible = "ti,k2g-sci";
69		ti,host-id = <12>;
70		mbox-names = "rx", "tx";
71		mboxes = <&secure_proxy_main 12>,
72			 <&secure_proxy_main 13>;
73		reg-names = "debug_messages";
74		reg = <0x00 0x44043000 0x00 0xfe0>;
75
76		k3_pds: power-controller {
77			bootph-all;
78			compatible = "ti,sci-pm-domain";
79			#power-domain-cells = <2>;
80		};
81
82		k3_clks: clock-controller {
83			bootph-all;
84			compatible = "ti,k2g-sci-clk";
85			#clock-cells = <2>;
86		};
87
88		k3_reset: reset-controller {
89			bootph-all;
90			compatible = "ti,sci-reset";
91			#reset-cells = <2>;
92		};
93	};
94
95	main_pmx0: pinctrl@f4000 {
96		bootph-all;
97		compatible = "pinctrl-single";
98		reg = <0x00 0xf4000 0x00 0x2ac>;
99		#pinctrl-cells = <1>;
100		pinctrl-single,register-width = <32>;
101		pinctrl-single,function-mask = <0xffffffff>;
102	};
103
104	main_timer0: timer@2400000 {
105		bootph-all;
106		compatible = "ti,am654-timer";
107		reg = <0x00 0x2400000 0x00 0x400>;
108		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
109		clocks = <&k3_clks 36 2>;
110		clock-names = "fck";
111		assigned-clocks = <&k3_clks 36 2>;
112		assigned-clock-parents = <&k3_clks 36 3>;
113		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
114		ti,timer-pwm;
115	};
116
117	main_uart0: serial@2800000 {
118		compatible = "ti,am64-uart", "ti,am654-uart";
119		reg = <0x00 0x02800000 0x00 0x100>;
120		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
121		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
122		clocks = <&k3_clks 146 0>;
123		clock-names = "fclk";
124		status = "disabled";
125	};
126
127	main_uart1: serial@2810000 {
128		compatible = "ti,am64-uart", "ti,am654-uart";
129		reg = <0x00 0x02810000 0x00 0x100>;
130		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
131		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
132		clocks = <&k3_clks 152 0>;
133		clock-names = "fclk";
134		status = "disabled";
135	};
136};
137