1*5fc6b1b6SVignesh Raghavendra// SPDX-License-Identifier: GPL-2.0 2*5fc6b1b6SVignesh Raghavendra/* 3*5fc6b1b6SVignesh Raghavendra * Device Tree Source for AM62A7 SoC family in Quad core configuration 4*5fc6b1b6SVignesh Raghavendra * 5*5fc6b1b6SVignesh Raghavendra * TRM: https://www.ti.com/lit/zip/spruj16 6*5fc6b1b6SVignesh Raghavendra * 7*5fc6b1b6SVignesh Raghavendra * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 8*5fc6b1b6SVignesh Raghavendra */ 9*5fc6b1b6SVignesh Raghavendra 10*5fc6b1b6SVignesh Raghavendra/dts-v1/; 11*5fc6b1b6SVignesh Raghavendra 12*5fc6b1b6SVignesh Raghavendra#include "k3-am62a.dtsi" 13*5fc6b1b6SVignesh Raghavendra 14*5fc6b1b6SVignesh Raghavendra/ { 15*5fc6b1b6SVignesh Raghavendra cpus { 16*5fc6b1b6SVignesh Raghavendra #address-cells = <1>; 17*5fc6b1b6SVignesh Raghavendra #size-cells = <0>; 18*5fc6b1b6SVignesh Raghavendra 19*5fc6b1b6SVignesh Raghavendra cpu-map { 20*5fc6b1b6SVignesh Raghavendra cluster0: cluster0 { 21*5fc6b1b6SVignesh Raghavendra core0 { 22*5fc6b1b6SVignesh Raghavendra cpu = <&cpu0>; 23*5fc6b1b6SVignesh Raghavendra }; 24*5fc6b1b6SVignesh Raghavendra 25*5fc6b1b6SVignesh Raghavendra core1 { 26*5fc6b1b6SVignesh Raghavendra cpu = <&cpu1>; 27*5fc6b1b6SVignesh Raghavendra }; 28*5fc6b1b6SVignesh Raghavendra 29*5fc6b1b6SVignesh Raghavendra core2 { 30*5fc6b1b6SVignesh Raghavendra cpu = <&cpu2>; 31*5fc6b1b6SVignesh Raghavendra }; 32*5fc6b1b6SVignesh Raghavendra 33*5fc6b1b6SVignesh Raghavendra core3 { 34*5fc6b1b6SVignesh Raghavendra cpu = <&cpu3>; 35*5fc6b1b6SVignesh Raghavendra }; 36*5fc6b1b6SVignesh Raghavendra }; 37*5fc6b1b6SVignesh Raghavendra }; 38*5fc6b1b6SVignesh Raghavendra 39*5fc6b1b6SVignesh Raghavendra cpu0: cpu@0 { 40*5fc6b1b6SVignesh Raghavendra compatible = "arm,cortex-a53"; 41*5fc6b1b6SVignesh Raghavendra reg = <0x000>; 42*5fc6b1b6SVignesh Raghavendra device_type = "cpu"; 43*5fc6b1b6SVignesh Raghavendra enable-method = "psci"; 44*5fc6b1b6SVignesh Raghavendra i-cache-size = <0x8000>; 45*5fc6b1b6SVignesh Raghavendra i-cache-line-size = <64>; 46*5fc6b1b6SVignesh Raghavendra i-cache-sets = <256>; 47*5fc6b1b6SVignesh Raghavendra d-cache-size = <0x8000>; 48*5fc6b1b6SVignesh Raghavendra d-cache-line-size = <64>; 49*5fc6b1b6SVignesh Raghavendra d-cache-sets = <128>; 50*5fc6b1b6SVignesh Raghavendra next-level-cache = <&L2_0>; 51*5fc6b1b6SVignesh Raghavendra }; 52*5fc6b1b6SVignesh Raghavendra 53*5fc6b1b6SVignesh Raghavendra cpu1: cpu@1 { 54*5fc6b1b6SVignesh Raghavendra compatible = "arm,cortex-a53"; 55*5fc6b1b6SVignesh Raghavendra reg = <0x001>; 56*5fc6b1b6SVignesh Raghavendra device_type = "cpu"; 57*5fc6b1b6SVignesh Raghavendra enable-method = "psci"; 58*5fc6b1b6SVignesh Raghavendra i-cache-size = <0x8000>; 59*5fc6b1b6SVignesh Raghavendra i-cache-line-size = <64>; 60*5fc6b1b6SVignesh Raghavendra i-cache-sets = <256>; 61*5fc6b1b6SVignesh Raghavendra d-cache-size = <0x8000>; 62*5fc6b1b6SVignesh Raghavendra d-cache-line-size = <64>; 63*5fc6b1b6SVignesh Raghavendra d-cache-sets = <128>; 64*5fc6b1b6SVignesh Raghavendra next-level-cache = <&L2_0>; 65*5fc6b1b6SVignesh Raghavendra }; 66*5fc6b1b6SVignesh Raghavendra 67*5fc6b1b6SVignesh Raghavendra cpu2: cpu@2 { 68*5fc6b1b6SVignesh Raghavendra compatible = "arm,cortex-a53"; 69*5fc6b1b6SVignesh Raghavendra reg = <0x002>; 70*5fc6b1b6SVignesh Raghavendra device_type = "cpu"; 71*5fc6b1b6SVignesh Raghavendra enable-method = "psci"; 72*5fc6b1b6SVignesh Raghavendra i-cache-size = <0x8000>; 73*5fc6b1b6SVignesh Raghavendra i-cache-line-size = <64>; 74*5fc6b1b6SVignesh Raghavendra i-cache-sets = <256>; 75*5fc6b1b6SVignesh Raghavendra d-cache-size = <0x8000>; 76*5fc6b1b6SVignesh Raghavendra d-cache-line-size = <64>; 77*5fc6b1b6SVignesh Raghavendra d-cache-sets = <128>; 78*5fc6b1b6SVignesh Raghavendra next-level-cache = <&L2_0>; 79*5fc6b1b6SVignesh Raghavendra }; 80*5fc6b1b6SVignesh Raghavendra 81*5fc6b1b6SVignesh Raghavendra cpu3: cpu@3 { 82*5fc6b1b6SVignesh Raghavendra compatible = "arm,cortex-a53"; 83*5fc6b1b6SVignesh Raghavendra reg = <0x003>; 84*5fc6b1b6SVignesh Raghavendra device_type = "cpu"; 85*5fc6b1b6SVignesh Raghavendra enable-method = "psci"; 86*5fc6b1b6SVignesh Raghavendra i-cache-size = <0x8000>; 87*5fc6b1b6SVignesh Raghavendra i-cache-line-size = <64>; 88*5fc6b1b6SVignesh Raghavendra i-cache-sets = <256>; 89*5fc6b1b6SVignesh Raghavendra d-cache-size = <0x8000>; 90*5fc6b1b6SVignesh Raghavendra d-cache-line-size = <64>; 91*5fc6b1b6SVignesh Raghavendra d-cache-sets = <128>; 92*5fc6b1b6SVignesh Raghavendra next-level-cache = <&L2_0>; 93*5fc6b1b6SVignesh Raghavendra }; 94*5fc6b1b6SVignesh Raghavendra }; 95*5fc6b1b6SVignesh Raghavendra 96*5fc6b1b6SVignesh Raghavendra L2_0: l2-cache0 { 97*5fc6b1b6SVignesh Raghavendra compatible = "cache"; 98*5fc6b1b6SVignesh Raghavendra cache-level = <2>; 99*5fc6b1b6SVignesh Raghavendra cache-size = <0x40000>; 100*5fc6b1b6SVignesh Raghavendra cache-line-size = <64>; 101*5fc6b1b6SVignesh Raghavendra cache-sets = <512>; 102*5fc6b1b6SVignesh Raghavendra }; 103*5fc6b1b6SVignesh Raghavendra}; 104