1*f1d17330SVignesh Raghavendra// SPDX-License-Identifier: GPL-2.0 2*f1d17330SVignesh Raghavendra/* 3*f1d17330SVignesh Raghavendra * Device Tree Source for AM625 SoC family in Quad core configuration 4*f1d17330SVignesh Raghavendra * 5*f1d17330SVignesh Raghavendra * TRM: https://www.ti.com/lit/pdf/spruiv7 6*f1d17330SVignesh Raghavendra * 7*f1d17330SVignesh Raghavendra * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 8*f1d17330SVignesh Raghavendra */ 9*f1d17330SVignesh Raghavendra 10*f1d17330SVignesh Raghavendra/dts-v1/; 11*f1d17330SVignesh Raghavendra 12*f1d17330SVignesh Raghavendra#include "k3-am62.dtsi" 13*f1d17330SVignesh Raghavendra 14*f1d17330SVignesh Raghavendra/ { 15*f1d17330SVignesh Raghavendra cpus { 16*f1d17330SVignesh Raghavendra #address-cells = <1>; 17*f1d17330SVignesh Raghavendra #size-cells = <0>; 18*f1d17330SVignesh Raghavendra 19*f1d17330SVignesh Raghavendra cpu-map { 20*f1d17330SVignesh Raghavendra cluster0: cluster0 { 21*f1d17330SVignesh Raghavendra core0 { 22*f1d17330SVignesh Raghavendra cpu = <&cpu0>; 23*f1d17330SVignesh Raghavendra }; 24*f1d17330SVignesh Raghavendra 25*f1d17330SVignesh Raghavendra core1 { 26*f1d17330SVignesh Raghavendra cpu = <&cpu1>; 27*f1d17330SVignesh Raghavendra }; 28*f1d17330SVignesh Raghavendra 29*f1d17330SVignesh Raghavendra core2 { 30*f1d17330SVignesh Raghavendra cpu = <&cpu2>; 31*f1d17330SVignesh Raghavendra }; 32*f1d17330SVignesh Raghavendra 33*f1d17330SVignesh Raghavendra core3 { 34*f1d17330SVignesh Raghavendra cpu = <&cpu3>; 35*f1d17330SVignesh Raghavendra }; 36*f1d17330SVignesh Raghavendra }; 37*f1d17330SVignesh Raghavendra }; 38*f1d17330SVignesh Raghavendra 39*f1d17330SVignesh Raghavendra cpu0: cpu@0 { 40*f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53"; 41*f1d17330SVignesh Raghavendra reg = <0x000>; 42*f1d17330SVignesh Raghavendra device_type = "cpu"; 43*f1d17330SVignesh Raghavendra enable-method = "psci"; 44*f1d17330SVignesh Raghavendra i-cache-size = <0x8000>; 45*f1d17330SVignesh Raghavendra i-cache-line-size = <64>; 46*f1d17330SVignesh Raghavendra i-cache-sets = <256>; 47*f1d17330SVignesh Raghavendra d-cache-size = <0x8000>; 48*f1d17330SVignesh Raghavendra d-cache-line-size = <64>; 49*f1d17330SVignesh Raghavendra d-cache-sets = <128>; 50*f1d17330SVignesh Raghavendra next-level-cache = <&L2_0>; 51*f1d17330SVignesh Raghavendra }; 52*f1d17330SVignesh Raghavendra 53*f1d17330SVignesh Raghavendra cpu1: cpu@1 { 54*f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53"; 55*f1d17330SVignesh Raghavendra reg = <0x001>; 56*f1d17330SVignesh Raghavendra device_type = "cpu"; 57*f1d17330SVignesh Raghavendra enable-method = "psci"; 58*f1d17330SVignesh Raghavendra i-cache-size = <0x8000>; 59*f1d17330SVignesh Raghavendra i-cache-line-size = <64>; 60*f1d17330SVignesh Raghavendra i-cache-sets = <256>; 61*f1d17330SVignesh Raghavendra d-cache-size = <0x8000>; 62*f1d17330SVignesh Raghavendra d-cache-line-size = <64>; 63*f1d17330SVignesh Raghavendra d-cache-sets = <128>; 64*f1d17330SVignesh Raghavendra next-level-cache = <&L2_0>; 65*f1d17330SVignesh Raghavendra }; 66*f1d17330SVignesh Raghavendra 67*f1d17330SVignesh Raghavendra cpu2: cpu@2 { 68*f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53"; 69*f1d17330SVignesh Raghavendra reg = <0x002>; 70*f1d17330SVignesh Raghavendra device_type = "cpu"; 71*f1d17330SVignesh Raghavendra enable-method = "psci"; 72*f1d17330SVignesh Raghavendra i-cache-size = <0x8000>; 73*f1d17330SVignesh Raghavendra i-cache-line-size = <64>; 74*f1d17330SVignesh Raghavendra i-cache-sets = <256>; 75*f1d17330SVignesh Raghavendra d-cache-size = <0x8000>; 76*f1d17330SVignesh Raghavendra d-cache-line-size = <64>; 77*f1d17330SVignesh Raghavendra d-cache-sets = <128>; 78*f1d17330SVignesh Raghavendra next-level-cache = <&L2_0>; 79*f1d17330SVignesh Raghavendra }; 80*f1d17330SVignesh Raghavendra 81*f1d17330SVignesh Raghavendra cpu3: cpu@3 { 82*f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53"; 83*f1d17330SVignesh Raghavendra reg = <0x003>; 84*f1d17330SVignesh Raghavendra device_type = "cpu"; 85*f1d17330SVignesh Raghavendra enable-method = "psci"; 86*f1d17330SVignesh Raghavendra i-cache-size = <0x8000>; 87*f1d17330SVignesh Raghavendra i-cache-line-size = <64>; 88*f1d17330SVignesh Raghavendra i-cache-sets = <256>; 89*f1d17330SVignesh Raghavendra d-cache-size = <0x8000>; 90*f1d17330SVignesh Raghavendra d-cache-line-size = <64>; 91*f1d17330SVignesh Raghavendra d-cache-sets = <128>; 92*f1d17330SVignesh Raghavendra next-level-cache = <&L2_0>; 93*f1d17330SVignesh Raghavendra }; 94*f1d17330SVignesh Raghavendra }; 95*f1d17330SVignesh Raghavendra 96*f1d17330SVignesh Raghavendra L2_0: l2-cache0 { 97*f1d17330SVignesh Raghavendra compatible = "cache"; 98*f1d17330SVignesh Raghavendra cache-level = <2>; 99*f1d17330SVignesh Raghavendra cache-size = <0x40000>; 100*f1d17330SVignesh Raghavendra cache-line-size = <64>; 101*f1d17330SVignesh Raghavendra cache-sets = <512>; 102*f1d17330SVignesh Raghavendra }; 103*f1d17330SVignesh Raghavendra}; 104