1f1d17330SVignesh Raghavendra// SPDX-License-Identifier: GPL-2.0 2f1d17330SVignesh Raghavendra/* 3f1d17330SVignesh Raghavendra * Device Tree Source for AM625 SoC family in Quad core configuration 4f1d17330SVignesh Raghavendra * 5f1d17330SVignesh Raghavendra * TRM: https://www.ti.com/lit/pdf/spruiv7 6f1d17330SVignesh Raghavendra * 7f1d17330SVignesh Raghavendra * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 8f1d17330SVignesh Raghavendra */ 9f1d17330SVignesh Raghavendra 10f1d17330SVignesh Raghavendra/dts-v1/; 11f1d17330SVignesh Raghavendra 12f1d17330SVignesh Raghavendra#include "k3-am62.dtsi" 13f1d17330SVignesh Raghavendra 14f1d17330SVignesh Raghavendra/ { 15f1d17330SVignesh Raghavendra cpus { 16f1d17330SVignesh Raghavendra #address-cells = <1>; 17f1d17330SVignesh Raghavendra #size-cells = <0>; 18f1d17330SVignesh Raghavendra 19f1d17330SVignesh Raghavendra cpu-map { 20f1d17330SVignesh Raghavendra cluster0: cluster0 { 21f1d17330SVignesh Raghavendra core0 { 22f1d17330SVignesh Raghavendra cpu = <&cpu0>; 23f1d17330SVignesh Raghavendra }; 24f1d17330SVignesh Raghavendra 25f1d17330SVignesh Raghavendra core1 { 26f1d17330SVignesh Raghavendra cpu = <&cpu1>; 27f1d17330SVignesh Raghavendra }; 28f1d17330SVignesh Raghavendra 29f1d17330SVignesh Raghavendra core2 { 30f1d17330SVignesh Raghavendra cpu = <&cpu2>; 31f1d17330SVignesh Raghavendra }; 32f1d17330SVignesh Raghavendra 33f1d17330SVignesh Raghavendra core3 { 34f1d17330SVignesh Raghavendra cpu = <&cpu3>; 35f1d17330SVignesh Raghavendra }; 36f1d17330SVignesh Raghavendra }; 37f1d17330SVignesh Raghavendra }; 38f1d17330SVignesh Raghavendra 39f1d17330SVignesh Raghavendra cpu0: cpu@0 { 40f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53"; 41f1d17330SVignesh Raghavendra reg = <0x000>; 42f1d17330SVignesh Raghavendra device_type = "cpu"; 43f1d17330SVignesh Raghavendra enable-method = "psci"; 44f1d17330SVignesh Raghavendra i-cache-size = <0x8000>; 45f1d17330SVignesh Raghavendra i-cache-line-size = <64>; 46f1d17330SVignesh Raghavendra i-cache-sets = <256>; 47f1d17330SVignesh Raghavendra d-cache-size = <0x8000>; 48f1d17330SVignesh Raghavendra d-cache-line-size = <64>; 49f1d17330SVignesh Raghavendra d-cache-sets = <128>; 50f1d17330SVignesh Raghavendra next-level-cache = <&L2_0>; 516d4ee83bSDave Gerlach operating-points-v2 = <&a53_opp_table>; 526d4ee83bSDave Gerlach clocks = <&k3_clks 135 0>; 53f1d17330SVignesh Raghavendra }; 54f1d17330SVignesh Raghavendra 55f1d17330SVignesh Raghavendra cpu1: cpu@1 { 56f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53"; 57f1d17330SVignesh Raghavendra reg = <0x001>; 58f1d17330SVignesh Raghavendra device_type = "cpu"; 59f1d17330SVignesh Raghavendra enable-method = "psci"; 60f1d17330SVignesh Raghavendra i-cache-size = <0x8000>; 61f1d17330SVignesh Raghavendra i-cache-line-size = <64>; 62f1d17330SVignesh Raghavendra i-cache-sets = <256>; 63f1d17330SVignesh Raghavendra d-cache-size = <0x8000>; 64f1d17330SVignesh Raghavendra d-cache-line-size = <64>; 65f1d17330SVignesh Raghavendra d-cache-sets = <128>; 66f1d17330SVignesh Raghavendra next-level-cache = <&L2_0>; 676d4ee83bSDave Gerlach operating-points-v2 = <&a53_opp_table>; 686d4ee83bSDave Gerlach clocks = <&k3_clks 136 0>; 69f1d17330SVignesh Raghavendra }; 70f1d17330SVignesh Raghavendra 71f1d17330SVignesh Raghavendra cpu2: cpu@2 { 72f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53"; 73f1d17330SVignesh Raghavendra reg = <0x002>; 74f1d17330SVignesh Raghavendra device_type = "cpu"; 75f1d17330SVignesh Raghavendra enable-method = "psci"; 76f1d17330SVignesh Raghavendra i-cache-size = <0x8000>; 77f1d17330SVignesh Raghavendra i-cache-line-size = <64>; 78f1d17330SVignesh Raghavendra i-cache-sets = <256>; 79f1d17330SVignesh Raghavendra d-cache-size = <0x8000>; 80f1d17330SVignesh Raghavendra d-cache-line-size = <64>; 81f1d17330SVignesh Raghavendra d-cache-sets = <128>; 82f1d17330SVignesh Raghavendra next-level-cache = <&L2_0>; 836d4ee83bSDave Gerlach operating-points-v2 = <&a53_opp_table>; 846d4ee83bSDave Gerlach clocks = <&k3_clks 137 0>; 85f1d17330SVignesh Raghavendra }; 86f1d17330SVignesh Raghavendra 87f1d17330SVignesh Raghavendra cpu3: cpu@3 { 88f1d17330SVignesh Raghavendra compatible = "arm,cortex-a53"; 89f1d17330SVignesh Raghavendra reg = <0x003>; 90f1d17330SVignesh Raghavendra device_type = "cpu"; 91f1d17330SVignesh Raghavendra enable-method = "psci"; 92f1d17330SVignesh Raghavendra i-cache-size = <0x8000>; 93f1d17330SVignesh Raghavendra i-cache-line-size = <64>; 94f1d17330SVignesh Raghavendra i-cache-sets = <256>; 95f1d17330SVignesh Raghavendra d-cache-size = <0x8000>; 96f1d17330SVignesh Raghavendra d-cache-line-size = <64>; 97f1d17330SVignesh Raghavendra d-cache-sets = <128>; 98f1d17330SVignesh Raghavendra next-level-cache = <&L2_0>; 996d4ee83bSDave Gerlach operating-points-v2 = <&a53_opp_table>; 1006d4ee83bSDave Gerlach clocks = <&k3_clks 138 0>; 1016d4ee83bSDave Gerlach }; 1026d4ee83bSDave Gerlach }; 1036d4ee83bSDave Gerlach 1046d4ee83bSDave Gerlach a53_opp_table: opp-table { 1056d4ee83bSDave Gerlach compatible = "operating-points-v2-ti-cpu"; 1066d4ee83bSDave Gerlach opp-shared; 1076d4ee83bSDave Gerlach syscon = <&wkup_conf>; 1086d4ee83bSDave Gerlach 1096d4ee83bSDave Gerlach opp-200000000 { 1106d4ee83bSDave Gerlach opp-hz = /bits/ 64 <200000000>; 1116d4ee83bSDave Gerlach opp-supported-hw = <0x01 0x0007>; 1126d4ee83bSDave Gerlach clock-latency-ns = <6000000>; 1136d4ee83bSDave Gerlach }; 1146d4ee83bSDave Gerlach 1156d4ee83bSDave Gerlach opp-400000000 { 1166d4ee83bSDave Gerlach opp-hz = /bits/ 64 <400000000>; 1176d4ee83bSDave Gerlach opp-supported-hw = <0x01 0x0007>; 1186d4ee83bSDave Gerlach clock-latency-ns = <6000000>; 1196d4ee83bSDave Gerlach }; 1206d4ee83bSDave Gerlach 1216d4ee83bSDave Gerlach opp-600000000 { 1226d4ee83bSDave Gerlach opp-hz = /bits/ 64 <600000000>; 1236d4ee83bSDave Gerlach opp-supported-hw = <0x01 0x0007>; 1246d4ee83bSDave Gerlach clock-latency-ns = <6000000>; 1256d4ee83bSDave Gerlach }; 1266d4ee83bSDave Gerlach 1276d4ee83bSDave Gerlach opp-800000000 { 1286d4ee83bSDave Gerlach opp-hz = /bits/ 64 <800000000>; 1296d4ee83bSDave Gerlach opp-supported-hw = <0x01 0x0007>; 1306d4ee83bSDave Gerlach clock-latency-ns = <6000000>; 1316d4ee83bSDave Gerlach }; 1326d4ee83bSDave Gerlach 1336d4ee83bSDave Gerlach opp-1000000000 { 1346d4ee83bSDave Gerlach opp-hz = /bits/ 64 <1000000000>; 1356d4ee83bSDave Gerlach opp-supported-hw = <0x01 0x0006>; 1366d4ee83bSDave Gerlach clock-latency-ns = <6000000>; 1376d4ee83bSDave Gerlach }; 1386d4ee83bSDave Gerlach 1396d4ee83bSDave Gerlach opp-1250000000 { 1406d4ee83bSDave Gerlach opp-hz = /bits/ 64 <1250000000>; 1416d4ee83bSDave Gerlach opp-supported-hw = <0x01 0x0004>; 1426d4ee83bSDave Gerlach clock-latency-ns = <6000000>; 1436d4ee83bSDave Gerlach opp-suspend; 144f1d17330SVignesh Raghavendra }; 145f1d17330SVignesh Raghavendra }; 146f1d17330SVignesh Raghavendra 147f1d17330SVignesh Raghavendra L2_0: l2-cache0 { 148f1d17330SVignesh Raghavendra compatible = "cache"; 149880932e6SPierre Gondois cache-unified; 150f1d17330SVignesh Raghavendra cache-level = <2>; 151*6974371cSVignesh Raghavendra cache-size = <0x80000>; 152f1d17330SVignesh Raghavendra cache-line-size = <64>; 153f1d17330SVignesh Raghavendra cache-sets = <512>; 154f1d17330SVignesh Raghavendra }; 155f1d17330SVignesh Raghavendra}; 156