1a033588eSNishanth Menon// SPDX-License-Identifier: GPL-2.0
2a033588eSNishanth Menon/*
3a033588eSNishanth Menon * AM625 SK: https://www.ti.com/lit/zip/sprr448
4a033588eSNishanth Menon *
5a033588eSNishanth Menon * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
6a033588eSNishanth Menon */
7a033588eSNishanth Menon
8a033588eSNishanth Menon/dts-v1/;
9a033588eSNishanth Menon
10a033588eSNishanth Menon#include <dt-bindings/leds/common.h>
11a033588eSNishanth Menon#include <dt-bindings/gpio/gpio.h>
12*d19a66aeSVignesh Raghavendra#include <dt-bindings/net/ti-dp83867.h>
13a033588eSNishanth Menon#include "k3-am625.dtsi"
14a033588eSNishanth Menon
15a033588eSNishanth Menon/ {
16a033588eSNishanth Menon	compatible =  "ti,am625-sk", "ti,am625";
17a033588eSNishanth Menon	model = "Texas Instruments AM625 SK";
18a033588eSNishanth Menon
19a033588eSNishanth Menon	aliases {
20a033588eSNishanth Menon		serial2 = &main_uart0;
21*d19a66aeSVignesh Raghavendra		mmc0 = &sdhci0;
22*d19a66aeSVignesh Raghavendra		mmc1 = &sdhci1;
23*d19a66aeSVignesh Raghavendra		mmc2 = &sdhci2;
24*d19a66aeSVignesh Raghavendra		spi0 = &ospi0;
25*d19a66aeSVignesh Raghavendra		ethernet0 = &cpsw_port1;
26*d19a66aeSVignesh Raghavendra		ethernet1 = &cpsw_port2;
27a033588eSNishanth Menon	};
28a033588eSNishanth Menon
29a033588eSNishanth Menon	chosen {
30a033588eSNishanth Menon		stdout-path = "serial2:115200n8";
31a033588eSNishanth Menon		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
32a033588eSNishanth Menon	};
33a033588eSNishanth Menon
34a033588eSNishanth Menon	memory@80000000 {
35a033588eSNishanth Menon		device_type = "memory";
36a033588eSNishanth Menon		/* 2G RAM */
37a033588eSNishanth Menon		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
38a033588eSNishanth Menon
39a033588eSNishanth Menon	};
40a033588eSNishanth Menon
41a033588eSNishanth Menon	reserved-memory {
42a033588eSNishanth Menon		#address-cells = <2>;
43a033588eSNishanth Menon		#size-cells = <2>;
44a033588eSNishanth Menon		ranges;
45a033588eSNishanth Menon
46a033588eSNishanth Menon		secure_tfa_ddr: tfa@9e780000 {
47a033588eSNishanth Menon			reg = <0x00 0x9e780000 0x00 0x80000>;
48a033588eSNishanth Menon			alignment = <0x1000>;
49a033588eSNishanth Menon			no-map;
50a033588eSNishanth Menon		};
51a033588eSNishanth Menon
52a033588eSNishanth Menon		secure_ddr: optee@9e800000 {
53a033588eSNishanth Menon			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
54a033588eSNishanth Menon			alignment = <0x1000>;
55a033588eSNishanth Menon			no-map;
56a033588eSNishanth Menon		};
57a033588eSNishanth Menon
58a033588eSNishanth Menon		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
59a033588eSNishanth Menon			compatible = "shared-dma-pool";
60a033588eSNishanth Menon			reg = <0x00 0x9db00000 0x00 0xc00000>;
61a033588eSNishanth Menon			no-map;
62a033588eSNishanth Menon		};
63a033588eSNishanth Menon	};
64a033588eSNishanth Menon
65a033588eSNishanth Menon	vmain_pd: regulator-0 {
66a033588eSNishanth Menon		/* TPS65988 PD CONTROLLER OUTPUT */
67a033588eSNishanth Menon		compatible = "regulator-fixed";
68a033588eSNishanth Menon		regulator-name = "vmain_pd";
69a033588eSNishanth Menon		regulator-min-microvolt = <5000000>;
70a033588eSNishanth Menon		regulator-max-microvolt = <5000000>;
71a033588eSNishanth Menon		regulator-always-on;
72a033588eSNishanth Menon		regulator-boot-on;
73a033588eSNishanth Menon	};
74a033588eSNishanth Menon
75a033588eSNishanth Menon	vcc_5v0: regulator-1 {
76a033588eSNishanth Menon		/* Output of LM34936 */
77a033588eSNishanth Menon		compatible = "regulator-fixed";
78a033588eSNishanth Menon		regulator-name = "vcc_5v0";
79a033588eSNishanth Menon		regulator-min-microvolt = <5000000>;
80a033588eSNishanth Menon		regulator-max-microvolt = <5000000>;
81a033588eSNishanth Menon		vin-supply = <&vmain_pd>;
82a033588eSNishanth Menon		regulator-always-on;
83a033588eSNishanth Menon		regulator-boot-on;
84a033588eSNishanth Menon	};
85a033588eSNishanth Menon
86a033588eSNishanth Menon	vcc_3v3_sys: regulator-2 {
87a033588eSNishanth Menon		/* output of LM61460-Q1 */
88a033588eSNishanth Menon		compatible = "regulator-fixed";
89a033588eSNishanth Menon		regulator-name = "vcc_3v3_sys";
90a033588eSNishanth Menon		regulator-min-microvolt = <3300000>;
91a033588eSNishanth Menon		regulator-max-microvolt = <3300000>;
92a033588eSNishanth Menon		vin-supply = <&vmain_pd>;
93a033588eSNishanth Menon		regulator-always-on;
94a033588eSNishanth Menon		regulator-boot-on;
95a033588eSNishanth Menon	};
96a033588eSNishanth Menon
97*d19a66aeSVignesh Raghavendra	vdd_mmc1: regulator-3 {
98*d19a66aeSVignesh Raghavendra		/* TPS22918DBVR */
99*d19a66aeSVignesh Raghavendra		compatible = "regulator-fixed";
100*d19a66aeSVignesh Raghavendra		regulator-name = "vdd_mmc1";
101*d19a66aeSVignesh Raghavendra		regulator-min-microvolt = <3300000>;
102*d19a66aeSVignesh Raghavendra		regulator-max-microvolt = <3300000>;
103*d19a66aeSVignesh Raghavendra		regulator-boot-on;
104*d19a66aeSVignesh Raghavendra		enable-active-high;
105*d19a66aeSVignesh Raghavendra		vin-supply = <&vcc_3v3_sys>;
106*d19a66aeSVignesh Raghavendra		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
107*d19a66aeSVignesh Raghavendra	};
108*d19a66aeSVignesh Raghavendra
109*d19a66aeSVignesh Raghavendra	vdd_sd_dv: regulator-4 {
110*d19a66aeSVignesh Raghavendra		/* Output of TLV71033 */
111*d19a66aeSVignesh Raghavendra		compatible = "regulator-gpio";
112*d19a66aeSVignesh Raghavendra		regulator-name = "tlv71033";
113*d19a66aeSVignesh Raghavendra		pinctrl-names = "default";
114*d19a66aeSVignesh Raghavendra		pinctrl-0 = <&vdd_sd_dv_pins_default>;
115*d19a66aeSVignesh Raghavendra		regulator-min-microvolt = <1800000>;
116*d19a66aeSVignesh Raghavendra		regulator-max-microvolt = <3300000>;
117*d19a66aeSVignesh Raghavendra		regulator-boot-on;
118*d19a66aeSVignesh Raghavendra		vin-supply = <&vcc_5v0>;
119*d19a66aeSVignesh Raghavendra		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
120*d19a66aeSVignesh Raghavendra		states = <1800000 0x0>,
121*d19a66aeSVignesh Raghavendra			 <3300000 0x1>;
122*d19a66aeSVignesh Raghavendra	};
123*d19a66aeSVignesh Raghavendra
124a033588eSNishanth Menon	leds {
125a033588eSNishanth Menon		compatible = "gpio-leds";
126a033588eSNishanth Menon		pinctrl-names = "default";
127a033588eSNishanth Menon		pinctrl-0 = <&usr_led_pins_default>;
128a033588eSNishanth Menon
129a033588eSNishanth Menon		led-0 {
130a033588eSNishanth Menon			label = "am62-sk:green:heartbeat";
131a033588eSNishanth Menon			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
132a033588eSNishanth Menon			linux,default-trigger = "heartbeat";
133a033588eSNishanth Menon			function = LED_FUNCTION_HEARTBEAT;
134a033588eSNishanth Menon			default-state = "off";
135a033588eSNishanth Menon		};
136a033588eSNishanth Menon	};
137a033588eSNishanth Menon};
138a033588eSNishanth Menon
139a033588eSNishanth Menon&main_pmx0 {
140a033588eSNishanth Menon	main_uart0_pins_default: main-uart0-pins-default {
141a033588eSNishanth Menon		pinctrl-single,pins = <
142a033588eSNishanth Menon			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
143a033588eSNishanth Menon			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
144a033588eSNishanth Menon		>;
145a033588eSNishanth Menon	};
146a033588eSNishanth Menon
147a033588eSNishanth Menon	main_i2c0_pins_default: main-i2c0-pins-default {
148a033588eSNishanth Menon		pinctrl-single,pins = <
149a033588eSNishanth Menon			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
150a033588eSNishanth Menon			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
151a033588eSNishanth Menon		>;
152a033588eSNishanth Menon	};
153a033588eSNishanth Menon
154a033588eSNishanth Menon	main_i2c1_pins_default: main-i2c1-pins-default {
155a033588eSNishanth Menon		pinctrl-single,pins = <
156a033588eSNishanth Menon			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
157a033588eSNishanth Menon			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
158a033588eSNishanth Menon		>;
159a033588eSNishanth Menon	};
160a033588eSNishanth Menon
161*d19a66aeSVignesh Raghavendra	main_i2c2_pins_default: main-i2c2-pins-default {
162*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
163*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
164*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
165*d19a66aeSVignesh Raghavendra		>;
166*d19a66aeSVignesh Raghavendra	};
167*d19a66aeSVignesh Raghavendra
168*d19a66aeSVignesh Raghavendra	main_mmc0_pins_default: main-mmc0-pins-default {
169*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
170*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
171*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
172*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
173*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
174*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
175*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
176*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
177*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
178*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
179*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
180*d19a66aeSVignesh Raghavendra		>;
181*d19a66aeSVignesh Raghavendra	};
182*d19a66aeSVignesh Raghavendra
183*d19a66aeSVignesh Raghavendra	main_mmc1_pins_default: main-mmc1-pins-default {
184*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
185*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
186*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
187*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
188*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
189*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
190*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
191*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
192*d19a66aeSVignesh Raghavendra		>;
193*d19a66aeSVignesh Raghavendra	};
194*d19a66aeSVignesh Raghavendra
195a033588eSNishanth Menon	usr_led_pins_default: usr-led-pins-default {
196a033588eSNishanth Menon		pinctrl-single,pins = <
197a033588eSNishanth Menon			AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
198a033588eSNishanth Menon		>;
199a033588eSNishanth Menon	};
200*d19a66aeSVignesh Raghavendra
201*d19a66aeSVignesh Raghavendra	main_mdio1_pins_default: main-mdio1-pins-default {
202*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
203*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
204*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
205*d19a66aeSVignesh Raghavendra		>;
206*d19a66aeSVignesh Raghavendra	};
207*d19a66aeSVignesh Raghavendra
208*d19a66aeSVignesh Raghavendra	main_rgmii1_pins_default: main-rgmii1-pins-default {
209*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
210*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
211*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
212*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
213*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
214*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
215*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
216*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
217*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
218*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
219*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
220*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
221*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
222*d19a66aeSVignesh Raghavendra		>;
223*d19a66aeSVignesh Raghavendra	};
224*d19a66aeSVignesh Raghavendra
225*d19a66aeSVignesh Raghavendra	main_rgmii2_pins_default: main-rgmii2-pins-default {
226*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
227*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
228*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
229*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
230*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
231*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
232*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
233*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
234*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
235*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
236*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
237*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
238*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
239*d19a66aeSVignesh Raghavendra		>;
240*d19a66aeSVignesh Raghavendra	};
241*d19a66aeSVignesh Raghavendra
242*d19a66aeSVignesh Raghavendra	ospi0_pins_default: ospi0-pins-default {
243*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
244*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
245*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
246*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
247*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
248*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
249*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
250*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
251*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
252*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
253*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
254*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
255*d19a66aeSVignesh Raghavendra		>;
256*d19a66aeSVignesh Raghavendra	};
257*d19a66aeSVignesh Raghavendra
258*d19a66aeSVignesh Raghavendra	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
259*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
260*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
261*d19a66aeSVignesh Raghavendra		>;
262*d19a66aeSVignesh Raghavendra	};
263*d19a66aeSVignesh Raghavendra
264*d19a66aeSVignesh Raghavendra	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
265*d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
266*d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
267*d19a66aeSVignesh Raghavendra		>;
268*d19a66aeSVignesh Raghavendra	};
269a033588eSNishanth Menon};
270a033588eSNishanth Menon
271a033588eSNishanth Menon&wkup_uart0 {
272a033588eSNishanth Menon	/* WKUP UART0 is used by DM firmware */
273a033588eSNishanth Menon	status = "reserved";
274a033588eSNishanth Menon};
275a033588eSNishanth Menon
276a033588eSNishanth Menon&mcu_uart0 {
277a033588eSNishanth Menon	status = "disabled";
278a033588eSNishanth Menon};
279a033588eSNishanth Menon
280a033588eSNishanth Menon&main_uart0 {
281a033588eSNishanth Menon	pinctrl-names = "default";
282a033588eSNishanth Menon	pinctrl-0 = <&main_uart0_pins_default>;
283a033588eSNishanth Menon};
284a033588eSNishanth Menon
285a033588eSNishanth Menon&main_uart1 {
286a033588eSNishanth Menon	/* Main UART1 is used by TIFS firmware */
287a033588eSNishanth Menon	status = "reserved";
288a033588eSNishanth Menon};
289a033588eSNishanth Menon
290a033588eSNishanth Menon&main_uart2 {
291a033588eSNishanth Menon	status = "disabled";
292a033588eSNishanth Menon};
293a033588eSNishanth Menon
294a033588eSNishanth Menon&main_uart3 {
295a033588eSNishanth Menon	status = "disabled";
296a033588eSNishanth Menon};
297a033588eSNishanth Menon
298a033588eSNishanth Menon&main_uart4 {
299a033588eSNishanth Menon	status = "disabled";
300a033588eSNishanth Menon};
301a033588eSNishanth Menon
302a033588eSNishanth Menon&main_uart5 {
303a033588eSNishanth Menon	status = "disabled";
304a033588eSNishanth Menon};
305a033588eSNishanth Menon
306a033588eSNishanth Menon&main_uart6 {
307a033588eSNishanth Menon	status = "disabled";
308a033588eSNishanth Menon};
309a033588eSNishanth Menon
310a033588eSNishanth Menon&mcu_i2c0 {
311a033588eSNishanth Menon	status = "disabled";
312a033588eSNishanth Menon};
313a033588eSNishanth Menon
314a033588eSNishanth Menon&wkup_i2c0 {
315a033588eSNishanth Menon	status = "disabled";
316a033588eSNishanth Menon};
317a033588eSNishanth Menon
318a033588eSNishanth Menon&main_i2c0 {
319a033588eSNishanth Menon	pinctrl-names = "default";
320a033588eSNishanth Menon	pinctrl-0 = <&main_i2c0_pins_default>;
321a033588eSNishanth Menon	clock-frequency = <400000>;
322a033588eSNishanth Menon};
323a033588eSNishanth Menon
324a033588eSNishanth Menon&main_i2c1 {
325a033588eSNishanth Menon	pinctrl-names = "default";
326a033588eSNishanth Menon	pinctrl-0 = <&main_i2c1_pins_default>;
327a033588eSNishanth Menon	clock-frequency = <400000>;
328*d19a66aeSVignesh Raghavendra
329*d19a66aeSVignesh Raghavendra	exp1: gpio@22 {
330*d19a66aeSVignesh Raghavendra		compatible = "ti,tca6424";
331*d19a66aeSVignesh Raghavendra		reg = <0x22>;
332*d19a66aeSVignesh Raghavendra		gpio-controller;
333*d19a66aeSVignesh Raghavendra		#gpio-cells = <2>;
334*d19a66aeSVignesh Raghavendra		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
335*d19a66aeSVignesh Raghavendra				   "PRU_DETECT", "MMC1_SD_EN",
336*d19a66aeSVignesh Raghavendra				   "VPP_LDO_EN", "EXP_PS_3V3_En",
337*d19a66aeSVignesh Raghavendra				   "EXP_PS_5V0_En", "EXP_HAT_DETECT",
338*d19a66aeSVignesh Raghavendra				   "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
339*d19a66aeSVignesh Raghavendra				   "UART1_FET_BUF_EN", "WL_LT_EN",
340*d19a66aeSVignesh Raghavendra				   "GPIO_HDMI_RSTn", "CSI_GPIO1",
341*d19a66aeSVignesh Raghavendra				   "CSI_GPIO2", "PRU_3V3_EN",
342*d19a66aeSVignesh Raghavendra				   "HDMI_INTn", "TEST_GPIO2",
343*d19a66aeSVignesh Raghavendra				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
344*d19a66aeSVignesh Raghavendra				   "MCASP1_FET_SEL", "UART1_FET_SEL",
345*d19a66aeSVignesh Raghavendra				   "TSINT#", "IO_EXP_TEST_LED";
346*d19a66aeSVignesh Raghavendra
347*d19a66aeSVignesh Raghavendra		interrupt-parent = <&main_gpio1>;
348*d19a66aeSVignesh Raghavendra		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
349*d19a66aeSVignesh Raghavendra		interrupt-controller;
350*d19a66aeSVignesh Raghavendra		#interrupt-cells = <2>;
351*d19a66aeSVignesh Raghavendra
352*d19a66aeSVignesh Raghavendra		pinctrl-names = "default";
353*d19a66aeSVignesh Raghavendra		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
354*d19a66aeSVignesh Raghavendra	};
355a033588eSNishanth Menon};
356a033588eSNishanth Menon
357a033588eSNishanth Menon&main_i2c2 {
358a033588eSNishanth Menon	status = "disabled";
359a033588eSNishanth Menon};
360a033588eSNishanth Menon
361a033588eSNishanth Menon&main_i2c3 {
362a033588eSNishanth Menon	status = "disabled";
363a033588eSNishanth Menon};
364a033588eSNishanth Menon
365*d19a66aeSVignesh Raghavendra&sdhci0 {
366*d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
367*d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mmc0_pins_default>;
368*d19a66aeSVignesh Raghavendra	ti,driver-strength-ohm = <50>;
369*d19a66aeSVignesh Raghavendra	disable-wp;
370*d19a66aeSVignesh Raghavendra};
371*d19a66aeSVignesh Raghavendra
372*d19a66aeSVignesh Raghavendra&sdhci1 {
373*d19a66aeSVignesh Raghavendra	/* SD/MMC */
374*d19a66aeSVignesh Raghavendra	vmmc-supply = <&vdd_mmc1>;
375*d19a66aeSVignesh Raghavendra	vqmmc-supply = <&vdd_sd_dv>;
376*d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
377*d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mmc1_pins_default>;
378*d19a66aeSVignesh Raghavendra	ti,driver-strength-ohm = <50>;
379*d19a66aeSVignesh Raghavendra	disable-wp;
380*d19a66aeSVignesh Raghavendra};
381*d19a66aeSVignesh Raghavendra
382*d19a66aeSVignesh Raghavendra&cpsw3g {
383*d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
384*d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mdio1_pins_default
385*d19a66aeSVignesh Raghavendra		     &main_rgmii1_pins_default
386*d19a66aeSVignesh Raghavendra		     &main_rgmii2_pins_default>;
387*d19a66aeSVignesh Raghavendra};
388*d19a66aeSVignesh Raghavendra
389*d19a66aeSVignesh Raghavendra&cpsw_port1 {
390*d19a66aeSVignesh Raghavendra	phy-mode = "rgmii-rxid";
391*d19a66aeSVignesh Raghavendra	phy-handle = <&cpsw3g_phy0>;
392*d19a66aeSVignesh Raghavendra};
393*d19a66aeSVignesh Raghavendra
394*d19a66aeSVignesh Raghavendra&cpsw_port2 {
395*d19a66aeSVignesh Raghavendra	phy-mode = "rgmii-rxid";
396*d19a66aeSVignesh Raghavendra	phy-handle = <&cpsw3g_phy1>;
397*d19a66aeSVignesh Raghavendra};
398*d19a66aeSVignesh Raghavendra
399*d19a66aeSVignesh Raghavendra&cpsw3g_mdio {
400*d19a66aeSVignesh Raghavendra	cpsw3g_phy0: ethernet-phy@0 {
401*d19a66aeSVignesh Raghavendra		reg = <0>;
402*d19a66aeSVignesh Raghavendra		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
403*d19a66aeSVignesh Raghavendra		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
404*d19a66aeSVignesh Raghavendra		ti,min-output-impedance;
405*d19a66aeSVignesh Raghavendra	};
406*d19a66aeSVignesh Raghavendra
407*d19a66aeSVignesh Raghavendra	cpsw3g_phy1: ethernet-phy@1 {
408*d19a66aeSVignesh Raghavendra		reg = <1>;
409*d19a66aeSVignesh Raghavendra		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
410*d19a66aeSVignesh Raghavendra		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
411*d19a66aeSVignesh Raghavendra		ti,min-output-impedance;
412*d19a66aeSVignesh Raghavendra	};
413*d19a66aeSVignesh Raghavendra};
414*d19a66aeSVignesh Raghavendra
415a033588eSNishanth Menon&mailbox0_cluster0 {
416a033588eSNishanth Menon	mbox_m4_0: mbox-m4-0 {
417a033588eSNishanth Menon		ti,mbox-rx = <0 0 0>;
418a033588eSNishanth Menon		ti,mbox-tx = <1 0 0>;
419a033588eSNishanth Menon	};
420a033588eSNishanth Menon};
421*d19a66aeSVignesh Raghavendra
422*d19a66aeSVignesh Raghavendra&ospi0 {
423*d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
424*d19a66aeSVignesh Raghavendra	pinctrl-0 = <&ospi0_pins_default>;
425*d19a66aeSVignesh Raghavendra
426*d19a66aeSVignesh Raghavendra	flash@0{
427*d19a66aeSVignesh Raghavendra		compatible = "jedec,spi-nor";
428*d19a66aeSVignesh Raghavendra		reg = <0x0>;
429*d19a66aeSVignesh Raghavendra		spi-tx-bus-width = <8>;
430*d19a66aeSVignesh Raghavendra		spi-rx-bus-width = <8>;
431*d19a66aeSVignesh Raghavendra		spi-max-frequency = <25000000>;
432*d19a66aeSVignesh Raghavendra		cdns,tshsl-ns = <60>;
433*d19a66aeSVignesh Raghavendra		cdns,tsd2d-ns = <60>;
434*d19a66aeSVignesh Raghavendra		cdns,tchsh-ns = <60>;
435*d19a66aeSVignesh Raghavendra		cdns,tslch-ns = <60>;
436*d19a66aeSVignesh Raghavendra		cdns,read-delay = <4>;
437*d19a66aeSVignesh Raghavendra
438*d19a66aeSVignesh Raghavendra		partitions {
439*d19a66aeSVignesh Raghavendra			compatible = "fixed-partitions";
440*d19a66aeSVignesh Raghavendra			#address-cells = <1>;
441*d19a66aeSVignesh Raghavendra			#size-cells = <1>;
442*d19a66aeSVignesh Raghavendra
443*d19a66aeSVignesh Raghavendra			partition@0 {
444*d19a66aeSVignesh Raghavendra				label = "ospi.tiboot3";
445*d19a66aeSVignesh Raghavendra				reg = <0x0 0x80000>;
446*d19a66aeSVignesh Raghavendra			};
447*d19a66aeSVignesh Raghavendra
448*d19a66aeSVignesh Raghavendra			partition@80000 {
449*d19a66aeSVignesh Raghavendra				label = "ospi.tispl";
450*d19a66aeSVignesh Raghavendra				reg = <0x80000 0x200000>;
451*d19a66aeSVignesh Raghavendra			};
452*d19a66aeSVignesh Raghavendra
453*d19a66aeSVignesh Raghavendra			partition@280000 {
454*d19a66aeSVignesh Raghavendra				label = "ospi.u-boot";
455*d19a66aeSVignesh Raghavendra				reg = <0x280000 0x400000>;
456*d19a66aeSVignesh Raghavendra			};
457*d19a66aeSVignesh Raghavendra
458*d19a66aeSVignesh Raghavendra			partition@680000 {
459*d19a66aeSVignesh Raghavendra				label = "ospi.env";
460*d19a66aeSVignesh Raghavendra				reg = <0x680000 0x40000>;
461*d19a66aeSVignesh Raghavendra			};
462*d19a66aeSVignesh Raghavendra
463*d19a66aeSVignesh Raghavendra			partition@6c0000 {
464*d19a66aeSVignesh Raghavendra				label = "ospi.env.backup";
465*d19a66aeSVignesh Raghavendra				reg = <0x6c0000 0x40000>;
466*d19a66aeSVignesh Raghavendra			};
467*d19a66aeSVignesh Raghavendra
468*d19a66aeSVignesh Raghavendra			partition@800000 {
469*d19a66aeSVignesh Raghavendra				label = "ospi.rootfs";
470*d19a66aeSVignesh Raghavendra				reg = <0x800000 0x37c0000>;
471*d19a66aeSVignesh Raghavendra			};
472*d19a66aeSVignesh Raghavendra
473*d19a66aeSVignesh Raghavendra			partition@3fc0000 {
474*d19a66aeSVignesh Raghavendra				label = "ospi.phypattern";
475*d19a66aeSVignesh Raghavendra				reg = <0x3fc0000 0x40000>;
476*d19a66aeSVignesh Raghavendra			};
477*d19a66aeSVignesh Raghavendra		};
478*d19a66aeSVignesh Raghavendra	};
479*d19a66aeSVignesh Raghavendra};
480