1a033588eSNishanth Menon// SPDX-License-Identifier: GPL-2.0
2a033588eSNishanth Menon/*
3a033588eSNishanth Menon * AM625 SK: https://www.ti.com/lit/zip/sprr448
4a033588eSNishanth Menon *
5a033588eSNishanth Menon * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
6a033588eSNishanth Menon */
7a033588eSNishanth Menon
8a033588eSNishanth Menon/dts-v1/;
9a033588eSNishanth Menon
10a033588eSNishanth Menon#include <dt-bindings/leds/common.h>
11a033588eSNishanth Menon#include <dt-bindings/gpio/gpio.h>
12d19a66aeSVignesh Raghavendra#include <dt-bindings/net/ti-dp83867.h>
13a033588eSNishanth Menon#include "k3-am625.dtsi"
14a033588eSNishanth Menon
15a033588eSNishanth Menon/ {
16a033588eSNishanth Menon	compatible = "ti,am625-sk", "ti,am625";
17a033588eSNishanth Menon	model = "Texas Instruments AM625 SK";
18a033588eSNishanth Menon
19a033588eSNishanth Menon	aliases {
20a033588eSNishanth Menon		serial2 = &main_uart0;
21d19a66aeSVignesh Raghavendra		mmc0 = &sdhci0;
22d19a66aeSVignesh Raghavendra		mmc1 = &sdhci1;
23d19a66aeSVignesh Raghavendra		mmc2 = &sdhci2;
24d19a66aeSVignesh Raghavendra		spi0 = &ospi0;
25d19a66aeSVignesh Raghavendra		ethernet0 = &cpsw_port1;
26d19a66aeSVignesh Raghavendra		ethernet1 = &cpsw_port2;
27a033588eSNishanth Menon	};
28a033588eSNishanth Menon
29a033588eSNishanth Menon	chosen {
30a033588eSNishanth Menon		stdout-path = "serial2:115200n8";
31a033588eSNishanth Menon		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
32a033588eSNishanth Menon	};
33a033588eSNishanth Menon
34a033588eSNishanth Menon	memory@80000000 {
35a033588eSNishanth Menon		device_type = "memory";
36a033588eSNishanth Menon		/* 2G RAM */
37a033588eSNishanth Menon		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
38a033588eSNishanth Menon
39a033588eSNishanth Menon	};
40a033588eSNishanth Menon
41a033588eSNishanth Menon	reserved-memory {
42a033588eSNishanth Menon		#address-cells = <2>;
43a033588eSNishanth Menon		#size-cells = <2>;
44a033588eSNishanth Menon		ranges;
45a033588eSNishanth Menon
46e2788887SGuillaume La Roque		ramoops@9ca00000 {
47e2788887SGuillaume La Roque			compatible = "ramoops";
48e2788887SGuillaume La Roque			reg = <0x00 0x9ca00000 0x00 0x00100000>;
49e2788887SGuillaume La Roque			record-size = <0x8000>;
50e2788887SGuillaume La Roque			console-size = <0x8000>;
51e2788887SGuillaume La Roque			ftrace-size = <0x00>;
52e2788887SGuillaume La Roque			pmsg-size = <0x8000>;
53e2788887SGuillaume La Roque		};
54e2788887SGuillaume La Roque
55a033588eSNishanth Menon		secure_tfa_ddr: tfa@9e780000 {
56a033588eSNishanth Menon			reg = <0x00 0x9e780000 0x00 0x80000>;
57a033588eSNishanth Menon			alignment = <0x1000>;
58a033588eSNishanth Menon			no-map;
59a033588eSNishanth Menon		};
60a033588eSNishanth Menon
61a033588eSNishanth Menon		secure_ddr: optee@9e800000 {
62a033588eSNishanth Menon			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
63a033588eSNishanth Menon			alignment = <0x1000>;
64a033588eSNishanth Menon			no-map;
65a033588eSNishanth Menon		};
66a033588eSNishanth Menon
67a033588eSNishanth Menon		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
68a033588eSNishanth Menon			compatible = "shared-dma-pool";
69a033588eSNishanth Menon			reg = <0x00 0x9db00000 0x00 0xc00000>;
70a033588eSNishanth Menon			no-map;
71a033588eSNishanth Menon		};
72a033588eSNishanth Menon	};
73a033588eSNishanth Menon
74a033588eSNishanth Menon	vmain_pd: regulator-0 {
75a033588eSNishanth Menon		/* TPS65988 PD CONTROLLER OUTPUT */
76a033588eSNishanth Menon		compatible = "regulator-fixed";
77a033588eSNishanth Menon		regulator-name = "vmain_pd";
78a033588eSNishanth Menon		regulator-min-microvolt = <5000000>;
79a033588eSNishanth Menon		regulator-max-microvolt = <5000000>;
80a033588eSNishanth Menon		regulator-always-on;
81a033588eSNishanth Menon		regulator-boot-on;
82a033588eSNishanth Menon	};
83a033588eSNishanth Menon
84a033588eSNishanth Menon	vcc_5v0: regulator-1 {
85a033588eSNishanth Menon		/* Output of LM34936 */
86a033588eSNishanth Menon		compatible = "regulator-fixed";
87a033588eSNishanth Menon		regulator-name = "vcc_5v0";
88a033588eSNishanth Menon		regulator-min-microvolt = <5000000>;
89a033588eSNishanth Menon		regulator-max-microvolt = <5000000>;
90a033588eSNishanth Menon		vin-supply = <&vmain_pd>;
91a033588eSNishanth Menon		regulator-always-on;
92a033588eSNishanth Menon		regulator-boot-on;
93a033588eSNishanth Menon	};
94a033588eSNishanth Menon
95a033588eSNishanth Menon	vcc_3v3_sys: regulator-2 {
96a033588eSNishanth Menon		/* output of LM61460-Q1 */
97a033588eSNishanth Menon		compatible = "regulator-fixed";
98a033588eSNishanth Menon		regulator-name = "vcc_3v3_sys";
99a033588eSNishanth Menon		regulator-min-microvolt = <3300000>;
100a033588eSNishanth Menon		regulator-max-microvolt = <3300000>;
101a033588eSNishanth Menon		vin-supply = <&vmain_pd>;
102a033588eSNishanth Menon		regulator-always-on;
103a033588eSNishanth Menon		regulator-boot-on;
104a033588eSNishanth Menon	};
105a033588eSNishanth Menon
106d19a66aeSVignesh Raghavendra	vdd_mmc1: regulator-3 {
107d19a66aeSVignesh Raghavendra		/* TPS22918DBVR */
108d19a66aeSVignesh Raghavendra		compatible = "regulator-fixed";
109d19a66aeSVignesh Raghavendra		regulator-name = "vdd_mmc1";
110d19a66aeSVignesh Raghavendra		regulator-min-microvolt = <3300000>;
111d19a66aeSVignesh Raghavendra		regulator-max-microvolt = <3300000>;
112d19a66aeSVignesh Raghavendra		regulator-boot-on;
113d19a66aeSVignesh Raghavendra		enable-active-high;
114d19a66aeSVignesh Raghavendra		vin-supply = <&vcc_3v3_sys>;
115d19a66aeSVignesh Raghavendra		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
116d19a66aeSVignesh Raghavendra	};
117d19a66aeSVignesh Raghavendra
118d19a66aeSVignesh Raghavendra	vdd_sd_dv: regulator-4 {
119d19a66aeSVignesh Raghavendra		/* Output of TLV71033 */
120d19a66aeSVignesh Raghavendra		compatible = "regulator-gpio";
121d19a66aeSVignesh Raghavendra		regulator-name = "tlv71033";
122d19a66aeSVignesh Raghavendra		pinctrl-names = "default";
123d19a66aeSVignesh Raghavendra		pinctrl-0 = <&vdd_sd_dv_pins_default>;
124d19a66aeSVignesh Raghavendra		regulator-min-microvolt = <1800000>;
125d19a66aeSVignesh Raghavendra		regulator-max-microvolt = <3300000>;
126d19a66aeSVignesh Raghavendra		regulator-boot-on;
127d19a66aeSVignesh Raghavendra		vin-supply = <&vcc_5v0>;
128d19a66aeSVignesh Raghavendra		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
129d19a66aeSVignesh Raghavendra		states = <1800000 0x0>,
130d19a66aeSVignesh Raghavendra			 <3300000 0x1>;
131d19a66aeSVignesh Raghavendra	};
132d19a66aeSVignesh Raghavendra
133a033588eSNishanth Menon	leds {
134a033588eSNishanth Menon		compatible = "gpio-leds";
135a033588eSNishanth Menon		pinctrl-names = "default";
136a033588eSNishanth Menon		pinctrl-0 = <&usr_led_pins_default>;
137a033588eSNishanth Menon
138a033588eSNishanth Menon		led-0 {
139a033588eSNishanth Menon			label = "am62-sk:green:heartbeat";
140a033588eSNishanth Menon			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
141a033588eSNishanth Menon			linux,default-trigger = "heartbeat";
142a033588eSNishanth Menon			function = LED_FUNCTION_HEARTBEAT;
143a033588eSNishanth Menon			default-state = "off";
144a033588eSNishanth Menon		};
145a033588eSNishanth Menon	};
146a033588eSNishanth Menon};
147a033588eSNishanth Menon
148a033588eSNishanth Menon&main_pmx0 {
149a033588eSNishanth Menon	main_uart0_pins_default: main-uart0-pins-default {
150a033588eSNishanth Menon		pinctrl-single,pins = <
151a033588eSNishanth Menon			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
152a033588eSNishanth Menon			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
153a033588eSNishanth Menon		>;
154a033588eSNishanth Menon	};
155a033588eSNishanth Menon
156a033588eSNishanth Menon	main_i2c0_pins_default: main-i2c0-pins-default {
157a033588eSNishanth Menon		pinctrl-single,pins = <
158a033588eSNishanth Menon			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
159a033588eSNishanth Menon			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
160a033588eSNishanth Menon		>;
161a033588eSNishanth Menon	};
162a033588eSNishanth Menon
163a033588eSNishanth Menon	main_i2c1_pins_default: main-i2c1-pins-default {
164a033588eSNishanth Menon		pinctrl-single,pins = <
165a033588eSNishanth Menon			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
166a033588eSNishanth Menon			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
167a033588eSNishanth Menon		>;
168a033588eSNishanth Menon	};
169a033588eSNishanth Menon
170d19a66aeSVignesh Raghavendra	main_i2c2_pins_default: main-i2c2-pins-default {
171d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
172d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
173d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
174d19a66aeSVignesh Raghavendra		>;
175d19a66aeSVignesh Raghavendra	};
176d19a66aeSVignesh Raghavendra
177d19a66aeSVignesh Raghavendra	main_mmc0_pins_default: main-mmc0-pins-default {
178d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
179d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
180d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
181d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
182d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
183d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
184d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
185d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
186d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
187d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
188d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
189d19a66aeSVignesh Raghavendra		>;
190d19a66aeSVignesh Raghavendra	};
191d19a66aeSVignesh Raghavendra
192d19a66aeSVignesh Raghavendra	main_mmc1_pins_default: main-mmc1-pins-default {
193d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
194d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
195d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
196d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
197d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
198d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
199d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
200d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
201d19a66aeSVignesh Raghavendra		>;
202d19a66aeSVignesh Raghavendra	};
203d19a66aeSVignesh Raghavendra
204a033588eSNishanth Menon	usr_led_pins_default: usr-led-pins-default {
205a033588eSNishanth Menon		pinctrl-single,pins = <
206a033588eSNishanth Menon			AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
207a033588eSNishanth Menon		>;
208a033588eSNishanth Menon	};
209d19a66aeSVignesh Raghavendra
210d19a66aeSVignesh Raghavendra	main_mdio1_pins_default: main-mdio1-pins-default {
211d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
212d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
213d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
214d19a66aeSVignesh Raghavendra		>;
215d19a66aeSVignesh Raghavendra	};
216d19a66aeSVignesh Raghavendra
217d19a66aeSVignesh Raghavendra	main_rgmii1_pins_default: main-rgmii1-pins-default {
218d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
219d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
220d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
221d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
222d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
223d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
224d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
225d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
226d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
227d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
228d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
229d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
230d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
231d19a66aeSVignesh Raghavendra		>;
232d19a66aeSVignesh Raghavendra	};
233d19a66aeSVignesh Raghavendra
234d19a66aeSVignesh Raghavendra	main_rgmii2_pins_default: main-rgmii2-pins-default {
235d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
236d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
237d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
238d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
239d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
240d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
241d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
242d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
243d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
244d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
245d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
246d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
247d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
248d19a66aeSVignesh Raghavendra		>;
249d19a66aeSVignesh Raghavendra	};
250d19a66aeSVignesh Raghavendra
251d19a66aeSVignesh Raghavendra	ospi0_pins_default: ospi0-pins-default {
252d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
253d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
254d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
255d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
256d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
257d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
258d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
259d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
260d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
261d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
262d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
263d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
264d19a66aeSVignesh Raghavendra		>;
265d19a66aeSVignesh Raghavendra	};
266d19a66aeSVignesh Raghavendra
267d19a66aeSVignesh Raghavendra	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
268d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
269d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
270d19a66aeSVignesh Raghavendra		>;
271d19a66aeSVignesh Raghavendra	};
272d19a66aeSVignesh Raghavendra
273d19a66aeSVignesh Raghavendra	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
274d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
275d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
276d19a66aeSVignesh Raghavendra		>;
277d19a66aeSVignesh Raghavendra	};
278a033588eSNishanth Menon};
279a033588eSNishanth Menon
280a033588eSNishanth Menon&wkup_uart0 {
281a033588eSNishanth Menon	/* WKUP UART0 is used by DM firmware */
282a033588eSNishanth Menon	status = "reserved";
283a033588eSNishanth Menon};
284a033588eSNishanth Menon
285a033588eSNishanth Menon&mcu_uart0 {
286a033588eSNishanth Menon	status = "disabled";
287a033588eSNishanth Menon};
288a033588eSNishanth Menon
289a033588eSNishanth Menon&main_uart0 {
290a033588eSNishanth Menon	pinctrl-names = "default";
291a033588eSNishanth Menon	pinctrl-0 = <&main_uart0_pins_default>;
292a033588eSNishanth Menon};
293a033588eSNishanth Menon
294a033588eSNishanth Menon&main_uart1 {
295a033588eSNishanth Menon	/* Main UART1 is used by TIFS firmware */
296a033588eSNishanth Menon	status = "reserved";
297a033588eSNishanth Menon};
298a033588eSNishanth Menon
299a033588eSNishanth Menon&main_uart2 {
300a033588eSNishanth Menon	status = "disabled";
301a033588eSNishanth Menon};
302a033588eSNishanth Menon
303a033588eSNishanth Menon&main_uart3 {
304a033588eSNishanth Menon	status = "disabled";
305a033588eSNishanth Menon};
306a033588eSNishanth Menon
307a033588eSNishanth Menon&main_uart4 {
308a033588eSNishanth Menon	status = "disabled";
309a033588eSNishanth Menon};
310a033588eSNishanth Menon
311a033588eSNishanth Menon&main_uart5 {
312a033588eSNishanth Menon	status = "disabled";
313a033588eSNishanth Menon};
314a033588eSNishanth Menon
315a033588eSNishanth Menon&main_uart6 {
316a033588eSNishanth Menon	status = "disabled";
317a033588eSNishanth Menon};
318a033588eSNishanth Menon
319a033588eSNishanth Menon&mcu_i2c0 {
320a033588eSNishanth Menon	status = "disabled";
321a033588eSNishanth Menon};
322a033588eSNishanth Menon
323a033588eSNishanth Menon&wkup_i2c0 {
324a033588eSNishanth Menon	status = "disabled";
325a033588eSNishanth Menon};
326a033588eSNishanth Menon
327a033588eSNishanth Menon&main_i2c0 {
328a033588eSNishanth Menon	pinctrl-names = "default";
329a033588eSNishanth Menon	pinctrl-0 = <&main_i2c0_pins_default>;
330a033588eSNishanth Menon	clock-frequency = <400000>;
331a033588eSNishanth Menon};
332a033588eSNishanth Menon
333a033588eSNishanth Menon&main_i2c1 {
334a033588eSNishanth Menon	pinctrl-names = "default";
335a033588eSNishanth Menon	pinctrl-0 = <&main_i2c1_pins_default>;
336a033588eSNishanth Menon	clock-frequency = <400000>;
337d19a66aeSVignesh Raghavendra
338d19a66aeSVignesh Raghavendra	exp1: gpio@22 {
339d19a66aeSVignesh Raghavendra		compatible = "ti,tca6424";
340d19a66aeSVignesh Raghavendra		reg = <0x22>;
341d19a66aeSVignesh Raghavendra		gpio-controller;
342d19a66aeSVignesh Raghavendra		#gpio-cells = <2>;
343d19a66aeSVignesh Raghavendra		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
344d19a66aeSVignesh Raghavendra				   "PRU_DETECT", "MMC1_SD_EN",
345d19a66aeSVignesh Raghavendra				   "VPP_LDO_EN", "EXP_PS_3V3_En",
346d19a66aeSVignesh Raghavendra				   "EXP_PS_5V0_En", "EXP_HAT_DETECT",
347d19a66aeSVignesh Raghavendra				   "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
348d19a66aeSVignesh Raghavendra				   "UART1_FET_BUF_EN", "WL_LT_EN",
349d19a66aeSVignesh Raghavendra				   "GPIO_HDMI_RSTn", "CSI_GPIO1",
350d19a66aeSVignesh Raghavendra				   "CSI_GPIO2", "PRU_3V3_EN",
351d19a66aeSVignesh Raghavendra				   "HDMI_INTn", "TEST_GPIO2",
352d19a66aeSVignesh Raghavendra				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
353d19a66aeSVignesh Raghavendra				   "MCASP1_FET_SEL", "UART1_FET_SEL",
354d19a66aeSVignesh Raghavendra				   "TSINT#", "IO_EXP_TEST_LED";
355d19a66aeSVignesh Raghavendra
356d19a66aeSVignesh Raghavendra		interrupt-parent = <&main_gpio1>;
357d19a66aeSVignesh Raghavendra		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
358d19a66aeSVignesh Raghavendra		interrupt-controller;
359d19a66aeSVignesh Raghavendra		#interrupt-cells = <2>;
360d19a66aeSVignesh Raghavendra
361d19a66aeSVignesh Raghavendra		pinctrl-names = "default";
362d19a66aeSVignesh Raghavendra		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
363d19a66aeSVignesh Raghavendra	};
364a033588eSNishanth Menon};
365a033588eSNishanth Menon
366a033588eSNishanth Menon&main_i2c2 {
367a033588eSNishanth Menon	status = "disabled";
368a033588eSNishanth Menon};
369a033588eSNishanth Menon
370a033588eSNishanth Menon&main_i2c3 {
371a033588eSNishanth Menon	status = "disabled";
372a033588eSNishanth Menon};
373a033588eSNishanth Menon
374d19a66aeSVignesh Raghavendra&sdhci0 {
375d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
376d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mmc0_pins_default>;
377d19a66aeSVignesh Raghavendra	ti,driver-strength-ohm = <50>;
378d19a66aeSVignesh Raghavendra	disable-wp;
379d19a66aeSVignesh Raghavendra};
380d19a66aeSVignesh Raghavendra
381d19a66aeSVignesh Raghavendra&sdhci1 {
382d19a66aeSVignesh Raghavendra	/* SD/MMC */
383d19a66aeSVignesh Raghavendra	vmmc-supply = <&vdd_mmc1>;
384d19a66aeSVignesh Raghavendra	vqmmc-supply = <&vdd_sd_dv>;
385d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
386d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mmc1_pins_default>;
387d19a66aeSVignesh Raghavendra	ti,driver-strength-ohm = <50>;
388d19a66aeSVignesh Raghavendra	disable-wp;
389d19a66aeSVignesh Raghavendra};
390d19a66aeSVignesh Raghavendra
391d19a66aeSVignesh Raghavendra&cpsw3g {
392d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
393d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mdio1_pins_default
394d19a66aeSVignesh Raghavendra		     &main_rgmii1_pins_default
395d19a66aeSVignesh Raghavendra		     &main_rgmii2_pins_default>;
396d19a66aeSVignesh Raghavendra};
397d19a66aeSVignesh Raghavendra
398d19a66aeSVignesh Raghavendra&cpsw_port1 {
399d19a66aeSVignesh Raghavendra	phy-mode = "rgmii-rxid";
400d19a66aeSVignesh Raghavendra	phy-handle = <&cpsw3g_phy0>;
401d19a66aeSVignesh Raghavendra};
402d19a66aeSVignesh Raghavendra
403d19a66aeSVignesh Raghavendra&cpsw_port2 {
404d19a66aeSVignesh Raghavendra	phy-mode = "rgmii-rxid";
405d19a66aeSVignesh Raghavendra	phy-handle = <&cpsw3g_phy1>;
406d19a66aeSVignesh Raghavendra};
407d19a66aeSVignesh Raghavendra
408d19a66aeSVignesh Raghavendra&cpsw3g_mdio {
409d19a66aeSVignesh Raghavendra	cpsw3g_phy0: ethernet-phy@0 {
410d19a66aeSVignesh Raghavendra		reg = <0>;
411d19a66aeSVignesh Raghavendra		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
412d19a66aeSVignesh Raghavendra		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
413d19a66aeSVignesh Raghavendra		ti,min-output-impedance;
414d19a66aeSVignesh Raghavendra	};
415d19a66aeSVignesh Raghavendra
416d19a66aeSVignesh Raghavendra	cpsw3g_phy1: ethernet-phy@1 {
417d19a66aeSVignesh Raghavendra		reg = <1>;
418d19a66aeSVignesh Raghavendra		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
419d19a66aeSVignesh Raghavendra		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
420d19a66aeSVignesh Raghavendra		ti,min-output-impedance;
421d19a66aeSVignesh Raghavendra	};
422d19a66aeSVignesh Raghavendra};
423d19a66aeSVignesh Raghavendra
424a033588eSNishanth Menon&mailbox0_cluster0 {
425a033588eSNishanth Menon	mbox_m4_0: mbox-m4-0 {
426a033588eSNishanth Menon		ti,mbox-rx = <0 0 0>;
427a033588eSNishanth Menon		ti,mbox-tx = <1 0 0>;
428a033588eSNishanth Menon	};
429a033588eSNishanth Menon};
430d19a66aeSVignesh Raghavendra
431d19a66aeSVignesh Raghavendra&ospi0 {
432d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
433d19a66aeSVignesh Raghavendra	pinctrl-0 = <&ospi0_pins_default>;
434d19a66aeSVignesh Raghavendra
435d19a66aeSVignesh Raghavendra	flash@0{
436d19a66aeSVignesh Raghavendra		compatible = "jedec,spi-nor";
437d19a66aeSVignesh Raghavendra		reg = <0x0>;
438d19a66aeSVignesh Raghavendra		spi-tx-bus-width = <8>;
439d19a66aeSVignesh Raghavendra		spi-rx-bus-width = <8>;
440d19a66aeSVignesh Raghavendra		spi-max-frequency = <25000000>;
441d19a66aeSVignesh Raghavendra		cdns,tshsl-ns = <60>;
442d19a66aeSVignesh Raghavendra		cdns,tsd2d-ns = <60>;
443d19a66aeSVignesh Raghavendra		cdns,tchsh-ns = <60>;
444d19a66aeSVignesh Raghavendra		cdns,tslch-ns = <60>;
445d19a66aeSVignesh Raghavendra		cdns,read-delay = <4>;
446d19a66aeSVignesh Raghavendra
447d19a66aeSVignesh Raghavendra		partitions {
448d19a66aeSVignesh Raghavendra			compatible = "fixed-partitions";
449d19a66aeSVignesh Raghavendra			#address-cells = <1>;
450d19a66aeSVignesh Raghavendra			#size-cells = <1>;
451d19a66aeSVignesh Raghavendra
452d19a66aeSVignesh Raghavendra			partition@0 {
453d19a66aeSVignesh Raghavendra				label = "ospi.tiboot3";
454d19a66aeSVignesh Raghavendra				reg = <0x0 0x80000>;
455d19a66aeSVignesh Raghavendra			};
456d19a66aeSVignesh Raghavendra
457d19a66aeSVignesh Raghavendra			partition@80000 {
458d19a66aeSVignesh Raghavendra				label = "ospi.tispl";
459d19a66aeSVignesh Raghavendra				reg = <0x80000 0x200000>;
460d19a66aeSVignesh Raghavendra			};
461d19a66aeSVignesh Raghavendra
462d19a66aeSVignesh Raghavendra			partition@280000 {
463d19a66aeSVignesh Raghavendra				label = "ospi.u-boot";
464d19a66aeSVignesh Raghavendra				reg = <0x280000 0x400000>;
465d19a66aeSVignesh Raghavendra			};
466d19a66aeSVignesh Raghavendra
467d19a66aeSVignesh Raghavendra			partition@680000 {
468d19a66aeSVignesh Raghavendra				label = "ospi.env";
469d19a66aeSVignesh Raghavendra				reg = <0x680000 0x40000>;
470d19a66aeSVignesh Raghavendra			};
471d19a66aeSVignesh Raghavendra
472d19a66aeSVignesh Raghavendra			partition@6c0000 {
473d19a66aeSVignesh Raghavendra				label = "ospi.env.backup";
474d19a66aeSVignesh Raghavendra				reg = <0x6c0000 0x40000>;
475d19a66aeSVignesh Raghavendra			};
476d19a66aeSVignesh Raghavendra
477d19a66aeSVignesh Raghavendra			partition@800000 {
478d19a66aeSVignesh Raghavendra				label = "ospi.rootfs";
479d19a66aeSVignesh Raghavendra				reg = <0x800000 0x37c0000>;
480d19a66aeSVignesh Raghavendra			};
481d19a66aeSVignesh Raghavendra
482d19a66aeSVignesh Raghavendra			partition@3fc0000 {
483d19a66aeSVignesh Raghavendra				label = "ospi.phypattern";
484d19a66aeSVignesh Raghavendra				reg = <0x3fc0000 0x40000>;
485d19a66aeSVignesh Raghavendra			};
486d19a66aeSVignesh Raghavendra		};
487d19a66aeSVignesh Raghavendra	};
488d19a66aeSVignesh Raghavendra};
489bd67e1beSVignesh Raghavendra
490bd67e1beSVignesh Raghavendra&ecap0 {
491bd67e1beSVignesh Raghavendra	status = "disabled";
492bd67e1beSVignesh Raghavendra};
493bd67e1beSVignesh Raghavendra
494bd67e1beSVignesh Raghavendra&ecap1 {
495bd67e1beSVignesh Raghavendra	status = "disabled";
496bd67e1beSVignesh Raghavendra};
497bd67e1beSVignesh Raghavendra
498bd67e1beSVignesh Raghavendra&ecap2 {
499bd67e1beSVignesh Raghavendra	status = "disabled";
500bd67e1beSVignesh Raghavendra};
5012492a974SAswath Govindraju
5022492a974SAswath Govindraju&main_mcan0 {
5032492a974SAswath Govindraju	status = "disabled";
5042492a974SAswath Govindraju};
505*acf3fdc8SGeorgi Vlaev
506*acf3fdc8SGeorgi Vlaev&epwm0 {
507*acf3fdc8SGeorgi Vlaev	status = "disabled";
508*acf3fdc8SGeorgi Vlaev};
509*acf3fdc8SGeorgi Vlaev
510*acf3fdc8SGeorgi Vlaev&epwm1 {
511*acf3fdc8SGeorgi Vlaev	status = "disabled";
512*acf3fdc8SGeorgi Vlaev};
513*acf3fdc8SGeorgi Vlaev
514*acf3fdc8SGeorgi Vlaev&epwm2 {
515*acf3fdc8SGeorgi Vlaev	status = "disabled";
516*acf3fdc8SGeorgi Vlaev};
517