1a033588eSNishanth Menon// SPDX-License-Identifier: GPL-2.0 2a033588eSNishanth Menon/* 3a033588eSNishanth Menon * AM625 SK: https://www.ti.com/lit/zip/sprr448 4a033588eSNishanth Menon * 5a033588eSNishanth Menon * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ 6a033588eSNishanth Menon */ 7a033588eSNishanth Menon 8a033588eSNishanth Menon/dts-v1/; 9a033588eSNishanth Menon 10a8415814SAnand Gadiyar#include "k3-am62x-sk-common.dtsi" 11a033588eSNishanth Menon 12a033588eSNishanth Menon/ { 13a033588eSNishanth Menon compatible = "ti,am625-sk", "ti,am625"; 14a033588eSNishanth Menon model = "Texas Instruments AM625 SK"; 15a033588eSNishanth Menon 161313edfdSVibhore Vardhan opp-table { 171313edfdSVibhore Vardhan /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ 181313edfdSVibhore Vardhan opp-1400000000 { 191313edfdSVibhore Vardhan opp-hz = /bits/ 64 <1400000000>; 201313edfdSVibhore Vardhan opp-supported-hw = <0x01 0x0004>; 211313edfdSVibhore Vardhan clock-latency-ns = <6000000>; 221313edfdSVibhore Vardhan }; 231313edfdSVibhore Vardhan }; 241313edfdSVibhore Vardhan 25a033588eSNishanth Menon memory@80000000 { 26a033588eSNishanth Menon device_type = "memory"; 27a033588eSNishanth Menon /* 2G RAM */ 28a033588eSNishanth Menon reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 29a033588eSNishanth Menon 30a033588eSNishanth Menon }; 31a033588eSNishanth Menon 32a033588eSNishanth Menon vmain_pd: regulator-0 { 33a033588eSNishanth Menon /* TPS65988 PD CONTROLLER OUTPUT */ 34a033588eSNishanth Menon compatible = "regulator-fixed"; 35a033588eSNishanth Menon regulator-name = "vmain_pd"; 36a033588eSNishanth Menon regulator-min-microvolt = <5000000>; 37a033588eSNishanth Menon regulator-max-microvolt = <5000000>; 38a033588eSNishanth Menon regulator-always-on; 39a033588eSNishanth Menon regulator-boot-on; 40a033588eSNishanth Menon }; 41a033588eSNishanth Menon 42a033588eSNishanth Menon vcc_5v0: regulator-1 { 43a033588eSNishanth Menon /* Output of LM34936 */ 44a033588eSNishanth Menon compatible = "regulator-fixed"; 45a033588eSNishanth Menon regulator-name = "vcc_5v0"; 46a033588eSNishanth Menon regulator-min-microvolt = <5000000>; 47a033588eSNishanth Menon regulator-max-microvolt = <5000000>; 48a033588eSNishanth Menon vin-supply = <&vmain_pd>; 49a033588eSNishanth Menon regulator-always-on; 50a033588eSNishanth Menon regulator-boot-on; 51a033588eSNishanth Menon }; 52a033588eSNishanth Menon 53a033588eSNishanth Menon vcc_3v3_sys: regulator-2 { 54a033588eSNishanth Menon /* output of LM61460-Q1 */ 55a033588eSNishanth Menon compatible = "regulator-fixed"; 56a033588eSNishanth Menon regulator-name = "vcc_3v3_sys"; 57a033588eSNishanth Menon regulator-min-microvolt = <3300000>; 58a033588eSNishanth Menon regulator-max-microvolt = <3300000>; 59a033588eSNishanth Menon vin-supply = <&vmain_pd>; 60a033588eSNishanth Menon regulator-always-on; 61a033588eSNishanth Menon regulator-boot-on; 62a033588eSNishanth Menon }; 63a033588eSNishanth Menon 64d19a66aeSVignesh Raghavendra vdd_mmc1: regulator-3 { 65d19a66aeSVignesh Raghavendra /* TPS22918DBVR */ 66d19a66aeSVignesh Raghavendra compatible = "regulator-fixed"; 67d19a66aeSVignesh Raghavendra regulator-name = "vdd_mmc1"; 68d19a66aeSVignesh Raghavendra regulator-min-microvolt = <3300000>; 69d19a66aeSVignesh Raghavendra regulator-max-microvolt = <3300000>; 70d19a66aeSVignesh Raghavendra regulator-boot-on; 71d19a66aeSVignesh Raghavendra enable-active-high; 72d19a66aeSVignesh Raghavendra vin-supply = <&vcc_3v3_sys>; 73d19a66aeSVignesh Raghavendra gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 74d19a66aeSVignesh Raghavendra }; 75d19a66aeSVignesh Raghavendra 76d19a66aeSVignesh Raghavendra vdd_sd_dv: regulator-4 { 77d19a66aeSVignesh Raghavendra /* Output of TLV71033 */ 78d19a66aeSVignesh Raghavendra compatible = "regulator-gpio"; 79d19a66aeSVignesh Raghavendra regulator-name = "tlv71033"; 80d19a66aeSVignesh Raghavendra pinctrl-names = "default"; 81d19a66aeSVignesh Raghavendra pinctrl-0 = <&vdd_sd_dv_pins_default>; 82d19a66aeSVignesh Raghavendra regulator-min-microvolt = <1800000>; 83d19a66aeSVignesh Raghavendra regulator-max-microvolt = <3300000>; 84d19a66aeSVignesh Raghavendra regulator-boot-on; 85d19a66aeSVignesh Raghavendra vin-supply = <&vcc_5v0>; 86d19a66aeSVignesh Raghavendra gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; 87d19a66aeSVignesh Raghavendra states = <1800000 0x0>, 88d19a66aeSVignesh Raghavendra <3300000 0x1>; 89d19a66aeSVignesh Raghavendra }; 90b94b4371SJai Luthra 91b94b4371SJai Luthra vcc_1v8: regulator-5 { 92b94b4371SJai Luthra /* output of TPS6282518DMQ */ 93b94b4371SJai Luthra compatible = "regulator-fixed"; 94b94b4371SJai Luthra regulator-name = "vcc_1v8"; 95b94b4371SJai Luthra regulator-min-microvolt = <1800000>; 96b94b4371SJai Luthra regulator-max-microvolt = <1800000>; 97b94b4371SJai Luthra vin-supply = <&vcc_3v3_sys>; 98b94b4371SJai Luthra regulator-always-on; 99b94b4371SJai Luthra regulator-boot-on; 100b94b4371SJai Luthra }; 101a033588eSNishanth Menon}; 102a033588eSNishanth Menon 103a033588eSNishanth Menon&main_pmx0 { 104*a4956811STony Lindgren main_rgmii2_pins_default: main-rgmii2-default-pins { 105d19a66aeSVignesh Raghavendra pinctrl-single,pins = < 106d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ 107d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ 108d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ 109d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ 110d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ 111d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ 112d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ 113d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ 114d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ 115d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ 116d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ 117d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ 118d19a66aeSVignesh Raghavendra >; 119d19a66aeSVignesh Raghavendra }; 120d19a66aeSVignesh Raghavendra 121*a4956811STony Lindgren ospi0_pins_default: ospi0-default-pins { 122d19a66aeSVignesh Raghavendra pinctrl-single,pins = < 123d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ 124d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ 125d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ 126d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ 127d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ 128d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ 129d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ 130d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ 131d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ 132d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ 133d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ 134d19a66aeSVignesh Raghavendra >; 135d19a66aeSVignesh Raghavendra }; 136d19a66aeSVignesh Raghavendra 137*a4956811STony Lindgren vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 138d19a66aeSVignesh Raghavendra pinctrl-single,pins = < 139d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ 140d19a66aeSVignesh Raghavendra >; 141d19a66aeSVignesh Raghavendra }; 142d19a66aeSVignesh Raghavendra 143*a4956811STony Lindgren main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { 144d19a66aeSVignesh Raghavendra pinctrl-single,pins = < 145d19a66aeSVignesh Raghavendra AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ 146d19a66aeSVignesh Raghavendra >; 147d19a66aeSVignesh Raghavendra }; 148a033588eSNishanth Menon}; 149a033588eSNishanth Menon 150a033588eSNishanth Menon&main_i2c1 { 151d19a66aeSVignesh Raghavendra exp1: gpio@22 { 152d19a66aeSVignesh Raghavendra compatible = "ti,tca6424"; 153d19a66aeSVignesh Raghavendra reg = <0x22>; 154d19a66aeSVignesh Raghavendra gpio-controller; 155d19a66aeSVignesh Raghavendra #gpio-cells = <2>; 156d19a66aeSVignesh Raghavendra gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 157d19a66aeSVignesh Raghavendra "PRU_DETECT", "MMC1_SD_EN", 158d19a66aeSVignesh Raghavendra "VPP_LDO_EN", "EXP_PS_3V3_En", 159d19a66aeSVignesh Raghavendra "EXP_PS_5V0_En", "EXP_HAT_DETECT", 160d19a66aeSVignesh Raghavendra "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", 161d19a66aeSVignesh Raghavendra "UART1_FET_BUF_EN", "WL_LT_EN", 162d19a66aeSVignesh Raghavendra "GPIO_HDMI_RSTn", "CSI_GPIO1", 163d19a66aeSVignesh Raghavendra "CSI_GPIO2", "PRU_3V3_EN", 1642c213d19SRoger Quadros "HDMI_INTn", "PD_I2C_IRQ", 165d19a66aeSVignesh Raghavendra "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", 166d19a66aeSVignesh Raghavendra "MCASP1_FET_SEL", "UART1_FET_SEL", 167d19a66aeSVignesh Raghavendra "TSINT#", "IO_EXP_TEST_LED"; 168d19a66aeSVignesh Raghavendra 169d19a66aeSVignesh Raghavendra interrupt-parent = <&main_gpio1>; 170d19a66aeSVignesh Raghavendra interrupts = <23 IRQ_TYPE_EDGE_FALLING>; 171d19a66aeSVignesh Raghavendra interrupt-controller; 172d19a66aeSVignesh Raghavendra #interrupt-cells = <2>; 173d19a66aeSVignesh Raghavendra 174d19a66aeSVignesh Raghavendra pinctrl-names = "default"; 175d19a66aeSVignesh Raghavendra pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; 176d19a66aeSVignesh Raghavendra }; 177a033588eSNishanth Menon}; 178a033588eSNishanth Menon 179d19a66aeSVignesh Raghavendra&sdhci1 { 180d19a66aeSVignesh Raghavendra vmmc-supply = <&vdd_mmc1>; 181d19a66aeSVignesh Raghavendra vqmmc-supply = <&vdd_sd_dv>; 182d19a66aeSVignesh Raghavendra}; 183d19a66aeSVignesh Raghavendra 184d19a66aeSVignesh Raghavendra&cpsw3g { 185d19a66aeSVignesh Raghavendra pinctrl-names = "default"; 186875aad10SNishanth Menon pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; 187d19a66aeSVignesh Raghavendra}; 188d19a66aeSVignesh Raghavendra 189d19a66aeSVignesh Raghavendra&cpsw_port2 { 190d19a66aeSVignesh Raghavendra phy-mode = "rgmii-rxid"; 191d19a66aeSVignesh Raghavendra phy-handle = <&cpsw3g_phy1>; 192d19a66aeSVignesh Raghavendra}; 193d19a66aeSVignesh Raghavendra 194d19a66aeSVignesh Raghavendra&cpsw3g_mdio { 195d19a66aeSVignesh Raghavendra cpsw3g_phy1: ethernet-phy@1 { 196d19a66aeSVignesh Raghavendra reg = <1>; 197d19a66aeSVignesh Raghavendra ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 198d19a66aeSVignesh Raghavendra ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 199d19a66aeSVignesh Raghavendra ti,min-output-impedance; 200d19a66aeSVignesh Raghavendra }; 201d19a66aeSVignesh Raghavendra}; 202d19a66aeSVignesh Raghavendra 203a033588eSNishanth Menon&mailbox0_cluster0 { 204a033588eSNishanth Menon mbox_m4_0: mbox-m4-0 { 205a033588eSNishanth Menon ti,mbox-rx = <0 0 0>; 206a033588eSNishanth Menon ti,mbox-tx = <1 0 0>; 207a033588eSNishanth Menon }; 208a033588eSNishanth Menon}; 209d19a66aeSVignesh Raghavendra 210d19a66aeSVignesh Raghavendra&ospi0 { 211b0ca32e8SAndrew Davis status = "okay"; 212d19a66aeSVignesh Raghavendra pinctrl-names = "default"; 213d19a66aeSVignesh Raghavendra pinctrl-0 = <&ospi0_pins_default>; 214d19a66aeSVignesh Raghavendra 215d19a66aeSVignesh Raghavendra flash@0 { 216d19a66aeSVignesh Raghavendra compatible = "jedec,spi-nor"; 217d19a66aeSVignesh Raghavendra reg = <0x0>; 218d19a66aeSVignesh Raghavendra spi-tx-bus-width = <8>; 219d19a66aeSVignesh Raghavendra spi-rx-bus-width = <8>; 220d19a66aeSVignesh Raghavendra spi-max-frequency = <25000000>; 221d19a66aeSVignesh Raghavendra cdns,tshsl-ns = <60>; 222d19a66aeSVignesh Raghavendra cdns,tsd2d-ns = <60>; 223d19a66aeSVignesh Raghavendra cdns,tchsh-ns = <60>; 224d19a66aeSVignesh Raghavendra cdns,tslch-ns = <60>; 225d19a66aeSVignesh Raghavendra cdns,read-delay = <4>; 226d19a66aeSVignesh Raghavendra 227d19a66aeSVignesh Raghavendra partitions { 228d19a66aeSVignesh Raghavendra compatible = "fixed-partitions"; 229d19a66aeSVignesh Raghavendra #address-cells = <1>; 230d19a66aeSVignesh Raghavendra #size-cells = <1>; 231d19a66aeSVignesh Raghavendra 232d19a66aeSVignesh Raghavendra partition@0 { 233d19a66aeSVignesh Raghavendra label = "ospi.tiboot3"; 234d19a66aeSVignesh Raghavendra reg = <0x0 0x80000>; 235d19a66aeSVignesh Raghavendra }; 236d19a66aeSVignesh Raghavendra 237d19a66aeSVignesh Raghavendra partition@80000 { 238d19a66aeSVignesh Raghavendra label = "ospi.tispl"; 239d19a66aeSVignesh Raghavendra reg = <0x80000 0x200000>; 240d19a66aeSVignesh Raghavendra }; 241d19a66aeSVignesh Raghavendra 242d19a66aeSVignesh Raghavendra partition@280000 { 243d19a66aeSVignesh Raghavendra label = "ospi.u-boot"; 244d19a66aeSVignesh Raghavendra reg = <0x280000 0x400000>; 245d19a66aeSVignesh Raghavendra }; 246d19a66aeSVignesh Raghavendra 247d19a66aeSVignesh Raghavendra partition@680000 { 248d19a66aeSVignesh Raghavendra label = "ospi.env"; 249d19a66aeSVignesh Raghavendra reg = <0x680000 0x40000>; 250d19a66aeSVignesh Raghavendra }; 251d19a66aeSVignesh Raghavendra 252d19a66aeSVignesh Raghavendra partition@6c0000 { 253d19a66aeSVignesh Raghavendra label = "ospi.env.backup"; 254d19a66aeSVignesh Raghavendra reg = <0x6c0000 0x40000>; 255d19a66aeSVignesh Raghavendra }; 256d19a66aeSVignesh Raghavendra 257d19a66aeSVignesh Raghavendra partition@800000 { 258d19a66aeSVignesh Raghavendra label = "ospi.rootfs"; 259d19a66aeSVignesh Raghavendra reg = <0x800000 0x37c0000>; 260d19a66aeSVignesh Raghavendra }; 261d19a66aeSVignesh Raghavendra 262d19a66aeSVignesh Raghavendra partition@3fc0000 { 263d19a66aeSVignesh Raghavendra label = "ospi.phypattern"; 264d19a66aeSVignesh Raghavendra reg = <0x3fc0000 0x40000>; 265d19a66aeSVignesh Raghavendra }; 266d19a66aeSVignesh Raghavendra }; 267d19a66aeSVignesh Raghavendra }; 268d19a66aeSVignesh Raghavendra}; 269b94b4371SJai Luthra 270b94b4371SJai Luthra&tlv320aic3106 { 271b94b4371SJai Luthra DVDD-supply = <&vcc_1v8>; 272b94b4371SJai Luthra}; 273