1a033588eSNishanth Menon// SPDX-License-Identifier: GPL-2.0
2a033588eSNishanth Menon/*
3a033588eSNishanth Menon * AM625 SK: https://www.ti.com/lit/zip/sprr448
4a033588eSNishanth Menon *
5a033588eSNishanth Menon * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
6a033588eSNishanth Menon */
7a033588eSNishanth Menon
8a033588eSNishanth Menon/dts-v1/;
9a033588eSNishanth Menon
10a033588eSNishanth Menon#include <dt-bindings/leds/common.h>
11a033588eSNishanth Menon#include <dt-bindings/gpio/gpio.h>
12d19a66aeSVignesh Raghavendra#include <dt-bindings/net/ti-dp83867.h>
13a033588eSNishanth Menon#include "k3-am625.dtsi"
14a033588eSNishanth Menon
15a033588eSNishanth Menon/ {
16a033588eSNishanth Menon	compatible = "ti,am625-sk", "ti,am625";
17a033588eSNishanth Menon	model = "Texas Instruments AM625 SK";
18a033588eSNishanth Menon
19a033588eSNishanth Menon	aliases {
20a033588eSNishanth Menon		serial2 = &main_uart0;
21d19a66aeSVignesh Raghavendra		mmc0 = &sdhci0;
22d19a66aeSVignesh Raghavendra		mmc1 = &sdhci1;
23d19a66aeSVignesh Raghavendra		mmc2 = &sdhci2;
24d19a66aeSVignesh Raghavendra		spi0 = &ospi0;
25d19a66aeSVignesh Raghavendra		ethernet0 = &cpsw_port1;
26d19a66aeSVignesh Raghavendra		ethernet1 = &cpsw_port2;
27a033588eSNishanth Menon	};
28a033588eSNishanth Menon
29a033588eSNishanth Menon	chosen {
30a033588eSNishanth Menon		stdout-path = "serial2:115200n8";
31a033588eSNishanth Menon		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
32a033588eSNishanth Menon	};
33a033588eSNishanth Menon
34*1313edfdSVibhore Vardhan	opp-table {
35*1313edfdSVibhore Vardhan		/* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */
36*1313edfdSVibhore Vardhan		opp-1400000000 {
37*1313edfdSVibhore Vardhan			opp-hz = /bits/ 64 <1400000000>;
38*1313edfdSVibhore Vardhan			opp-supported-hw = <0x01 0x0004>;
39*1313edfdSVibhore Vardhan			clock-latency-ns = <6000000>;
40*1313edfdSVibhore Vardhan		};
41*1313edfdSVibhore Vardhan	};
42*1313edfdSVibhore Vardhan
43a033588eSNishanth Menon	memory@80000000 {
44a033588eSNishanth Menon		device_type = "memory";
45a033588eSNishanth Menon		/* 2G RAM */
46a033588eSNishanth Menon		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
47a033588eSNishanth Menon
48a033588eSNishanth Menon	};
49a033588eSNishanth Menon
50a033588eSNishanth Menon	reserved-memory {
51a033588eSNishanth Menon		#address-cells = <2>;
52a033588eSNishanth Menon		#size-cells = <2>;
53a033588eSNishanth Menon		ranges;
54a033588eSNishanth Menon
55e2788887SGuillaume La Roque		ramoops@9ca00000 {
56e2788887SGuillaume La Roque			compatible = "ramoops";
57e2788887SGuillaume La Roque			reg = <0x00 0x9ca00000 0x00 0x00100000>;
58e2788887SGuillaume La Roque			record-size = <0x8000>;
59e2788887SGuillaume La Roque			console-size = <0x8000>;
60e2788887SGuillaume La Roque			ftrace-size = <0x00>;
61e2788887SGuillaume La Roque			pmsg-size = <0x8000>;
62e2788887SGuillaume La Roque		};
63e2788887SGuillaume La Roque
64a033588eSNishanth Menon		secure_tfa_ddr: tfa@9e780000 {
65a033588eSNishanth Menon			reg = <0x00 0x9e780000 0x00 0x80000>;
66a033588eSNishanth Menon			alignment = <0x1000>;
67a033588eSNishanth Menon			no-map;
68a033588eSNishanth Menon		};
69a033588eSNishanth Menon
70a033588eSNishanth Menon		secure_ddr: optee@9e800000 {
71a033588eSNishanth Menon			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
72a033588eSNishanth Menon			alignment = <0x1000>;
73a033588eSNishanth Menon			no-map;
74a033588eSNishanth Menon		};
75a033588eSNishanth Menon
76a033588eSNishanth Menon		wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
77a033588eSNishanth Menon			compatible = "shared-dma-pool";
78a033588eSNishanth Menon			reg = <0x00 0x9db00000 0x00 0xc00000>;
79a033588eSNishanth Menon			no-map;
80a033588eSNishanth Menon		};
81a033588eSNishanth Menon	};
82a033588eSNishanth Menon
83a033588eSNishanth Menon	vmain_pd: regulator-0 {
84a033588eSNishanth Menon		/* TPS65988 PD CONTROLLER OUTPUT */
85a033588eSNishanth Menon		compatible = "regulator-fixed";
86a033588eSNishanth Menon		regulator-name = "vmain_pd";
87a033588eSNishanth Menon		regulator-min-microvolt = <5000000>;
88a033588eSNishanth Menon		regulator-max-microvolt = <5000000>;
89a033588eSNishanth Menon		regulator-always-on;
90a033588eSNishanth Menon		regulator-boot-on;
91a033588eSNishanth Menon	};
92a033588eSNishanth Menon
93a033588eSNishanth Menon	vcc_5v0: regulator-1 {
94a033588eSNishanth Menon		/* Output of LM34936 */
95a033588eSNishanth Menon		compatible = "regulator-fixed";
96a033588eSNishanth Menon		regulator-name = "vcc_5v0";
97a033588eSNishanth Menon		regulator-min-microvolt = <5000000>;
98a033588eSNishanth Menon		regulator-max-microvolt = <5000000>;
99a033588eSNishanth Menon		vin-supply = <&vmain_pd>;
100a033588eSNishanth Menon		regulator-always-on;
101a033588eSNishanth Menon		regulator-boot-on;
102a033588eSNishanth Menon	};
103a033588eSNishanth Menon
104a033588eSNishanth Menon	vcc_3v3_sys: regulator-2 {
105a033588eSNishanth Menon		/* output of LM61460-Q1 */
106a033588eSNishanth Menon		compatible = "regulator-fixed";
107a033588eSNishanth Menon		regulator-name = "vcc_3v3_sys";
108a033588eSNishanth Menon		regulator-min-microvolt = <3300000>;
109a033588eSNishanth Menon		regulator-max-microvolt = <3300000>;
110a033588eSNishanth Menon		vin-supply = <&vmain_pd>;
111a033588eSNishanth Menon		regulator-always-on;
112a033588eSNishanth Menon		regulator-boot-on;
113a033588eSNishanth Menon	};
114a033588eSNishanth Menon
115d19a66aeSVignesh Raghavendra	vdd_mmc1: regulator-3 {
116d19a66aeSVignesh Raghavendra		/* TPS22918DBVR */
117d19a66aeSVignesh Raghavendra		compatible = "regulator-fixed";
118d19a66aeSVignesh Raghavendra		regulator-name = "vdd_mmc1";
119d19a66aeSVignesh Raghavendra		regulator-min-microvolt = <3300000>;
120d19a66aeSVignesh Raghavendra		regulator-max-microvolt = <3300000>;
121d19a66aeSVignesh Raghavendra		regulator-boot-on;
122d19a66aeSVignesh Raghavendra		enable-active-high;
123d19a66aeSVignesh Raghavendra		vin-supply = <&vcc_3v3_sys>;
124d19a66aeSVignesh Raghavendra		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
125d19a66aeSVignesh Raghavendra	};
126d19a66aeSVignesh Raghavendra
127d19a66aeSVignesh Raghavendra	vdd_sd_dv: regulator-4 {
128d19a66aeSVignesh Raghavendra		/* Output of TLV71033 */
129d19a66aeSVignesh Raghavendra		compatible = "regulator-gpio";
130d19a66aeSVignesh Raghavendra		regulator-name = "tlv71033";
131d19a66aeSVignesh Raghavendra		pinctrl-names = "default";
132d19a66aeSVignesh Raghavendra		pinctrl-0 = <&vdd_sd_dv_pins_default>;
133d19a66aeSVignesh Raghavendra		regulator-min-microvolt = <1800000>;
134d19a66aeSVignesh Raghavendra		regulator-max-microvolt = <3300000>;
135d19a66aeSVignesh Raghavendra		regulator-boot-on;
136d19a66aeSVignesh Raghavendra		vin-supply = <&vcc_5v0>;
137d19a66aeSVignesh Raghavendra		gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
138d19a66aeSVignesh Raghavendra		states = <1800000 0x0>,
139d19a66aeSVignesh Raghavendra			 <3300000 0x1>;
140d19a66aeSVignesh Raghavendra	};
141d19a66aeSVignesh Raghavendra
142a033588eSNishanth Menon	leds {
143a033588eSNishanth Menon		compatible = "gpio-leds";
144a033588eSNishanth Menon		pinctrl-names = "default";
145a033588eSNishanth Menon		pinctrl-0 = <&usr_led_pins_default>;
146a033588eSNishanth Menon
147a033588eSNishanth Menon		led-0 {
148a033588eSNishanth Menon			label = "am62-sk:green:heartbeat";
149a033588eSNishanth Menon			gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
150a033588eSNishanth Menon			linux,default-trigger = "heartbeat";
151a033588eSNishanth Menon			function = LED_FUNCTION_HEARTBEAT;
152a033588eSNishanth Menon			default-state = "off";
153a033588eSNishanth Menon		};
154a033588eSNishanth Menon	};
155a033588eSNishanth Menon};
156a033588eSNishanth Menon
157a033588eSNishanth Menon&main_pmx0 {
158a033588eSNishanth Menon	main_uart0_pins_default: main-uart0-pins-default {
159a033588eSNishanth Menon		pinctrl-single,pins = <
160a033588eSNishanth Menon			AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
161a033588eSNishanth Menon			AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
162a033588eSNishanth Menon		>;
163a033588eSNishanth Menon	};
164a033588eSNishanth Menon
165a033588eSNishanth Menon	main_i2c0_pins_default: main-i2c0-pins-default {
166a033588eSNishanth Menon		pinctrl-single,pins = <
167a033588eSNishanth Menon			AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
168a033588eSNishanth Menon			AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
169a033588eSNishanth Menon		>;
170a033588eSNishanth Menon	};
171a033588eSNishanth Menon
172a033588eSNishanth Menon	main_i2c1_pins_default: main-i2c1-pins-default {
173a033588eSNishanth Menon		pinctrl-single,pins = <
174a033588eSNishanth Menon			AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
175a033588eSNishanth Menon			AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
176a033588eSNishanth Menon		>;
177a033588eSNishanth Menon	};
178a033588eSNishanth Menon
179d19a66aeSVignesh Raghavendra	main_i2c2_pins_default: main-i2c2-pins-default {
180d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
181d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
182d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
183d19a66aeSVignesh Raghavendra		>;
184d19a66aeSVignesh Raghavendra	};
185d19a66aeSVignesh Raghavendra
186d19a66aeSVignesh Raghavendra	main_mmc0_pins_default: main-mmc0-pins-default {
187d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
188d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
189d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
190d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
191d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
192d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
193d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
194d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
195d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
196d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
197d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
198d19a66aeSVignesh Raghavendra		>;
199d19a66aeSVignesh Raghavendra	};
200d19a66aeSVignesh Raghavendra
201d19a66aeSVignesh Raghavendra	main_mmc1_pins_default: main-mmc1-pins-default {
202d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
203d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
204d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
205d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
206d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
207d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
208d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
209d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
210d19a66aeSVignesh Raghavendra		>;
211d19a66aeSVignesh Raghavendra	};
212d19a66aeSVignesh Raghavendra
213a033588eSNishanth Menon	usr_led_pins_default: usr-led-pins-default {
214a033588eSNishanth Menon		pinctrl-single,pins = <
215a033588eSNishanth Menon			AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
216a033588eSNishanth Menon		>;
217a033588eSNishanth Menon	};
218d19a66aeSVignesh Raghavendra
219d19a66aeSVignesh Raghavendra	main_mdio1_pins_default: main-mdio1-pins-default {
220d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
221d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
222d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
223d19a66aeSVignesh Raghavendra		>;
224d19a66aeSVignesh Raghavendra	};
225d19a66aeSVignesh Raghavendra
226d19a66aeSVignesh Raghavendra	main_rgmii1_pins_default: main-rgmii1-pins-default {
227d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
228d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
229d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
230d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
231d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
232d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
233d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
234d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
235d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
236d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
237d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
238d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
239d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
240d19a66aeSVignesh Raghavendra		>;
241d19a66aeSVignesh Raghavendra	};
242d19a66aeSVignesh Raghavendra
243d19a66aeSVignesh Raghavendra	main_rgmii2_pins_default: main-rgmii2-pins-default {
244d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
245d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
246d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
247d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
248d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
249d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
250d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
251d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
252d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
253d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
254d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
255d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
256d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
257d19a66aeSVignesh Raghavendra		>;
258d19a66aeSVignesh Raghavendra	};
259d19a66aeSVignesh Raghavendra
260d19a66aeSVignesh Raghavendra	ospi0_pins_default: ospi0-pins-default {
261d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
262d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
263d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
264d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
265d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
266d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
267d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
268d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
269d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
270d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
271d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
272d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
273d19a66aeSVignesh Raghavendra		>;
274d19a66aeSVignesh Raghavendra	};
275d19a66aeSVignesh Raghavendra
276d19a66aeSVignesh Raghavendra	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
277d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
278d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
279d19a66aeSVignesh Raghavendra		>;
280d19a66aeSVignesh Raghavendra	};
281d19a66aeSVignesh Raghavendra
282d19a66aeSVignesh Raghavendra	main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
283d19a66aeSVignesh Raghavendra		pinctrl-single,pins = <
284d19a66aeSVignesh Raghavendra			AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
285d19a66aeSVignesh Raghavendra		>;
286d19a66aeSVignesh Raghavendra	};
287a033588eSNishanth Menon};
288a033588eSNishanth Menon
289a033588eSNishanth Menon&wkup_uart0 {
290a033588eSNishanth Menon	/* WKUP UART0 is used by DM firmware */
291a033588eSNishanth Menon	status = "reserved";
292a033588eSNishanth Menon};
293a033588eSNishanth Menon
294a033588eSNishanth Menon&mcu_uart0 {
295a033588eSNishanth Menon	status = "disabled";
296a033588eSNishanth Menon};
297a033588eSNishanth Menon
298a033588eSNishanth Menon&main_uart0 {
299a033588eSNishanth Menon	pinctrl-names = "default";
300a033588eSNishanth Menon	pinctrl-0 = <&main_uart0_pins_default>;
301a033588eSNishanth Menon};
302a033588eSNishanth Menon
303a033588eSNishanth Menon&main_uart1 {
304a033588eSNishanth Menon	/* Main UART1 is used by TIFS firmware */
305a033588eSNishanth Menon	status = "reserved";
306a033588eSNishanth Menon};
307a033588eSNishanth Menon
308a033588eSNishanth Menon&main_uart2 {
309a033588eSNishanth Menon	status = "disabled";
310a033588eSNishanth Menon};
311a033588eSNishanth Menon
312a033588eSNishanth Menon&main_uart3 {
313a033588eSNishanth Menon	status = "disabled";
314a033588eSNishanth Menon};
315a033588eSNishanth Menon
316a033588eSNishanth Menon&main_uart4 {
317a033588eSNishanth Menon	status = "disabled";
318a033588eSNishanth Menon};
319a033588eSNishanth Menon
320a033588eSNishanth Menon&main_uart5 {
321a033588eSNishanth Menon	status = "disabled";
322a033588eSNishanth Menon};
323a033588eSNishanth Menon
324a033588eSNishanth Menon&main_uart6 {
325a033588eSNishanth Menon	status = "disabled";
326a033588eSNishanth Menon};
327a033588eSNishanth Menon
328a033588eSNishanth Menon&mcu_i2c0 {
329a033588eSNishanth Menon	status = "disabled";
330a033588eSNishanth Menon};
331a033588eSNishanth Menon
332a033588eSNishanth Menon&wkup_i2c0 {
333a033588eSNishanth Menon	status = "disabled";
334a033588eSNishanth Menon};
335a033588eSNishanth Menon
336a033588eSNishanth Menon&main_i2c0 {
337a033588eSNishanth Menon	pinctrl-names = "default";
338a033588eSNishanth Menon	pinctrl-0 = <&main_i2c0_pins_default>;
339a033588eSNishanth Menon	clock-frequency = <400000>;
340a033588eSNishanth Menon};
341a033588eSNishanth Menon
342a033588eSNishanth Menon&main_i2c1 {
343a033588eSNishanth Menon	pinctrl-names = "default";
344a033588eSNishanth Menon	pinctrl-0 = <&main_i2c1_pins_default>;
345a033588eSNishanth Menon	clock-frequency = <400000>;
346d19a66aeSVignesh Raghavendra
347d19a66aeSVignesh Raghavendra	exp1: gpio@22 {
348d19a66aeSVignesh Raghavendra		compatible = "ti,tca6424";
349d19a66aeSVignesh Raghavendra		reg = <0x22>;
350d19a66aeSVignesh Raghavendra		gpio-controller;
351d19a66aeSVignesh Raghavendra		#gpio-cells = <2>;
352d19a66aeSVignesh Raghavendra		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
353d19a66aeSVignesh Raghavendra				   "PRU_DETECT", "MMC1_SD_EN",
354d19a66aeSVignesh Raghavendra				   "VPP_LDO_EN", "EXP_PS_3V3_En",
355d19a66aeSVignesh Raghavendra				   "EXP_PS_5V0_En", "EXP_HAT_DETECT",
356d19a66aeSVignesh Raghavendra				   "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
357d19a66aeSVignesh Raghavendra				   "UART1_FET_BUF_EN", "WL_LT_EN",
358d19a66aeSVignesh Raghavendra				   "GPIO_HDMI_RSTn", "CSI_GPIO1",
359d19a66aeSVignesh Raghavendra				   "CSI_GPIO2", "PRU_3V3_EN",
360d19a66aeSVignesh Raghavendra				   "HDMI_INTn", "TEST_GPIO2",
361d19a66aeSVignesh Raghavendra				   "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
362d19a66aeSVignesh Raghavendra				   "MCASP1_FET_SEL", "UART1_FET_SEL",
363d19a66aeSVignesh Raghavendra				   "TSINT#", "IO_EXP_TEST_LED";
364d19a66aeSVignesh Raghavendra
365d19a66aeSVignesh Raghavendra		interrupt-parent = <&main_gpio1>;
366d19a66aeSVignesh Raghavendra		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
367d19a66aeSVignesh Raghavendra		interrupt-controller;
368d19a66aeSVignesh Raghavendra		#interrupt-cells = <2>;
369d19a66aeSVignesh Raghavendra
370d19a66aeSVignesh Raghavendra		pinctrl-names = "default";
371d19a66aeSVignesh Raghavendra		pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
372d19a66aeSVignesh Raghavendra	};
373a033588eSNishanth Menon};
374a033588eSNishanth Menon
375a033588eSNishanth Menon&main_i2c2 {
376a033588eSNishanth Menon	status = "disabled";
377a033588eSNishanth Menon};
378a033588eSNishanth Menon
379a033588eSNishanth Menon&main_i2c3 {
380a033588eSNishanth Menon	status = "disabled";
381a033588eSNishanth Menon};
382a033588eSNishanth Menon
383d19a66aeSVignesh Raghavendra&sdhci0 {
384d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
385d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mmc0_pins_default>;
386d19a66aeSVignesh Raghavendra	ti,driver-strength-ohm = <50>;
387d19a66aeSVignesh Raghavendra	disable-wp;
388d19a66aeSVignesh Raghavendra};
389d19a66aeSVignesh Raghavendra
390d19a66aeSVignesh Raghavendra&sdhci1 {
391d19a66aeSVignesh Raghavendra	/* SD/MMC */
392d19a66aeSVignesh Raghavendra	vmmc-supply = <&vdd_mmc1>;
393d19a66aeSVignesh Raghavendra	vqmmc-supply = <&vdd_sd_dv>;
394d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
395d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mmc1_pins_default>;
396d19a66aeSVignesh Raghavendra	ti,driver-strength-ohm = <50>;
397d19a66aeSVignesh Raghavendra	disable-wp;
398d19a66aeSVignesh Raghavendra};
399d19a66aeSVignesh Raghavendra
400d19a66aeSVignesh Raghavendra&cpsw3g {
401d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
402d19a66aeSVignesh Raghavendra	pinctrl-0 = <&main_mdio1_pins_default
403d19a66aeSVignesh Raghavendra		     &main_rgmii1_pins_default
404d19a66aeSVignesh Raghavendra		     &main_rgmii2_pins_default>;
405d19a66aeSVignesh Raghavendra};
406d19a66aeSVignesh Raghavendra
407d19a66aeSVignesh Raghavendra&cpsw_port1 {
408d19a66aeSVignesh Raghavendra	phy-mode = "rgmii-rxid";
409d19a66aeSVignesh Raghavendra	phy-handle = <&cpsw3g_phy0>;
410d19a66aeSVignesh Raghavendra};
411d19a66aeSVignesh Raghavendra
412d19a66aeSVignesh Raghavendra&cpsw_port2 {
413d19a66aeSVignesh Raghavendra	phy-mode = "rgmii-rxid";
414d19a66aeSVignesh Raghavendra	phy-handle = <&cpsw3g_phy1>;
415d19a66aeSVignesh Raghavendra};
416d19a66aeSVignesh Raghavendra
417d19a66aeSVignesh Raghavendra&cpsw3g_mdio {
418d19a66aeSVignesh Raghavendra	cpsw3g_phy0: ethernet-phy@0 {
419d19a66aeSVignesh Raghavendra		reg = <0>;
420d19a66aeSVignesh Raghavendra		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
421d19a66aeSVignesh Raghavendra		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
422d19a66aeSVignesh Raghavendra		ti,min-output-impedance;
423d19a66aeSVignesh Raghavendra	};
424d19a66aeSVignesh Raghavendra
425d19a66aeSVignesh Raghavendra	cpsw3g_phy1: ethernet-phy@1 {
426d19a66aeSVignesh Raghavendra		reg = <1>;
427d19a66aeSVignesh Raghavendra		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
428d19a66aeSVignesh Raghavendra		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
429d19a66aeSVignesh Raghavendra		ti,min-output-impedance;
430d19a66aeSVignesh Raghavendra	};
431d19a66aeSVignesh Raghavendra};
432d19a66aeSVignesh Raghavendra
433a033588eSNishanth Menon&mailbox0_cluster0 {
434a033588eSNishanth Menon	mbox_m4_0: mbox-m4-0 {
435a033588eSNishanth Menon		ti,mbox-rx = <0 0 0>;
436a033588eSNishanth Menon		ti,mbox-tx = <1 0 0>;
437a033588eSNishanth Menon	};
438a033588eSNishanth Menon};
439d19a66aeSVignesh Raghavendra
440d19a66aeSVignesh Raghavendra&ospi0 {
441d19a66aeSVignesh Raghavendra	pinctrl-names = "default";
442d19a66aeSVignesh Raghavendra	pinctrl-0 = <&ospi0_pins_default>;
443d19a66aeSVignesh Raghavendra
444d19a66aeSVignesh Raghavendra	flash@0{
445d19a66aeSVignesh Raghavendra		compatible = "jedec,spi-nor";
446d19a66aeSVignesh Raghavendra		reg = <0x0>;
447d19a66aeSVignesh Raghavendra		spi-tx-bus-width = <8>;
448d19a66aeSVignesh Raghavendra		spi-rx-bus-width = <8>;
449d19a66aeSVignesh Raghavendra		spi-max-frequency = <25000000>;
450d19a66aeSVignesh Raghavendra		cdns,tshsl-ns = <60>;
451d19a66aeSVignesh Raghavendra		cdns,tsd2d-ns = <60>;
452d19a66aeSVignesh Raghavendra		cdns,tchsh-ns = <60>;
453d19a66aeSVignesh Raghavendra		cdns,tslch-ns = <60>;
454d19a66aeSVignesh Raghavendra		cdns,read-delay = <4>;
455d19a66aeSVignesh Raghavendra
456d19a66aeSVignesh Raghavendra		partitions {
457d19a66aeSVignesh Raghavendra			compatible = "fixed-partitions";
458d19a66aeSVignesh Raghavendra			#address-cells = <1>;
459d19a66aeSVignesh Raghavendra			#size-cells = <1>;
460d19a66aeSVignesh Raghavendra
461d19a66aeSVignesh Raghavendra			partition@0 {
462d19a66aeSVignesh Raghavendra				label = "ospi.tiboot3";
463d19a66aeSVignesh Raghavendra				reg = <0x0 0x80000>;
464d19a66aeSVignesh Raghavendra			};
465d19a66aeSVignesh Raghavendra
466d19a66aeSVignesh Raghavendra			partition@80000 {
467d19a66aeSVignesh Raghavendra				label = "ospi.tispl";
468d19a66aeSVignesh Raghavendra				reg = <0x80000 0x200000>;
469d19a66aeSVignesh Raghavendra			};
470d19a66aeSVignesh Raghavendra
471d19a66aeSVignesh Raghavendra			partition@280000 {
472d19a66aeSVignesh Raghavendra				label = "ospi.u-boot";
473d19a66aeSVignesh Raghavendra				reg = <0x280000 0x400000>;
474d19a66aeSVignesh Raghavendra			};
475d19a66aeSVignesh Raghavendra
476d19a66aeSVignesh Raghavendra			partition@680000 {
477d19a66aeSVignesh Raghavendra				label = "ospi.env";
478d19a66aeSVignesh Raghavendra				reg = <0x680000 0x40000>;
479d19a66aeSVignesh Raghavendra			};
480d19a66aeSVignesh Raghavendra
481d19a66aeSVignesh Raghavendra			partition@6c0000 {
482d19a66aeSVignesh Raghavendra				label = "ospi.env.backup";
483d19a66aeSVignesh Raghavendra				reg = <0x6c0000 0x40000>;
484d19a66aeSVignesh Raghavendra			};
485d19a66aeSVignesh Raghavendra
486d19a66aeSVignesh Raghavendra			partition@800000 {
487d19a66aeSVignesh Raghavendra				label = "ospi.rootfs";
488d19a66aeSVignesh Raghavendra				reg = <0x800000 0x37c0000>;
489d19a66aeSVignesh Raghavendra			};
490d19a66aeSVignesh Raghavendra
491d19a66aeSVignesh Raghavendra			partition@3fc0000 {
492d19a66aeSVignesh Raghavendra				label = "ospi.phypattern";
493d19a66aeSVignesh Raghavendra				reg = <0x3fc0000 0x40000>;
494d19a66aeSVignesh Raghavendra			};
495d19a66aeSVignesh Raghavendra		};
496d19a66aeSVignesh Raghavendra	};
497d19a66aeSVignesh Raghavendra};
498bd67e1beSVignesh Raghavendra
499bd67e1beSVignesh Raghavendra&ecap0 {
500bd67e1beSVignesh Raghavendra	status = "disabled";
501bd67e1beSVignesh Raghavendra};
502bd67e1beSVignesh Raghavendra
503bd67e1beSVignesh Raghavendra&ecap1 {
504bd67e1beSVignesh Raghavendra	status = "disabled";
505bd67e1beSVignesh Raghavendra};
506bd67e1beSVignesh Raghavendra
507bd67e1beSVignesh Raghavendra&ecap2 {
508bd67e1beSVignesh Raghavendra	status = "disabled";
509bd67e1beSVignesh Raghavendra};
5102492a974SAswath Govindraju
5112492a974SAswath Govindraju&main_mcan0 {
5122492a974SAswath Govindraju	status = "disabled";
5132492a974SAswath Govindraju};
514acf3fdc8SGeorgi Vlaev
515acf3fdc8SGeorgi Vlaev&epwm0 {
516acf3fdc8SGeorgi Vlaev	status = "disabled";
517acf3fdc8SGeorgi Vlaev};
518acf3fdc8SGeorgi Vlaev
519acf3fdc8SGeorgi Vlaev&epwm1 {
520acf3fdc8SGeorgi Vlaev	status = "disabled";
521acf3fdc8SGeorgi Vlaev};
522acf3fdc8SGeorgi Vlaev
523acf3fdc8SGeorgi Vlaev&epwm2 {
524acf3fdc8SGeorgi Vlaev	status = "disabled";
525acf3fdc8SGeorgi Vlaev};
526