1f1d17330SVignesh Raghavendra// SPDX-License-Identifier: GPL-2.0
2f1d17330SVignesh Raghavendra/*
3f1d17330SVignesh Raghavendra * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
4f1d17330SVignesh Raghavendra *
5f1d17330SVignesh Raghavendra * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6f1d17330SVignesh Raghavendra */
7f1d17330SVignesh Raghavendra
8f1d17330SVignesh Raghavendra&cbass_wakeup {
9f1d17330SVignesh Raghavendra	wkup_conf: syscon@43000000 {
10f1d17330SVignesh Raghavendra		compatible = "syscon", "simple-mfd";
11f1d17330SVignesh Raghavendra		reg = <0x00 0x43000000 0x00 0x20000>;
12f1d17330SVignesh Raghavendra		#address-cells = <1>;
13f1d17330SVignesh Raghavendra		#size-cells = <1>;
14f1d17330SVignesh Raghavendra		ranges = <0x0 0x00 0x43000000 0x20000>;
15f1d17330SVignesh Raghavendra
16f1d17330SVignesh Raghavendra		chipid: chipid@14 {
17f1d17330SVignesh Raghavendra			compatible = "ti,am654-chipid";
18f1d17330SVignesh Raghavendra			reg = <0x14 0x4>;
19f1d17330SVignesh Raghavendra		};
20f1d17330SVignesh Raghavendra	};
21f1d17330SVignesh Raghavendra
22f1d17330SVignesh Raghavendra	wkup_uart0: serial@2b300000 {
23f1d17330SVignesh Raghavendra		compatible = "ti,am64-uart", "ti,am654-uart";
24f1d17330SVignesh Raghavendra		reg = <0x00 0x2b300000 0x00 0x100>;
25f1d17330SVignesh Raghavendra		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
26f1d17330SVignesh Raghavendra		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
27f1d17330SVignesh Raghavendra		clocks = <&k3_clks 114 0>;
28f1d17330SVignesh Raghavendra		clock-names = "fclk";
29b5877d9bSAndrew Davis		status = "disabled";
30f1d17330SVignesh Raghavendra	};
31f1d17330SVignesh Raghavendra
32f1d17330SVignesh Raghavendra	wkup_i2c0: i2c@2b200000 {
33f1d17330SVignesh Raghavendra		compatible = "ti,am64-i2c", "ti,omap4-i2c";
3481685b3dSKrzysztof Kozlowski		reg = <0x00 0x2b200000 0x00 0x100>;
35f1d17330SVignesh Raghavendra		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
36f1d17330SVignesh Raghavendra		#address-cells = <1>;
37f1d17330SVignesh Raghavendra		#size-cells = <0>;
38f1d17330SVignesh Raghavendra		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
39f1d17330SVignesh Raghavendra		clocks = <&k3_clks 107 4>;
40f1d17330SVignesh Raghavendra		clock-names = "fck";
41a1541a08SAndrew Davis		status = "disabled";
42f1d17330SVignesh Raghavendra	};
430c51ceeeSNishanth Menon
440c51ceeeSNishanth Menon	wkup_rtc0: rtc@2b1f0000 {
450c51ceeeSNishanth Menon		compatible = "ti,am62-rtc";
460c51ceeeSNishanth Menon		reg = <0x00 0x2b1f0000 0x00 0x100>;
470c51ceeeSNishanth Menon		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
480c51ceeeSNishanth Menon		clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
490c51ceeeSNishanth Menon		clock-names = "vbus", "osc32k";
500c51ceeeSNishanth Menon		power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
510c51ceeeSNishanth Menon		wakeup-source;
520c51ceeeSNishanth Menon	};
534eec5d77SJulien Panis
544eec5d77SJulien Panis	wkup_rti0: watchdog@2b000000 {
554eec5d77SJulien Panis		compatible = "ti,j7-rti-wdt";
564eec5d77SJulien Panis		reg = <0x00 0x2b000000 0x00 0x100>;
574eec5d77SJulien Panis		clocks = <&k3_clks 132 0>;
584eec5d77SJulien Panis		power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>;
594eec5d77SJulien Panis		assigned-clocks = <&k3_clks 132 0>;
604eec5d77SJulien Panis		assigned-clock-parents = <&k3_clks 132 2>;
614eec5d77SJulien Panis		/* Used by DM firmware */
624eec5d77SJulien Panis		status = "reserved";
634eec5d77SJulien Panis	};
64*bbb6dc62SBryan Brattlof
65*bbb6dc62SBryan Brattlof	wkup_vtm0: temperature-sensor@b00000 {
66*bbb6dc62SBryan Brattlof		compatible = "ti,j7200-vtm";
67*bbb6dc62SBryan Brattlof		reg = <0x00 0xb00000 0x00 0x400>,
68*bbb6dc62SBryan Brattlof		      <0x00 0xb01000 0x00 0x400>;
69*bbb6dc62SBryan Brattlof		power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
70*bbb6dc62SBryan Brattlof		#thermal-sensor-cells = <1>;
71*bbb6dc62SBryan Brattlof	};
72f1d17330SVignesh Raghavendra};
73