1f1d17330SVignesh Raghavendra// SPDX-License-Identifier: GPL-2.0 2f1d17330SVignesh Raghavendra/* 3f1d17330SVignesh Raghavendra * Device Tree Source for AM625 SoC Family MCU Domain peripherals 4f1d17330SVignesh Raghavendra * 5f1d17330SVignesh Raghavendra * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6f1d17330SVignesh Raghavendra */ 7f1d17330SVignesh Raghavendra 8f1d17330SVignesh Raghavendra&cbass_mcu { 9f1d17330SVignesh Raghavendra mcu_pmx0: pinctrl@4084000 { 10f1d17330SVignesh Raghavendra compatible = "pinctrl-single"; 11f1d17330SVignesh Raghavendra reg = <0x00 0x04084000 0x00 0x88>; 12f1d17330SVignesh Raghavendra #pinctrl-cells = <1>; 13f1d17330SVignesh Raghavendra pinctrl-single,register-width = <32>; 14f1d17330SVignesh Raghavendra pinctrl-single,function-mask = <0xffffffff>; 15f1d17330SVignesh Raghavendra }; 16f1d17330SVignesh Raghavendra 17f1d17330SVignesh Raghavendra mcu_uart0: serial@4a00000 { 18f1d17330SVignesh Raghavendra compatible = "ti,am64-uart", "ti,am654-uart"; 19f1d17330SVignesh Raghavendra reg = <0x00 0x04a00000 0x00 0x100>; 20f1d17330SVignesh Raghavendra interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 21f1d17330SVignesh Raghavendra power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 22f1d17330SVignesh Raghavendra clocks = <&k3_clks 149 0>; 23f1d17330SVignesh Raghavendra clock-names = "fclk"; 24f1d17330SVignesh Raghavendra }; 25f1d17330SVignesh Raghavendra 26f1d17330SVignesh Raghavendra mcu_i2c0: i2c@4900000 { 27f1d17330SVignesh Raghavendra compatible = "ti,am64-i2c", "ti,omap4-i2c"; 28f1d17330SVignesh Raghavendra reg = <0x00 0x04900000 0x00 0x100>; 29f1d17330SVignesh Raghavendra interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 30f1d17330SVignesh Raghavendra #address-cells = <1>; 31f1d17330SVignesh Raghavendra #size-cells = <0>; 32f1d17330SVignesh Raghavendra power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 33f1d17330SVignesh Raghavendra clocks = <&k3_clks 106 2>; 34f1d17330SVignesh Raghavendra clock-names = "fck"; 35f1d17330SVignesh Raghavendra }; 36*c37c58fdSVignesh Raghavendra 37*c37c58fdSVignesh Raghavendra mcu_spi0: spi@4b00000 { 38*c37c58fdSVignesh Raghavendra compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 39*c37c58fdSVignesh Raghavendra reg = <0x00 0x04b00000 0x00 0x400>; 40*c37c58fdSVignesh Raghavendra interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 41*c37c58fdSVignesh Raghavendra #address-cells = <1>; 42*c37c58fdSVignesh Raghavendra #size-cells = <0>; 43*c37c58fdSVignesh Raghavendra power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 44*c37c58fdSVignesh Raghavendra clocks = <&k3_clks 147 0>; 45*c37c58fdSVignesh Raghavendra }; 46*c37c58fdSVignesh Raghavendra 47*c37c58fdSVignesh Raghavendra mcu_spi1: spi@4b10000 { 48*c37c58fdSVignesh Raghavendra compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 49*c37c58fdSVignesh Raghavendra reg = <0x00 0x04b10000 0x00 0x400>; 50*c37c58fdSVignesh Raghavendra interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 51*c37c58fdSVignesh Raghavendra #address-cells = <1>; 52*c37c58fdSVignesh Raghavendra #size-cells = <0>; 53*c37c58fdSVignesh Raghavendra power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 54*c37c58fdSVignesh Raghavendra clocks = <&k3_clks 148 0>; 55*c37c58fdSVignesh Raghavendra }; 56f1d17330SVignesh Raghavendra}; 57