13c0e3abdSOrson Zhai/* 23c0e3abdSOrson Zhai * Spreadtrum Whale2 platform peripherals 33c0e3abdSOrson Zhai * 43c0e3abdSOrson Zhai * Copyright (C) 2016, Spreadtrum Communications Inc. 53c0e3abdSOrson Zhai * 63c0e3abdSOrson Zhai * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 73c0e3abdSOrson Zhai */ 83c0e3abdSOrson Zhai 96c6fbbd1SBaolin Wang#include <dt-bindings/clock/sprd,sc9860-clk.h> 106c6fbbd1SBaolin Wang 113c0e3abdSOrson Zhai/ { 123c0e3abdSOrson Zhai interrupt-parent = <&gic>; 133c0e3abdSOrson Zhai #address-cells = <2>; 143c0e3abdSOrson Zhai #size-cells = <2>; 153c0e3abdSOrson Zhai 163c0e3abdSOrson Zhai soc: soc { 173c0e3abdSOrson Zhai compatible = "simple-bus"; 183c0e3abdSOrson Zhai #address-cells = <2>; 193c0e3abdSOrson Zhai #size-cells = <2>; 203c0e3abdSOrson Zhai ranges; 213c0e3abdSOrson Zhai 2233d3ebd4SChunyan Zhang ap_ahb_regs: syscon@20210000 { 2333d3ebd4SChunyan Zhang compatible = "syscon"; 2433d3ebd4SChunyan Zhang reg = <0 0x20210000 0 0x10000>; 2533d3ebd4SChunyan Zhang }; 2633d3ebd4SChunyan Zhang 2733d3ebd4SChunyan Zhang pmu_regs: syscon@402b0000 { 2833d3ebd4SChunyan Zhang compatible = "syscon"; 2933d3ebd4SChunyan Zhang reg = <0 0x402b0000 0 0x10000>; 3033d3ebd4SChunyan Zhang }; 3133d3ebd4SChunyan Zhang 3233d3ebd4SChunyan Zhang aon_regs: syscon@402e0000 { 3333d3ebd4SChunyan Zhang compatible = "syscon"; 3433d3ebd4SChunyan Zhang reg = <0 0x402e0000 0 0x10000>; 3533d3ebd4SChunyan Zhang }; 3633d3ebd4SChunyan Zhang 3733d3ebd4SChunyan Zhang ana_regs: syscon@40400000 { 3833d3ebd4SChunyan Zhang compatible = "syscon"; 3933d3ebd4SChunyan Zhang reg = <0 0x40400000 0 0x10000>; 4033d3ebd4SChunyan Zhang }; 4133d3ebd4SChunyan Zhang 4233d3ebd4SChunyan Zhang agcp_regs: syscon@415e0000 { 4333d3ebd4SChunyan Zhang compatible = "syscon"; 4433d3ebd4SChunyan Zhang reg = <0 0x415e0000 0 0x1000000>; 4533d3ebd4SChunyan Zhang }; 4633d3ebd4SChunyan Zhang 4733d3ebd4SChunyan Zhang vsp_regs: syscon@61100000 { 4833d3ebd4SChunyan Zhang compatible = "syscon"; 4933d3ebd4SChunyan Zhang reg = <0 0x61100000 0 0x10000>; 5033d3ebd4SChunyan Zhang }; 5133d3ebd4SChunyan Zhang 5233d3ebd4SChunyan Zhang cam_regs: syscon@62100000 { 5333d3ebd4SChunyan Zhang compatible = "syscon"; 5433d3ebd4SChunyan Zhang reg = <0 0x62100000 0 0x10000>; 5533d3ebd4SChunyan Zhang }; 5633d3ebd4SChunyan Zhang 5733d3ebd4SChunyan Zhang disp_regs: syscon@63100000 { 5833d3ebd4SChunyan Zhang compatible = "syscon"; 5933d3ebd4SChunyan Zhang reg = <0 0x63100000 0 0x10000>; 6033d3ebd4SChunyan Zhang }; 6133d3ebd4SChunyan Zhang 6233d3ebd4SChunyan Zhang ap_apb_regs: syscon@70b00000 { 6333d3ebd4SChunyan Zhang compatible = "syscon"; 6433d3ebd4SChunyan Zhang reg = <0 0x70b00000 0 0x40000>; 6533d3ebd4SChunyan Zhang }; 6633d3ebd4SChunyan Zhang 673c0e3abdSOrson Zhai ap-apb { 683c0e3abdSOrson Zhai compatible = "simple-bus"; 693c0e3abdSOrson Zhai #address-cells = <1>; 703c0e3abdSOrson Zhai #size-cells = <1>; 713c0e3abdSOrson Zhai ranges = <0 0x0 0x70000000 0x10000000>; 723c0e3abdSOrson Zhai 733c0e3abdSOrson Zhai uart0: serial@0 { 743c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 753c0e3abdSOrson Zhai "sprd,sc9836-uart"; 763c0e3abdSOrson Zhai reg = <0x0 0x100>; 773c0e3abdSOrson Zhai interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 7815d574fbSBaolin Wang clock-names = "enable", "uart", "source"; 7915d574fbSBaolin Wang clocks = <&apapb_gate CLK_UART0_EB>, 8015d574fbSBaolin Wang <&ap_clk CLK_UART0>, <&ext_26m>; 813c0e3abdSOrson Zhai status = "disabled"; 823c0e3abdSOrson Zhai }; 833c0e3abdSOrson Zhai 843c0e3abdSOrson Zhai uart1: serial@100000 { 853c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 863c0e3abdSOrson Zhai "sprd,sc9836-uart"; 873c0e3abdSOrson Zhai reg = <0x100000 0x100>; 883c0e3abdSOrson Zhai interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 8915d574fbSBaolin Wang clock-names = "enable", "uart", "source"; 9015d574fbSBaolin Wang clocks = <&apapb_gate CLK_UART1_EB>, 9115d574fbSBaolin Wang <&ap_clk CLK_UART1>, <&ext_26m>; 923c0e3abdSOrson Zhai status = "disabled"; 933c0e3abdSOrson Zhai }; 943c0e3abdSOrson Zhai 953c0e3abdSOrson Zhai uart2: serial@200000 { 963c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 973c0e3abdSOrson Zhai "sprd,sc9836-uart"; 983c0e3abdSOrson Zhai reg = <0x200000 0x100>; 993c0e3abdSOrson Zhai interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 10015d574fbSBaolin Wang clock-names = "enable", "uart", "source"; 10115d574fbSBaolin Wang clocks = <&apapb_gate CLK_UART2_EB>, 10215d574fbSBaolin Wang <&ap_clk CLK_UART2>, <&ext_26m>; 1033c0e3abdSOrson Zhai status = "disabled"; 1043c0e3abdSOrson Zhai }; 1053c0e3abdSOrson Zhai 1063c0e3abdSOrson Zhai uart3: serial@300000 { 1073c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 1083c0e3abdSOrson Zhai "sprd,sc9836-uart"; 1093c0e3abdSOrson Zhai reg = <0x300000 0x100>; 1103c0e3abdSOrson Zhai interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 11115d574fbSBaolin Wang clock-names = "enable", "uart", "source"; 11215d574fbSBaolin Wang clocks = <&apapb_gate CLK_UART3_EB>, 11315d574fbSBaolin Wang <&ap_clk CLK_UART3>, <&ext_26m>; 1143c0e3abdSOrson Zhai status = "disabled"; 1153c0e3abdSOrson Zhai }; 1163c0e3abdSOrson Zhai }; 1176c6fbbd1SBaolin Wang 118258e1ae6SBaolin Wang ap-ahb { 119258e1ae6SBaolin Wang compatible = "simple-bus"; 120258e1ae6SBaolin Wang #address-cells = <2>; 121258e1ae6SBaolin Wang #size-cells = <2>; 122258e1ae6SBaolin Wang ranges; 123258e1ae6SBaolin Wang 124258e1ae6SBaolin Wang ap_dma: dma-controller@20100000 { 125258e1ae6SBaolin Wang compatible = "sprd,sc9860-dma"; 126258e1ae6SBaolin Wang reg = <0 0x20100000 0 0x4000>; 127258e1ae6SBaolin Wang interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 128258e1ae6SBaolin Wang #dma-cells = <1>; 129258e1ae6SBaolin Wang #dma-channels = <32>; 130258e1ae6SBaolin Wang clock-names = "enable"; 131258e1ae6SBaolin Wang clocks = <&apahb_gate CLK_DMA_EB>; 132258e1ae6SBaolin Wang }; 133c311f4ffSBaolin Wang 134c311f4ffSBaolin Wang sdio3: sdio@50430000 { 135c311f4ffSBaolin Wang compatible = "sprd,sdhci-r11"; 136c311f4ffSBaolin Wang reg = <0 0x50430000 0 0x1000>; 137c311f4ffSBaolin Wang interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 138c311f4ffSBaolin Wang 139c311f4ffSBaolin Wang clock-names = "sdio", "enable", "2x_enable"; 140c311f4ffSBaolin Wang clocks = <&aon_prediv CLK_EMMC_2X>, 141c311f4ffSBaolin Wang <&apahb_gate CLK_EMMC_EB>, 142c311f4ffSBaolin Wang <&aon_gate CLK_EMMC_2X_EN>; 143c311f4ffSBaolin Wang assigned-clocks = <&aon_prediv CLK_EMMC_2X>; 144c311f4ffSBaolin Wang assigned-clock-parents = <&clk_l0_409m6>; 145c311f4ffSBaolin Wang 146c311f4ffSBaolin Wang sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; 147c311f4ffSBaolin Wang sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; 148c311f4ffSBaolin Wang sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; 149c311f4ffSBaolin Wang sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; 150c311f4ffSBaolin Wang vmmc-supply = <&vddemmccore>; 151c311f4ffSBaolin Wang bus-width = <8>; 152c311f4ffSBaolin Wang non-removable; 153c311f4ffSBaolin Wang no-sdio; 154c311f4ffSBaolin Wang no-sd; 155c311f4ffSBaolin Wang cap-mmc-hw-reset; 156c311f4ffSBaolin Wang mmc-hs400-enhanced-strobe; 157c311f4ffSBaolin Wang mmc-hs400-1_8v; 158c311f4ffSBaolin Wang mmc-hs200-1_8v; 159c311f4ffSBaolin Wang mmc-ddr-1_8v; 160c311f4ffSBaolin Wang }; 161258e1ae6SBaolin Wang }; 162258e1ae6SBaolin Wang 1636c6fbbd1SBaolin Wang aon { 1646c6fbbd1SBaolin Wang compatible = "simple-bus"; 1656c6fbbd1SBaolin Wang #address-cells = <2>; 1666c6fbbd1SBaolin Wang #size-cells = <2>; 1676c6fbbd1SBaolin Wang ranges; 1686c6fbbd1SBaolin Wang 169e254460aSBaolin Wang adi_bus: spi@40030000 { 170e254460aSBaolin Wang compatible = "sprd,sc9860-adi"; 171e254460aSBaolin Wang reg = <0 0x40030000 0 0x10000>; 172e254460aSBaolin Wang hwlocks = <&hwlock 0>; 173e254460aSBaolin Wang hwlock-names = "adi"; 174e254460aSBaolin Wang #address-cells = <1>; 175e254460aSBaolin Wang #size-cells = <0>; 176e254460aSBaolin Wang }; 177e254460aSBaolin Wang 1780cb3dad0SBaolin Wang timer@40050000 { 1790cb3dad0SBaolin Wang compatible = "sprd,sc9860-timer"; 1800cb3dad0SBaolin Wang reg = <0 0x40050000 0 0x20>; 1810cb3dad0SBaolin Wang interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1820cb3dad0SBaolin Wang clocks = <&ext_32k>; 1830cb3dad0SBaolin Wang }; 1840cb3dad0SBaolin Wang 185b2d94b3fSBaolin Wang timer@40050020 { 186b2d94b3fSBaolin Wang compatible = "sprd,sc9860-suspend-timer"; 187b2d94b3fSBaolin Wang reg = <0 0x40050020 0 0x20>; 188b2d94b3fSBaolin Wang clocks = <&ext_32k>; 189b2d94b3fSBaolin Wang }; 190b2d94b3fSBaolin Wang 1916c6fbbd1SBaolin Wang hwlock: hwspinlock@40500000 { 1926c6fbbd1SBaolin Wang compatible = "sprd,hwspinlock-r3p0"; 1936c6fbbd1SBaolin Wang reg = <0 0x40500000 0 0x1000>; 1946c6fbbd1SBaolin Wang #hwlock-cells = <1>; 1956c6fbbd1SBaolin Wang clock-names = "enable"; 1966c6fbbd1SBaolin Wang clocks = <&aon_gate CLK_SPLK_EB>; 1976c6fbbd1SBaolin Wang }; 198d85bcd9cSBaolin Wang 1991cea2c22SBaolin Wang eic_debounce: gpio@40210000 { 2001cea2c22SBaolin Wang compatible = "sprd,sc9860-eic-debounce"; 2011cea2c22SBaolin Wang reg = <0 0x40210000 0 0x80>; 2021cea2c22SBaolin Wang gpio-controller; 2031cea2c22SBaolin Wang #gpio-cells = <2>; 2041cea2c22SBaolin Wang interrupt-controller; 2051cea2c22SBaolin Wang #interrupt-cells = <2>; 2061cea2c22SBaolin Wang interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 2071cea2c22SBaolin Wang }; 2081cea2c22SBaolin Wang 2091cea2c22SBaolin Wang eic_latch: gpio@40210080 { 2101cea2c22SBaolin Wang compatible = "sprd,sc9860-eic-latch"; 2111cea2c22SBaolin Wang reg = <0 0x40210080 0 0x20>; 2121cea2c22SBaolin Wang gpio-controller; 2131cea2c22SBaolin Wang #gpio-cells = <2>; 2141cea2c22SBaolin Wang interrupt-controller; 2151cea2c22SBaolin Wang #interrupt-cells = <2>; 2161cea2c22SBaolin Wang interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 2171cea2c22SBaolin Wang }; 2181cea2c22SBaolin Wang 2191cea2c22SBaolin Wang eic_async: gpio@402100a0 { 2201cea2c22SBaolin Wang compatible = "sprd,sc9860-eic-async"; 2211cea2c22SBaolin Wang reg = <0 0x402100a0 0 0x20>; 2221cea2c22SBaolin Wang gpio-controller; 2231cea2c22SBaolin Wang #gpio-cells = <2>; 2241cea2c22SBaolin Wang interrupt-controller; 2251cea2c22SBaolin Wang #interrupt-cells = <2>; 2261cea2c22SBaolin Wang interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 2271cea2c22SBaolin Wang }; 2281cea2c22SBaolin Wang 2291cea2c22SBaolin Wang eic_sync: gpio@402100c0 { 2301cea2c22SBaolin Wang compatible = "sprd,sc9860-eic-sync"; 2311cea2c22SBaolin Wang reg = <0 0x402100c0 0 0x20>; 2321cea2c22SBaolin Wang gpio-controller; 2331cea2c22SBaolin Wang #gpio-cells = <2>; 2341cea2c22SBaolin Wang interrupt-controller; 2351cea2c22SBaolin Wang #interrupt-cells = <2>; 2361cea2c22SBaolin Wang interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 2371cea2c22SBaolin Wang }; 2381cea2c22SBaolin Wang 2391cea2c22SBaolin Wang ap_gpio: gpio@40280000 { 2401cea2c22SBaolin Wang compatible = "sprd,sc9860-gpio"; 2411cea2c22SBaolin Wang reg = <0 0x40280000 0 0x1000>; 2421cea2c22SBaolin Wang gpio-controller; 2431cea2c22SBaolin Wang #gpio-cells = <2>; 2441cea2c22SBaolin Wang interrupt-controller; 2451cea2c22SBaolin Wang #interrupt-cells = <2>; 2461cea2c22SBaolin Wang interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 2471cea2c22SBaolin Wang }; 2481cea2c22SBaolin Wang 249d85bcd9cSBaolin Wang pin_controller: pinctrl@402a0000 { 250d85bcd9cSBaolin Wang compatible = "sprd,sc9860-pinctrl"; 251d85bcd9cSBaolin Wang reg = <0 0x402a0000 0 0x10000>; 252d85bcd9cSBaolin Wang }; 2534f681369SBaolin Wang 2544f681369SBaolin Wang watchdog@40310000 { 2554f681369SBaolin Wang compatible = "sprd,sp9860-wdt"; 2564f681369SBaolin Wang reg = <0 0x40310000 0 0x1000>; 2574f681369SBaolin Wang interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 2584f681369SBaolin Wang timeout-sec = <12>; 25921a9883fSBaolin Wang clock-names = "enable", "rtc_enable"; 26021a9883fSBaolin Wang clocks = <&aon_gate CLK_APCPU_WDG_EB>, 26121a9883fSBaolin Wang <&aon_gate CLK_AP_WDG_RTC_EB>; 2624f681369SBaolin Wang }; 2636c6fbbd1SBaolin Wang }; 264258e1ae6SBaolin Wang 265258e1ae6SBaolin Wang agcp { 266258e1ae6SBaolin Wang compatible = "simple-bus"; 267258e1ae6SBaolin Wang #address-cells = <2>; 268258e1ae6SBaolin Wang #size-cells = <2>; 269258e1ae6SBaolin Wang ranges; 270258e1ae6SBaolin Wang 271258e1ae6SBaolin Wang agcp_dma: dma-controller@41580000 { 272258e1ae6SBaolin Wang compatible = "sprd,sc9860-dma"; 273258e1ae6SBaolin Wang reg = <0 0x41580000 0 0x4000>; 274258e1ae6SBaolin Wang #dma-cells = <1>; 275258e1ae6SBaolin Wang #dma-channels = <32>; 276258e1ae6SBaolin Wang clock-names = "enable", "ashb_eb"; 277258e1ae6SBaolin Wang clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, 278258e1ae6SBaolin Wang <&agcp_gate CLK_AGCP_AP_ASHB_EB>; 279258e1ae6SBaolin Wang }; 280258e1ae6SBaolin Wang }; 2813c0e3abdSOrson Zhai }; 2823c0e3abdSOrson Zhai 28322f37a24SChunyan Zhang ext_32k: ext_32k { 28422f37a24SChunyan Zhang compatible = "fixed-clock"; 28522f37a24SChunyan Zhang #clock-cells = <0>; 28622f37a24SChunyan Zhang clock-frequency = <32768>; 28722f37a24SChunyan Zhang clock-output-names = "ext-32k"; 28822f37a24SChunyan Zhang }; 28922f37a24SChunyan Zhang 29022f37a24SChunyan Zhang ext_26m: ext_26m { 2913c0e3abdSOrson Zhai compatible = "fixed-clock"; 2923c0e3abdSOrson Zhai #clock-cells = <0>; 2933c0e3abdSOrson Zhai clock-frequency = <26000000>; 29422f37a24SChunyan Zhang clock-output-names = "ext-26m"; 29522f37a24SChunyan Zhang }; 29622f37a24SChunyan Zhang 29722f37a24SChunyan Zhang ext_rco_100m: ext_rco_100m { 29822f37a24SChunyan Zhang compatible = "fixed-clock"; 29922f37a24SChunyan Zhang #clock-cells = <0>; 30022f37a24SChunyan Zhang clock-frequency = <100000000>; 30122f37a24SChunyan Zhang clock-output-names = "ext-rco-100m"; 3023c0e3abdSOrson Zhai }; 303c311f4ffSBaolin Wang 304c311f4ffSBaolin Wang clk_l0_409m6: clk_l0_409m6 { 305c311f4ffSBaolin Wang compatible = "fixed-clock"; 306c311f4ffSBaolin Wang #clock-cells = <0>; 307c311f4ffSBaolin Wang clock-frequency = <409600000>; 308c311f4ffSBaolin Wang clock-output-names = "ext-409m6"; 309c311f4ffSBaolin Wang }; 3103c0e3abdSOrson Zhai}; 311