13c0e3abdSOrson Zhai/* 23c0e3abdSOrson Zhai * Spreadtrum Whale2 platform peripherals 33c0e3abdSOrson Zhai * 43c0e3abdSOrson Zhai * Copyright (C) 2016, Spreadtrum Communications Inc. 53c0e3abdSOrson Zhai * 63c0e3abdSOrson Zhai * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 73c0e3abdSOrson Zhai */ 83c0e3abdSOrson Zhai 96c6fbbd1SBaolin Wang#include <dt-bindings/clock/sprd,sc9860-clk.h> 106c6fbbd1SBaolin Wang 113c0e3abdSOrson Zhai/ { 123c0e3abdSOrson Zhai interrupt-parent = <&gic>; 133c0e3abdSOrson Zhai #address-cells = <2>; 143c0e3abdSOrson Zhai #size-cells = <2>; 153c0e3abdSOrson Zhai 163c0e3abdSOrson Zhai soc: soc { 173c0e3abdSOrson Zhai compatible = "simple-bus"; 183c0e3abdSOrson Zhai #address-cells = <2>; 193c0e3abdSOrson Zhai #size-cells = <2>; 203c0e3abdSOrson Zhai ranges; 213c0e3abdSOrson Zhai 2233d3ebd4SChunyan Zhang ap_ahb_regs: syscon@20210000 { 2333d3ebd4SChunyan Zhang compatible = "syscon"; 2433d3ebd4SChunyan Zhang reg = <0 0x20210000 0 0x10000>; 2533d3ebd4SChunyan Zhang }; 2633d3ebd4SChunyan Zhang 2733d3ebd4SChunyan Zhang pmu_regs: syscon@402b0000 { 2833d3ebd4SChunyan Zhang compatible = "syscon"; 2933d3ebd4SChunyan Zhang reg = <0 0x402b0000 0 0x10000>; 3033d3ebd4SChunyan Zhang }; 3133d3ebd4SChunyan Zhang 3233d3ebd4SChunyan Zhang aon_regs: syscon@402e0000 { 3333d3ebd4SChunyan Zhang compatible = "syscon"; 3433d3ebd4SChunyan Zhang reg = <0 0x402e0000 0 0x10000>; 3533d3ebd4SChunyan Zhang }; 3633d3ebd4SChunyan Zhang 3733d3ebd4SChunyan Zhang ana_regs: syscon@40400000 { 3833d3ebd4SChunyan Zhang compatible = "syscon"; 3933d3ebd4SChunyan Zhang reg = <0 0x40400000 0 0x10000>; 4033d3ebd4SChunyan Zhang }; 4133d3ebd4SChunyan Zhang 4233d3ebd4SChunyan Zhang agcp_regs: syscon@415e0000 { 4333d3ebd4SChunyan Zhang compatible = "syscon"; 4433d3ebd4SChunyan Zhang reg = <0 0x415e0000 0 0x1000000>; 4533d3ebd4SChunyan Zhang }; 4633d3ebd4SChunyan Zhang 4733d3ebd4SChunyan Zhang vsp_regs: syscon@61100000 { 4833d3ebd4SChunyan Zhang compatible = "syscon"; 4933d3ebd4SChunyan Zhang reg = <0 0x61100000 0 0x10000>; 5033d3ebd4SChunyan Zhang }; 5133d3ebd4SChunyan Zhang 5233d3ebd4SChunyan Zhang cam_regs: syscon@62100000 { 5333d3ebd4SChunyan Zhang compatible = "syscon"; 5433d3ebd4SChunyan Zhang reg = <0 0x62100000 0 0x10000>; 5533d3ebd4SChunyan Zhang }; 5633d3ebd4SChunyan Zhang 5733d3ebd4SChunyan Zhang disp_regs: syscon@63100000 { 5833d3ebd4SChunyan Zhang compatible = "syscon"; 5933d3ebd4SChunyan Zhang reg = <0 0x63100000 0 0x10000>; 6033d3ebd4SChunyan Zhang }; 6133d3ebd4SChunyan Zhang 6233d3ebd4SChunyan Zhang ap_apb_regs: syscon@70b00000 { 6333d3ebd4SChunyan Zhang compatible = "syscon"; 6433d3ebd4SChunyan Zhang reg = <0 0x70b00000 0 0x40000>; 6533d3ebd4SChunyan Zhang }; 6633d3ebd4SChunyan Zhang 673c0e3abdSOrson Zhai ap-apb { 683c0e3abdSOrson Zhai compatible = "simple-bus"; 693c0e3abdSOrson Zhai #address-cells = <1>; 703c0e3abdSOrson Zhai #size-cells = <1>; 713c0e3abdSOrson Zhai ranges = <0 0x0 0x70000000 0x10000000>; 723c0e3abdSOrson Zhai 733c0e3abdSOrson Zhai uart0: serial@0 { 743c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 753c0e3abdSOrson Zhai "sprd,sc9836-uart"; 763c0e3abdSOrson Zhai reg = <0x0 0x100>; 773c0e3abdSOrson Zhai interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 783c0e3abdSOrson Zhai clocks = <&ext_26m>; 793c0e3abdSOrson Zhai status = "disabled"; 803c0e3abdSOrson Zhai }; 813c0e3abdSOrson Zhai 823c0e3abdSOrson Zhai uart1: serial@100000 { 833c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 843c0e3abdSOrson Zhai "sprd,sc9836-uart"; 853c0e3abdSOrson Zhai reg = <0x100000 0x100>; 863c0e3abdSOrson Zhai interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 873c0e3abdSOrson Zhai clocks = <&ext_26m>; 883c0e3abdSOrson Zhai status = "disabled"; 893c0e3abdSOrson Zhai }; 903c0e3abdSOrson Zhai 913c0e3abdSOrson Zhai uart2: serial@200000 { 923c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 933c0e3abdSOrson Zhai "sprd,sc9836-uart"; 943c0e3abdSOrson Zhai reg = <0x200000 0x100>; 953c0e3abdSOrson Zhai interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 963c0e3abdSOrson Zhai clocks = <&ext_26m>; 973c0e3abdSOrson Zhai status = "disabled"; 983c0e3abdSOrson Zhai }; 993c0e3abdSOrson Zhai 1003c0e3abdSOrson Zhai uart3: serial@300000 { 1013c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 1023c0e3abdSOrson Zhai "sprd,sc9836-uart"; 1033c0e3abdSOrson Zhai reg = <0x300000 0x100>; 1043c0e3abdSOrson Zhai interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1053c0e3abdSOrson Zhai clocks = <&ext_26m>; 1063c0e3abdSOrson Zhai status = "disabled"; 1073c0e3abdSOrson Zhai }; 1083c0e3abdSOrson Zhai }; 1096c6fbbd1SBaolin Wang 110258e1ae6SBaolin Wang ap-ahb { 111258e1ae6SBaolin Wang compatible = "simple-bus"; 112258e1ae6SBaolin Wang #address-cells = <2>; 113258e1ae6SBaolin Wang #size-cells = <2>; 114258e1ae6SBaolin Wang ranges; 115258e1ae6SBaolin Wang 116258e1ae6SBaolin Wang ap_dma: dma-controller@20100000 { 117258e1ae6SBaolin Wang compatible = "sprd,sc9860-dma"; 118258e1ae6SBaolin Wang reg = <0 0x20100000 0 0x4000>; 119258e1ae6SBaolin Wang interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 120258e1ae6SBaolin Wang #dma-cells = <1>; 121258e1ae6SBaolin Wang #dma-channels = <32>; 122258e1ae6SBaolin Wang clock-names = "enable"; 123258e1ae6SBaolin Wang clocks = <&apahb_gate CLK_DMA_EB>; 124258e1ae6SBaolin Wang }; 125258e1ae6SBaolin Wang }; 126258e1ae6SBaolin Wang 1276c6fbbd1SBaolin Wang aon { 1286c6fbbd1SBaolin Wang compatible = "simple-bus"; 1296c6fbbd1SBaolin Wang #address-cells = <2>; 1306c6fbbd1SBaolin Wang #size-cells = <2>; 1316c6fbbd1SBaolin Wang ranges; 1326c6fbbd1SBaolin Wang 133e254460aSBaolin Wang adi_bus: spi@40030000 { 134e254460aSBaolin Wang compatible = "sprd,sc9860-adi"; 135e254460aSBaolin Wang reg = <0 0x40030000 0 0x10000>; 136e254460aSBaolin Wang hwlocks = <&hwlock 0>; 137e254460aSBaolin Wang hwlock-names = "adi"; 138e254460aSBaolin Wang #address-cells = <1>; 139e254460aSBaolin Wang #size-cells = <0>; 140e254460aSBaolin Wang }; 141e254460aSBaolin Wang 1420cb3dad0SBaolin Wang timer@40050000 { 1430cb3dad0SBaolin Wang compatible = "sprd,sc9860-timer"; 1440cb3dad0SBaolin Wang reg = <0 0x40050000 0 0x20>; 1450cb3dad0SBaolin Wang interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1460cb3dad0SBaolin Wang clocks = <&ext_32k>; 1470cb3dad0SBaolin Wang }; 1480cb3dad0SBaolin Wang 1496c6fbbd1SBaolin Wang hwlock: hwspinlock@40500000 { 1506c6fbbd1SBaolin Wang compatible = "sprd,hwspinlock-r3p0"; 1516c6fbbd1SBaolin Wang reg = <0 0x40500000 0 0x1000>; 1526c6fbbd1SBaolin Wang #hwlock-cells = <1>; 1536c6fbbd1SBaolin Wang clock-names = "enable"; 1546c6fbbd1SBaolin Wang clocks = <&aon_gate CLK_SPLK_EB>; 1556c6fbbd1SBaolin Wang }; 156d85bcd9cSBaolin Wang 1571cea2c22SBaolin Wang eic_debounce: gpio@40210000 { 1581cea2c22SBaolin Wang compatible = "sprd,sc9860-eic-debounce"; 1591cea2c22SBaolin Wang reg = <0 0x40210000 0 0x80>; 1601cea2c22SBaolin Wang gpio-controller; 1611cea2c22SBaolin Wang #gpio-cells = <2>; 1621cea2c22SBaolin Wang interrupt-controller; 1631cea2c22SBaolin Wang #interrupt-cells = <2>; 1641cea2c22SBaolin Wang interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1651cea2c22SBaolin Wang }; 1661cea2c22SBaolin Wang 1671cea2c22SBaolin Wang eic_latch: gpio@40210080 { 1681cea2c22SBaolin Wang compatible = "sprd,sc9860-eic-latch"; 1691cea2c22SBaolin Wang reg = <0 0x40210080 0 0x20>; 1701cea2c22SBaolin Wang gpio-controller; 1711cea2c22SBaolin Wang #gpio-cells = <2>; 1721cea2c22SBaolin Wang interrupt-controller; 1731cea2c22SBaolin Wang #interrupt-cells = <2>; 1741cea2c22SBaolin Wang interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1751cea2c22SBaolin Wang }; 1761cea2c22SBaolin Wang 1771cea2c22SBaolin Wang eic_async: gpio@402100a0 { 1781cea2c22SBaolin Wang compatible = "sprd,sc9860-eic-async"; 1791cea2c22SBaolin Wang reg = <0 0x402100a0 0 0x20>; 1801cea2c22SBaolin Wang gpio-controller; 1811cea2c22SBaolin Wang #gpio-cells = <2>; 1821cea2c22SBaolin Wang interrupt-controller; 1831cea2c22SBaolin Wang #interrupt-cells = <2>; 1841cea2c22SBaolin Wang interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1851cea2c22SBaolin Wang }; 1861cea2c22SBaolin Wang 1871cea2c22SBaolin Wang eic_sync: gpio@402100c0 { 1881cea2c22SBaolin Wang compatible = "sprd,sc9860-eic-sync"; 1891cea2c22SBaolin Wang reg = <0 0x402100c0 0 0x20>; 1901cea2c22SBaolin Wang gpio-controller; 1911cea2c22SBaolin Wang #gpio-cells = <2>; 1921cea2c22SBaolin Wang interrupt-controller; 1931cea2c22SBaolin Wang #interrupt-cells = <2>; 1941cea2c22SBaolin Wang interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1951cea2c22SBaolin Wang }; 1961cea2c22SBaolin Wang 1971cea2c22SBaolin Wang ap_gpio: gpio@40280000 { 1981cea2c22SBaolin Wang compatible = "sprd,sc9860-gpio"; 1991cea2c22SBaolin Wang reg = <0 0x40280000 0 0x1000>; 2001cea2c22SBaolin Wang gpio-controller; 2011cea2c22SBaolin Wang #gpio-cells = <2>; 2021cea2c22SBaolin Wang interrupt-controller; 2031cea2c22SBaolin Wang #interrupt-cells = <2>; 2041cea2c22SBaolin Wang interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 2051cea2c22SBaolin Wang }; 2061cea2c22SBaolin Wang 207d85bcd9cSBaolin Wang pin_controller: pinctrl@402a0000 { 208d85bcd9cSBaolin Wang compatible = "sprd,sc9860-pinctrl"; 209d85bcd9cSBaolin Wang reg = <0 0x402a0000 0 0x10000>; 210d85bcd9cSBaolin Wang }; 2114f681369SBaolin Wang 2124f681369SBaolin Wang watchdog@40310000 { 2134f681369SBaolin Wang compatible = "sprd,sp9860-wdt"; 2144f681369SBaolin Wang reg = <0 0x40310000 0 0x1000>; 2154f681369SBaolin Wang interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 2164f681369SBaolin Wang timeout-sec = <12>; 21721a9883fSBaolin Wang clock-names = "enable", "rtc_enable"; 21821a9883fSBaolin Wang clocks = <&aon_gate CLK_APCPU_WDG_EB>, 21921a9883fSBaolin Wang <&aon_gate CLK_AP_WDG_RTC_EB>; 2204f681369SBaolin Wang }; 2216c6fbbd1SBaolin Wang }; 222258e1ae6SBaolin Wang 223258e1ae6SBaolin Wang agcp { 224258e1ae6SBaolin Wang compatible = "simple-bus"; 225258e1ae6SBaolin Wang #address-cells = <2>; 226258e1ae6SBaolin Wang #size-cells = <2>; 227258e1ae6SBaolin Wang ranges; 228258e1ae6SBaolin Wang 229258e1ae6SBaolin Wang agcp_dma: dma-controller@41580000 { 230258e1ae6SBaolin Wang compatible = "sprd,sc9860-dma"; 231258e1ae6SBaolin Wang reg = <0 0x41580000 0 0x4000>; 232258e1ae6SBaolin Wang #dma-cells = <1>; 233258e1ae6SBaolin Wang #dma-channels = <32>; 234258e1ae6SBaolin Wang clock-names = "enable", "ashb_eb"; 235258e1ae6SBaolin Wang clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, 236258e1ae6SBaolin Wang <&agcp_gate CLK_AGCP_AP_ASHB_EB>; 237258e1ae6SBaolin Wang }; 238258e1ae6SBaolin Wang }; 2393c0e3abdSOrson Zhai }; 2403c0e3abdSOrson Zhai 24122f37a24SChunyan Zhang ext_32k: ext_32k { 24222f37a24SChunyan Zhang compatible = "fixed-clock"; 24322f37a24SChunyan Zhang #clock-cells = <0>; 24422f37a24SChunyan Zhang clock-frequency = <32768>; 24522f37a24SChunyan Zhang clock-output-names = "ext-32k"; 24622f37a24SChunyan Zhang }; 24722f37a24SChunyan Zhang 24822f37a24SChunyan Zhang ext_26m: ext_26m { 2493c0e3abdSOrson Zhai compatible = "fixed-clock"; 2503c0e3abdSOrson Zhai #clock-cells = <0>; 2513c0e3abdSOrson Zhai clock-frequency = <26000000>; 25222f37a24SChunyan Zhang clock-output-names = "ext-26m"; 25322f37a24SChunyan Zhang }; 25422f37a24SChunyan Zhang 25522f37a24SChunyan Zhang ext_rco_100m: ext_rco_100m { 25622f37a24SChunyan Zhang compatible = "fixed-clock"; 25722f37a24SChunyan Zhang #clock-cells = <0>; 25822f37a24SChunyan Zhang clock-frequency = <100000000>; 25922f37a24SChunyan Zhang clock-output-names = "ext-rco-100m"; 2603c0e3abdSOrson Zhai }; 2613c0e3abdSOrson Zhai}; 262