13c0e3abdSOrson Zhai/* 23c0e3abdSOrson Zhai * Spreadtrum Whale2 platform peripherals 33c0e3abdSOrson Zhai * 43c0e3abdSOrson Zhai * Copyright (C) 2016, Spreadtrum Communications Inc. 53c0e3abdSOrson Zhai * 63c0e3abdSOrson Zhai * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 73c0e3abdSOrson Zhai */ 83c0e3abdSOrson Zhai 96c6fbbd1SBaolin Wang#include <dt-bindings/clock/sprd,sc9860-clk.h> 106c6fbbd1SBaolin Wang 113c0e3abdSOrson Zhai/ { 123c0e3abdSOrson Zhai interrupt-parent = <&gic>; 133c0e3abdSOrson Zhai #address-cells = <2>; 143c0e3abdSOrson Zhai #size-cells = <2>; 153c0e3abdSOrson Zhai 163c0e3abdSOrson Zhai soc: soc { 173c0e3abdSOrson Zhai compatible = "simple-bus"; 183c0e3abdSOrson Zhai #address-cells = <2>; 193c0e3abdSOrson Zhai #size-cells = <2>; 203c0e3abdSOrson Zhai ranges; 213c0e3abdSOrson Zhai 2233d3ebd4SChunyan Zhang ap_ahb_regs: syscon@20210000 { 2333d3ebd4SChunyan Zhang compatible = "syscon"; 2433d3ebd4SChunyan Zhang reg = <0 0x20210000 0 0x10000>; 2533d3ebd4SChunyan Zhang }; 2633d3ebd4SChunyan Zhang 2733d3ebd4SChunyan Zhang pmu_regs: syscon@402b0000 { 2833d3ebd4SChunyan Zhang compatible = "syscon"; 2933d3ebd4SChunyan Zhang reg = <0 0x402b0000 0 0x10000>; 3033d3ebd4SChunyan Zhang }; 3133d3ebd4SChunyan Zhang 3233d3ebd4SChunyan Zhang aon_regs: syscon@402e0000 { 3333d3ebd4SChunyan Zhang compatible = "syscon"; 3433d3ebd4SChunyan Zhang reg = <0 0x402e0000 0 0x10000>; 3533d3ebd4SChunyan Zhang }; 3633d3ebd4SChunyan Zhang 3733d3ebd4SChunyan Zhang ana_regs: syscon@40400000 { 3833d3ebd4SChunyan Zhang compatible = "syscon"; 3933d3ebd4SChunyan Zhang reg = <0 0x40400000 0 0x10000>; 4033d3ebd4SChunyan Zhang }; 4133d3ebd4SChunyan Zhang 4233d3ebd4SChunyan Zhang agcp_regs: syscon@415e0000 { 4333d3ebd4SChunyan Zhang compatible = "syscon"; 4433d3ebd4SChunyan Zhang reg = <0 0x415e0000 0 0x1000000>; 4533d3ebd4SChunyan Zhang }; 4633d3ebd4SChunyan Zhang 4733d3ebd4SChunyan Zhang vsp_regs: syscon@61100000 { 4833d3ebd4SChunyan Zhang compatible = "syscon"; 4933d3ebd4SChunyan Zhang reg = <0 0x61100000 0 0x10000>; 5033d3ebd4SChunyan Zhang }; 5133d3ebd4SChunyan Zhang 5233d3ebd4SChunyan Zhang cam_regs: syscon@62100000 { 5333d3ebd4SChunyan Zhang compatible = "syscon"; 5433d3ebd4SChunyan Zhang reg = <0 0x62100000 0 0x10000>; 5533d3ebd4SChunyan Zhang }; 5633d3ebd4SChunyan Zhang 5733d3ebd4SChunyan Zhang disp_regs: syscon@63100000 { 5833d3ebd4SChunyan Zhang compatible = "syscon"; 5933d3ebd4SChunyan Zhang reg = <0 0x63100000 0 0x10000>; 6033d3ebd4SChunyan Zhang }; 6133d3ebd4SChunyan Zhang 6233d3ebd4SChunyan Zhang ap_apb_regs: syscon@70b00000 { 6333d3ebd4SChunyan Zhang compatible = "syscon"; 6433d3ebd4SChunyan Zhang reg = <0 0x70b00000 0 0x40000>; 6533d3ebd4SChunyan Zhang }; 6633d3ebd4SChunyan Zhang 673c0e3abdSOrson Zhai ap-apb { 683c0e3abdSOrson Zhai compatible = "simple-bus"; 693c0e3abdSOrson Zhai #address-cells = <1>; 703c0e3abdSOrson Zhai #size-cells = <1>; 713c0e3abdSOrson Zhai ranges = <0 0x0 0x70000000 0x10000000>; 723c0e3abdSOrson Zhai 733c0e3abdSOrson Zhai uart0: serial@0 { 743c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 753c0e3abdSOrson Zhai "sprd,sc9836-uart"; 763c0e3abdSOrson Zhai reg = <0x0 0x100>; 773c0e3abdSOrson Zhai interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 783c0e3abdSOrson Zhai clocks = <&ext_26m>; 793c0e3abdSOrson Zhai status = "disabled"; 803c0e3abdSOrson Zhai }; 813c0e3abdSOrson Zhai 823c0e3abdSOrson Zhai uart1: serial@100000 { 833c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 843c0e3abdSOrson Zhai "sprd,sc9836-uart"; 853c0e3abdSOrson Zhai reg = <0x100000 0x100>; 863c0e3abdSOrson Zhai interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 873c0e3abdSOrson Zhai clocks = <&ext_26m>; 883c0e3abdSOrson Zhai status = "disabled"; 893c0e3abdSOrson Zhai }; 903c0e3abdSOrson Zhai 913c0e3abdSOrson Zhai uart2: serial@200000 { 923c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 933c0e3abdSOrson Zhai "sprd,sc9836-uart"; 943c0e3abdSOrson Zhai reg = <0x200000 0x100>; 953c0e3abdSOrson Zhai interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 963c0e3abdSOrson Zhai clocks = <&ext_26m>; 973c0e3abdSOrson Zhai status = "disabled"; 983c0e3abdSOrson Zhai }; 993c0e3abdSOrson Zhai 1003c0e3abdSOrson Zhai uart3: serial@300000 { 1013c0e3abdSOrson Zhai compatible = "sprd,sc9860-uart", 1023c0e3abdSOrson Zhai "sprd,sc9836-uart"; 1033c0e3abdSOrson Zhai reg = <0x300000 0x100>; 1043c0e3abdSOrson Zhai interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1053c0e3abdSOrson Zhai clocks = <&ext_26m>; 1063c0e3abdSOrson Zhai status = "disabled"; 1073c0e3abdSOrson Zhai }; 1083c0e3abdSOrson Zhai }; 1096c6fbbd1SBaolin Wang 1106c6fbbd1SBaolin Wang aon { 1116c6fbbd1SBaolin Wang compatible = "simple-bus"; 1126c6fbbd1SBaolin Wang #address-cells = <2>; 1136c6fbbd1SBaolin Wang #size-cells = <2>; 1146c6fbbd1SBaolin Wang ranges; 1156c6fbbd1SBaolin Wang 116e254460aSBaolin Wang adi_bus: spi@40030000 { 117e254460aSBaolin Wang compatible = "sprd,sc9860-adi"; 118e254460aSBaolin Wang reg = <0 0x40030000 0 0x10000>; 119e254460aSBaolin Wang hwlocks = <&hwlock 0>; 120e254460aSBaolin Wang hwlock-names = "adi"; 121e254460aSBaolin Wang #address-cells = <1>; 122e254460aSBaolin Wang #size-cells = <0>; 123e254460aSBaolin Wang }; 124e254460aSBaolin Wang 1250cb3dad0SBaolin Wang timer@40050000 { 1260cb3dad0SBaolin Wang compatible = "sprd,sc9860-timer"; 1270cb3dad0SBaolin Wang reg = <0 0x40050000 0 0x20>; 1280cb3dad0SBaolin Wang interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1290cb3dad0SBaolin Wang clocks = <&ext_32k>; 1300cb3dad0SBaolin Wang }; 1310cb3dad0SBaolin Wang 1326c6fbbd1SBaolin Wang hwlock: hwspinlock@40500000 { 1336c6fbbd1SBaolin Wang compatible = "sprd,hwspinlock-r3p0"; 1346c6fbbd1SBaolin Wang reg = <0 0x40500000 0 0x1000>; 1356c6fbbd1SBaolin Wang #hwlock-cells = <1>; 1366c6fbbd1SBaolin Wang clock-names = "enable"; 1376c6fbbd1SBaolin Wang clocks = <&aon_gate CLK_SPLK_EB>; 1386c6fbbd1SBaolin Wang }; 139d85bcd9cSBaolin Wang 140d85bcd9cSBaolin Wang pin_controller: pinctrl@402a0000 { 141d85bcd9cSBaolin Wang compatible = "sprd,sc9860-pinctrl"; 142d85bcd9cSBaolin Wang reg = <0 0x402a0000 0 0x10000>; 143d85bcd9cSBaolin Wang }; 1446c6fbbd1SBaolin Wang }; 1453c0e3abdSOrson Zhai }; 1463c0e3abdSOrson Zhai 14722f37a24SChunyan Zhang ext_32k: ext_32k { 14822f37a24SChunyan Zhang compatible = "fixed-clock"; 14922f37a24SChunyan Zhang #clock-cells = <0>; 15022f37a24SChunyan Zhang clock-frequency = <32768>; 15122f37a24SChunyan Zhang clock-output-names = "ext-32k"; 15222f37a24SChunyan Zhang }; 15322f37a24SChunyan Zhang 15422f37a24SChunyan Zhang ext_26m: ext_26m { 1553c0e3abdSOrson Zhai compatible = "fixed-clock"; 1563c0e3abdSOrson Zhai #clock-cells = <0>; 1573c0e3abdSOrson Zhai clock-frequency = <26000000>; 15822f37a24SChunyan Zhang clock-output-names = "ext-26m"; 15922f37a24SChunyan Zhang }; 16022f37a24SChunyan Zhang 16122f37a24SChunyan Zhang ext_rco_100m: ext_rco_100m { 16222f37a24SChunyan Zhang compatible = "fixed-clock"; 16322f37a24SChunyan Zhang #clock-cells = <0>; 16422f37a24SChunyan Zhang clock-frequency = <100000000>; 16522f37a24SChunyan Zhang clock-output-names = "ext-rco-100m"; 1663c0e3abdSOrson Zhai }; 1673c0e3abdSOrson Zhai}; 168