1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Unisoc SC9863A SoC DTS file 4 * 5 * Copyright (C) 2019, Unisoc Inc. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include "sharkl3.dtsi" 10 11/ { 12 cpus { 13 #address-cells = <2>; 14 #size-cells = <0>; 15 16 cpu-map { 17 cluster0 { 18 core0 { 19 cpu = <&CPU0>; 20 }; 21 core1 { 22 cpu = <&CPU1>; 23 }; 24 core2 { 25 cpu = <&CPU2>; 26 }; 27 core3 { 28 cpu = <&CPU3>; 29 }; 30 core4 { 31 cpu = <&CPU4>; 32 }; 33 core5 { 34 cpu = <&CPU5>; 35 }; 36 core6 { 37 cpu = <&CPU6>; 38 }; 39 core7 { 40 cpu = <&CPU7>; 41 }; 42 }; 43 }; 44 45 CPU0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a55"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 cpu-idle-states = <&CORE_PD>; 51 }; 52 53 CPU1: cpu@100 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x0 0x100>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CORE_PD>; 59 }; 60 61 CPU2: cpu@200 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a55"; 64 reg = <0x0 0x200>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CORE_PD>; 67 }; 68 69 CPU3: cpu@300 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a55"; 72 reg = <0x0 0x300>; 73 enable-method = "psci"; 74 cpu-idle-states = <&CORE_PD>; 75 }; 76 77 CPU4: cpu@400 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x0 0x400>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CORE_PD>; 83 }; 84 85 CPU5: cpu@500 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a55"; 88 reg = <0x0 0x500>; 89 enable-method = "psci"; 90 cpu-idle-states = <&CORE_PD>; 91 }; 92 93 CPU6: cpu@600 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x0 0x600>; 97 enable-method = "psci"; 98 cpu-idle-states = <&CORE_PD>; 99 }; 100 101 CPU7: cpu@700 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0 0x700>; 105 enable-method = "psci"; 106 cpu-idle-states = <&CORE_PD>; 107 }; 108 }; 109 110 idle-states { 111 entry-method = "psci"; 112 CORE_PD: core-pd { 113 compatible = "arm,idle-state"; 114 entry-latency-us = <4000>; 115 exit-latency-us = <4000>; 116 min-residency-us = <10000>; 117 local-timer-stop; 118 arm,psci-suspend-param = <0x00010000>; 119 }; 120 }; 121 122 psci { 123 compatible = "arm,psci-0.2"; 124 method = "smc"; 125 }; 126 127 timer { 128 compatible = "arm,armv8-timer"; 129 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ 130 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ 131 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ 132 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ 133 }; 134 135 pmu { 136 compatible = "arm,armv8-pmuv3"; 137 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 145 }; 146 147 soc { 148 gic: interrupt-controller@14000000 { 149 compatible = "arm,gic-v3"; 150 #interrupt-cells = <3>; 151 #address-cells = <2>; 152 #size-cells = <2>; 153 ranges; 154 redistributor-stride = <0x0 0x20000>; /* 128KB stride */ 155 #redistributor-regions = <1>; 156 interrupt-controller; 157 reg = <0x0 0x14000000 0 0x20000>, /* GICD */ 158 <0x0 0x14040000 0 0x100000>; /* GICR */ 159 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 162 ap_clk: clock-controller@21500000 { 163 compatible = "sprd,sc9863a-ap-clk"; 164 reg = <0 0x21500000 0 0x1000>; 165 clocks = <&ext_32k>, <&ext_26m>; 166 clock-names = "ext-32k", "ext-26m"; 167 #clock-cells = <1>; 168 }; 169 170 aon_clk: clock-controller@402d0000 { 171 compatible = "sprd,sc9863a-aon-clk"; 172 reg = <0 0x402d0000 0 0x1000>; 173 clocks = <&ext_26m>, <&rco_100m>, 174 <&ext_32k>, <&ext_4m>; 175 clock-names = "ext-26m", "rco-100m", 176 "ext-32k", "ext-4m"; 177 #clock-cells = <1>; 178 }; 179 180 mm_clk: clock-controller@60900000 { 181 compatible = "sprd,sc9863a-mm-clk"; 182 reg = <0 0x60900000 0 0x1000>; 183 #clock-cells = <1>; 184 }; 185 186 funnel@10001000 { 187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 188 reg = <0 0x10001000 0 0x1000>; 189 clocks = <&ext_26m>; 190 clock-names = "apb_pclk"; 191 192 out-ports { 193 port { 194 funnel_soc_out_port: endpoint { 195 remote-endpoint = <&etb_in>; 196 }; 197 }; 198 }; 199 200 in-ports { 201 port { 202 funnel_soc_in_port: endpoint { 203 remote-endpoint = 204 <&funnel_ca55_out_port>; 205 }; 206 }; 207 }; 208 }; 209 210 etb@10003000 { 211 compatible = "arm,coresight-tmc", "arm,primecell"; 212 reg = <0 0x10003000 0 0x1000>; 213 clocks = <&ext_26m>; 214 clock-names = "apb_pclk"; 215 216 in-ports { 217 port { 218 etb_in: endpoint { 219 remote-endpoint = 220 <&funnel_soc_out_port>; 221 }; 222 }; 223 }; 224 }; 225 226 funnel@12001000 { 227 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 228 reg = <0 0x12001000 0 0x1000>; 229 clocks = <&ext_26m>; 230 clock-names = "apb_pclk"; 231 232 out-ports { 233 port { 234 funnel_little_out_port: endpoint { 235 remote-endpoint = 236 <&etf_little_in>; 237 }; 238 }; 239 }; 240 241 in-ports { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 port@0 { 246 reg = <0>; 247 funnel_little_in_port0: endpoint { 248 remote-endpoint = <&etm0_out>; 249 }; 250 }; 251 252 port@1 { 253 reg = <1>; 254 funnel_little_in_port1: endpoint { 255 remote-endpoint = <&etm1_out>; 256 }; 257 }; 258 259 port@2 { 260 reg = <2>; 261 funnel_little_in_port2: endpoint { 262 remote-endpoint = <&etm2_out>; 263 }; 264 }; 265 266 port@3 { 267 reg = <3>; 268 funnel_little_in_port3: endpoint { 269 remote-endpoint = <&etm3_out>; 270 }; 271 }; 272 }; 273 }; 274 275 etf@12002000 { 276 compatible = "arm,coresight-tmc", "arm,primecell"; 277 reg = <0 0x12002000 0 0x1000>; 278 clocks = <&ext_26m>; 279 clock-names = "apb_pclk"; 280 281 out-ports { 282 port { 283 etf_little_out: endpoint { 284 remote-endpoint = 285 <&funnel_ca55_in_port0>; 286 }; 287 }; 288 }; 289 290 in-port { 291 port { 292 etf_little_in: endpoint { 293 remote-endpoint = 294 <&funnel_little_out_port>; 295 }; 296 }; 297 }; 298 }; 299 300 etf@12003000 { 301 compatible = "arm,coresight-tmc", "arm,primecell"; 302 reg = <0 0x12003000 0 0x1000>; 303 clocks = <&ext_26m>; 304 clock-names = "apb_pclk"; 305 306 out-ports { 307 port { 308 etf_big_out: endpoint { 309 remote-endpoint = 310 <&funnel_ca55_in_port1>; 311 }; 312 }; 313 }; 314 315 in-ports { 316 port { 317 etf_big_in: endpoint { 318 remote-endpoint = 319 <&funnel_big_out_port>; 320 }; 321 }; 322 }; 323 }; 324 325 funnel@12004000 { 326 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 327 reg = <0 0x12004000 0 0x1000>; 328 clocks = <&ext_26m>; 329 clock-names = "apb_pclk"; 330 331 out-ports { 332 port { 333 funnel_ca55_out_port: endpoint { 334 remote-endpoint = 335 <&funnel_soc_in_port>; 336 }; 337 }; 338 }; 339 340 in-ports { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 344 port@0 { 345 reg = <0>; 346 funnel_ca55_in_port0: endpoint { 347 remote-endpoint = 348 <&etf_little_out>; 349 }; 350 }; 351 352 port@1 { 353 reg = <1>; 354 funnel_ca55_in_port1: endpoint { 355 remote-endpoint = 356 <&etf_big_out>; 357 }; 358 }; 359 }; 360 }; 361 362 funnel@12005000 { 363 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 364 reg = <0 0x12005000 0 0x1000>; 365 clocks = <&ext_26m>; 366 clock-names = "apb_pclk"; 367 368 out-ports { 369 port { 370 funnel_big_out_port: endpoint { 371 remote-endpoint = 372 <&etf_big_in>; 373 }; 374 }; 375 }; 376 377 in-ports { 378 #address-cells = <1>; 379 #size-cells = <0>; 380 381 port@0 { 382 reg = <0>; 383 funnel_big_in_port0: endpoint { 384 remote-endpoint = <&etm4_out>; 385 }; 386 }; 387 388 port@1 { 389 reg = <1>; 390 funnel_big_in_port1: endpoint { 391 remote-endpoint = <&etm5_out>; 392 }; 393 }; 394 395 port@2 { 396 reg = <2>; 397 funnel_big_in_port2: endpoint { 398 remote-endpoint = <&etm6_out>; 399 }; 400 }; 401 402 port@3 { 403 reg = <3>; 404 funnel_big_in_port3: endpoint { 405 remote-endpoint = <&etm7_out>; 406 }; 407 }; 408 }; 409 }; 410 411 etm@13040000 { 412 compatible = "arm,coresight-etm4x", "arm,primecell"; 413 reg = <0 0x13040000 0 0x1000>; 414 cpu = <&CPU0>; 415 clocks = <&ext_26m>; 416 clock-names = "apb_pclk"; 417 418 out-ports { 419 port { 420 etm0_out: endpoint { 421 remote-endpoint = 422 <&funnel_little_in_port0>; 423 }; 424 }; 425 }; 426 }; 427 428 etm@13140000 { 429 compatible = "arm,coresight-etm4x", "arm,primecell"; 430 reg = <0 0x13140000 0 0x1000>; 431 cpu = <&CPU1>; 432 clocks = <&ext_26m>; 433 clock-names = "apb_pclk"; 434 435 out-ports { 436 port { 437 etm1_out: endpoint { 438 remote-endpoint = 439 <&funnel_little_in_port1>; 440 }; 441 }; 442 }; 443 }; 444 445 etm@13240000 { 446 compatible = "arm,coresight-etm4x", "arm,primecell"; 447 reg = <0 0x13240000 0 0x1000>; 448 cpu = <&CPU2>; 449 clocks = <&ext_26m>; 450 clock-names = "apb_pclk"; 451 452 out-ports { 453 port { 454 etm2_out: endpoint { 455 remote-endpoint = 456 <&funnel_little_in_port2>; 457 }; 458 }; 459 }; 460 }; 461 462 etm@13340000 { 463 compatible = "arm,coresight-etm4x", "arm,primecell"; 464 reg = <0 0x13340000 0 0x1000>; 465 cpu = <&CPU3>; 466 clocks = <&ext_26m>; 467 clock-names = "apb_pclk"; 468 469 out-ports { 470 port { 471 etm3_out: endpoint { 472 remote-endpoint = 473 <&funnel_little_in_port3>; 474 }; 475 }; 476 }; 477 }; 478 479 etm@13440000 { 480 compatible = "arm,coresight-etm4x", "arm,primecell"; 481 reg = <0 0x13440000 0 0x1000>; 482 cpu = <&CPU4>; 483 clocks = <&ext_26m>; 484 clock-names = "apb_pclk"; 485 486 out-ports { 487 port { 488 etm4_out: endpoint { 489 remote-endpoint = 490 <&funnel_big_in_port0>; 491 }; 492 }; 493 }; 494 }; 495 496 etm@13540000 { 497 compatible = "arm,coresight-etm4x", "arm,primecell"; 498 reg = <0 0x13540000 0 0x1000>; 499 cpu = <&CPU5>; 500 clocks = <&ext_26m>; 501 clock-names = "apb_pclk"; 502 503 out-ports { 504 port { 505 etm5_out: endpoint { 506 remote-endpoint = 507 <&funnel_big_in_port1>; 508 }; 509 }; 510 }; 511 }; 512 513 etm@13640000 { 514 compatible = "arm,coresight-etm4x", "arm,primecell"; 515 reg = <0 0x13640000 0 0x1000>; 516 cpu = <&CPU6>; 517 clocks = <&ext_26m>; 518 clock-names = "apb_pclk"; 519 520 out-ports { 521 port { 522 etm6_out: endpoint { 523 remote-endpoint = 524 <&funnel_big_in_port2>; 525 }; 526 }; 527 }; 528 }; 529 530 etm@13740000 { 531 compatible = "arm,coresight-etm4x", "arm,primecell"; 532 reg = <0 0x13740000 0 0x1000>; 533 cpu = <&CPU7>; 534 clocks = <&ext_26m>; 535 clock-names = "apb_pclk"; 536 537 out-ports { 538 port { 539 etm7_out: endpoint { 540 remote-endpoint = 541 <&funnel_big_in_port3>; 542 }; 543 }; 544 }; 545 }; 546 }; 547}; 548