13c0e3abdSOrson Zhai/* 23c0e3abdSOrson Zhai * Spreadtrum SC9860 SoC 33c0e3abdSOrson Zhai * 43c0e3abdSOrson Zhai * Copyright (C) 2016, Spreadtrum Communications Inc. 53c0e3abdSOrson Zhai * 63c0e3abdSOrson Zhai * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 73c0e3abdSOrson Zhai */ 83c0e3abdSOrson Zhai 93c0e3abdSOrson Zhai#include <dt-bindings/interrupt-controller/arm-gic.h> 103c0e3abdSOrson Zhai#include "whale2.dtsi" 113c0e3abdSOrson Zhai 123c0e3abdSOrson Zhai/ { 133c0e3abdSOrson Zhai cpus { 143c0e3abdSOrson Zhai #address-cells = <2>; 153c0e3abdSOrson Zhai #size-cells = <0>; 163c0e3abdSOrson Zhai 173c0e3abdSOrson Zhai cpu-map { 183c0e3abdSOrson Zhai cluster0 { 193c0e3abdSOrson Zhai core0 { 203c0e3abdSOrson Zhai cpu = <&CPU0>; 213c0e3abdSOrson Zhai }; 223c0e3abdSOrson Zhai core1 { 233c0e3abdSOrson Zhai cpu = <&CPU1>; 243c0e3abdSOrson Zhai }; 253c0e3abdSOrson Zhai core2 { 263c0e3abdSOrson Zhai cpu = <&CPU2>; 273c0e3abdSOrson Zhai }; 283c0e3abdSOrson Zhai core3 { 293c0e3abdSOrson Zhai cpu = <&CPU3>; 303c0e3abdSOrson Zhai }; 313c0e3abdSOrson Zhai }; 323c0e3abdSOrson Zhai 333c0e3abdSOrson Zhai cluster1 { 343c0e3abdSOrson Zhai core0 { 353c0e3abdSOrson Zhai cpu = <&CPU4>; 363c0e3abdSOrson Zhai }; 373c0e3abdSOrson Zhai core1 { 383c0e3abdSOrson Zhai cpu = <&CPU5>; 393c0e3abdSOrson Zhai }; 403c0e3abdSOrson Zhai core2 { 413c0e3abdSOrson Zhai cpu = <&CPU6>; 423c0e3abdSOrson Zhai }; 433c0e3abdSOrson Zhai core3 { 443c0e3abdSOrson Zhai cpu = <&CPU7>; 453c0e3abdSOrson Zhai }; 463c0e3abdSOrson Zhai }; 473c0e3abdSOrson Zhai }; 483c0e3abdSOrson Zhai 493c0e3abdSOrson Zhai CPU0: cpu@530000 { 503c0e3abdSOrson Zhai device_type = "cpu"; 513c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 523c0e3abdSOrson Zhai reg = <0x0 0x530000>; 533c0e3abdSOrson Zhai enable-method = "psci"; 543c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 553c0e3abdSOrson Zhai }; 563c0e3abdSOrson Zhai 573c0e3abdSOrson Zhai CPU1: cpu@530001 { 583c0e3abdSOrson Zhai device_type = "cpu"; 593c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 603c0e3abdSOrson Zhai reg = <0x0 0x530001>; 613c0e3abdSOrson Zhai enable-method = "psci"; 623c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 633c0e3abdSOrson Zhai }; 643c0e3abdSOrson Zhai 653c0e3abdSOrson Zhai CPU2: cpu@530002 { 663c0e3abdSOrson Zhai device_type = "cpu"; 673c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 683c0e3abdSOrson Zhai reg = <0x0 0x530002>; 693c0e3abdSOrson Zhai enable-method = "psci"; 703c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 713c0e3abdSOrson Zhai }; 723c0e3abdSOrson Zhai 733c0e3abdSOrson Zhai CPU3: cpu@530003 { 743c0e3abdSOrson Zhai device_type = "cpu"; 753c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 763c0e3abdSOrson Zhai reg = <0x0 0x530003>; 773c0e3abdSOrson Zhai enable-method = "psci"; 783c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 793c0e3abdSOrson Zhai }; 803c0e3abdSOrson Zhai 813c0e3abdSOrson Zhai CPU4: cpu@530100 { 823c0e3abdSOrson Zhai device_type = "cpu"; 833c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 843c0e3abdSOrson Zhai reg = <0x0 0x530100>; 853c0e3abdSOrson Zhai enable-method = "psci"; 863c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 873c0e3abdSOrson Zhai }; 883c0e3abdSOrson Zhai 893c0e3abdSOrson Zhai CPU5: cpu@530101 { 903c0e3abdSOrson Zhai device_type = "cpu"; 913c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 923c0e3abdSOrson Zhai reg = <0x0 0x530101>; 933c0e3abdSOrson Zhai enable-method = "psci"; 943c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 953c0e3abdSOrson Zhai }; 963c0e3abdSOrson Zhai 973c0e3abdSOrson Zhai CPU6: cpu@530102 { 983c0e3abdSOrson Zhai device_type = "cpu"; 993c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 1003c0e3abdSOrson Zhai reg = <0x0 0x530102>; 1013c0e3abdSOrson Zhai enable-method = "psci"; 1023c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 1033c0e3abdSOrson Zhai }; 1043c0e3abdSOrson Zhai 1053c0e3abdSOrson Zhai CPU7: cpu@530103 { 1063c0e3abdSOrson Zhai device_type = "cpu"; 1073c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 1083c0e3abdSOrson Zhai reg = <0x0 0x530103>; 1093c0e3abdSOrson Zhai enable-method = "psci"; 1103c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 1113c0e3abdSOrson Zhai }; 1123c0e3abdSOrson Zhai }; 1133c0e3abdSOrson Zhai 1143c0e3abdSOrson Zhai idle-states{ 1153c0e3abdSOrson Zhai entry-method = "arm,psci"; 1163c0e3abdSOrson Zhai 1173c0e3abdSOrson Zhai CORE_PD: core_pd { 1183c0e3abdSOrson Zhai compatible = "arm,idle-state"; 1193c0e3abdSOrson Zhai entry-latency-us = <1000>; 1203c0e3abdSOrson Zhai exit-latency-us = <700>; 1213c0e3abdSOrson Zhai min-residency-us = <2500>; 1223c0e3abdSOrson Zhai local-timer-stop; 1233c0e3abdSOrson Zhai arm,psci-suspend-param = <0x00010002>; 1243c0e3abdSOrson Zhai }; 1253c0e3abdSOrson Zhai 1263c0e3abdSOrson Zhai CLUSTER_PD: cluster_pd { 1273c0e3abdSOrson Zhai compatible = "arm,idle-state"; 1283c0e3abdSOrson Zhai entry-latency-us = <1000>; 1293c0e3abdSOrson Zhai exit-latency-us = <1000>; 1303c0e3abdSOrson Zhai min-residency-us = <3000>; 1313c0e3abdSOrson Zhai local-timer-stop; 1323c0e3abdSOrson Zhai arm,psci-suspend-param = <0x01010003>; 1333c0e3abdSOrson Zhai }; 1343c0e3abdSOrson Zhai }; 1353c0e3abdSOrson Zhai 1363c0e3abdSOrson Zhai gic: interrupt-controller@12001000 { 1373c0e3abdSOrson Zhai compatible = "arm,gic-400"; 1383c0e3abdSOrson Zhai reg = <0 0x12001000 0 0x1000>, 1393c0e3abdSOrson Zhai <0 0x12002000 0 0x2000>, 1403c0e3abdSOrson Zhai <0 0x12004000 0 0x2000>, 1413c0e3abdSOrson Zhai <0 0x12006000 0 0x2000>; 1423c0e3abdSOrson Zhai #interrupt-cells = <3>; 1433c0e3abdSOrson Zhai interrupt-controller; 1443c0e3abdSOrson Zhai interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) 1453c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_HIGH)>; 1463c0e3abdSOrson Zhai }; 1473c0e3abdSOrson Zhai 1483c0e3abdSOrson Zhai psci { 1493c0e3abdSOrson Zhai compatible = "arm,psci-0.2"; 1503c0e3abdSOrson Zhai method = "smc"; 1513c0e3abdSOrson Zhai }; 1523c0e3abdSOrson Zhai 1533c0e3abdSOrson Zhai timer { 1543c0e3abdSOrson Zhai compatible = "arm,armv8-timer"; 1553c0e3abdSOrson Zhai interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) 1563c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1573c0e3abdSOrson Zhai <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) 1583c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1593c0e3abdSOrson Zhai <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) 1603c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1613c0e3abdSOrson Zhai <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) 1623c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>; 1633c0e3abdSOrson Zhai }; 1643c0e3abdSOrson Zhai 1653c0e3abdSOrson Zhai pmu { 1663c0e3abdSOrson Zhai compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 1673c0e3abdSOrson Zhai interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1683c0e3abdSOrson Zhai <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1693c0e3abdSOrson Zhai <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1703c0e3abdSOrson Zhai <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1713c0e3abdSOrson Zhai <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1723c0e3abdSOrson Zhai <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1733c0e3abdSOrson Zhai <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1743c0e3abdSOrson Zhai <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1753c0e3abdSOrson Zhai interrupt-affinity = <&CPU0>, 1763c0e3abdSOrson Zhai <&CPU1>, 1773c0e3abdSOrson Zhai <&CPU2>, 1783c0e3abdSOrson Zhai <&CPU3>, 1793c0e3abdSOrson Zhai <&CPU4>, 1803c0e3abdSOrson Zhai <&CPU5>, 1813c0e3abdSOrson Zhai <&CPU6>, 1823c0e3abdSOrson Zhai <&CPU7>; 1833c0e3abdSOrson Zhai }; 1843c0e3abdSOrson Zhai 1853c0e3abdSOrson Zhai soc { 1863c0e3abdSOrson Zhai funnel@10001000 { /* SoC Funnel */ 1873c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 1883c0e3abdSOrson Zhai reg = <0 0x10001000 0 0x1000>; 1893c0e3abdSOrson Zhai clocks = <&ext_26m>; 1903c0e3abdSOrson Zhai clock-names = "apb_pclk"; 1913c0e3abdSOrson Zhai ports { 1923c0e3abdSOrson Zhai #address-cells = <1>; 1933c0e3abdSOrson Zhai #size-cells = <0>; 1943c0e3abdSOrson Zhai 1953c0e3abdSOrson Zhai port@0 { 1963c0e3abdSOrson Zhai reg = <0>; 1973c0e3abdSOrson Zhai soc_funnel_out_port: endpoint { 1983c0e3abdSOrson Zhai remote-endpoint = <&etb_in>; 1993c0e3abdSOrson Zhai }; 2003c0e3abdSOrson Zhai }; 2013c0e3abdSOrson Zhai 2023c0e3abdSOrson Zhai port@1 { 2033c0e3abdSOrson Zhai reg = <0>; 2043c0e3abdSOrson Zhai soc_funnel_in_port0: endpoint { 2053c0e3abdSOrson Zhai slave-mode; 2063c0e3abdSOrson Zhai remote-endpoint = 2073c0e3abdSOrson Zhai <&main_funnel_out_port>; 2083c0e3abdSOrson Zhai }; 2093c0e3abdSOrson Zhai }; 2103c0e3abdSOrson Zhai 2113c0e3abdSOrson Zhai port@2 { 2123c0e3abdSOrson Zhai reg = <4>; 2133c0e3abdSOrson Zhai soc_funnel_in_port1: endpoint { 2143c0e3abdSOrson Zhai slave-mode; 2153c0e3abdSOrson Zhai remote-endpioint = 2163c0e3abdSOrson Zhai <&stm_out_port>; 2173c0e3abdSOrson Zhai }; 2183c0e3abdSOrson Zhai }; 2193c0e3abdSOrson Zhai }; 2203c0e3abdSOrson Zhai }; 2213c0e3abdSOrson Zhai 2223c0e3abdSOrson Zhai etb@10003000 { 2233c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 2243c0e3abdSOrson Zhai reg = <0 0x10003000 0 0x1000>; 2253c0e3abdSOrson Zhai clocks = <&ext_26m>; 2263c0e3abdSOrson Zhai clock-names = "apb_pclk"; 2273c0e3abdSOrson Zhai port { 2283c0e3abdSOrson Zhai etb_in: endpoint { 2293c0e3abdSOrson Zhai slave-mode; 2303c0e3abdSOrson Zhai remote-endpoint = 2313c0e3abdSOrson Zhai <&soc_funnel_out_port>; 2323c0e3abdSOrson Zhai }; 2333c0e3abdSOrson Zhai }; 2343c0e3abdSOrson Zhai }; 2353c0e3abdSOrson Zhai 2363c0e3abdSOrson Zhai stm@10006000 { 2373c0e3abdSOrson Zhai compatible = "arm,coresight-stm", "arm,primecell"; 2383c0e3abdSOrson Zhai reg = <0 0x10006000 0 0x1000>, 2393c0e3abdSOrson Zhai <0 0x01000000 0 0x180000>; 2403c0e3abdSOrson Zhai reg-names = "stm-base", "stm-stimulus-base"; 2413c0e3abdSOrson Zhai clocks = <&ext_26m>; 2423c0e3abdSOrson Zhai clock-names = "apb_pclk"; 2433c0e3abdSOrson Zhai port { 2443c0e3abdSOrson Zhai stm_out_port: endpoint { 2453c0e3abdSOrson Zhai remote-endpoint = 2463c0e3abdSOrson Zhai <&soc_funnel_in_port1>; 2473c0e3abdSOrson Zhai }; 2483c0e3abdSOrson Zhai }; 2493c0e3abdSOrson Zhai }; 2503c0e3abdSOrson Zhai 2513c0e3abdSOrson Zhai funnel@11001000 { /* Cluster0 Funnel */ 2523c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 2533c0e3abdSOrson Zhai reg = <0 0x11001000 0 0x1000>; 2543c0e3abdSOrson Zhai clocks = <&ext_26m>; 2553c0e3abdSOrson Zhai clock-names = "apb_pclk"; 2563c0e3abdSOrson Zhai ports { 2573c0e3abdSOrson Zhai #address-cells = <1>; 2583c0e3abdSOrson Zhai #size-cells = <0>; 2593c0e3abdSOrson Zhai 2603c0e3abdSOrson Zhai port@0 { 2613c0e3abdSOrson Zhai reg = <0>; 2623c0e3abdSOrson Zhai cluster0_funnel_out_port: endpoint { 2633c0e3abdSOrson Zhai remote-endpoint = 2643c0e3abdSOrson Zhai <&cluster0_etf_in>; 2653c0e3abdSOrson Zhai }; 2663c0e3abdSOrson Zhai }; 2673c0e3abdSOrson Zhai 2683c0e3abdSOrson Zhai port@1 { 2693c0e3abdSOrson Zhai reg = <0>; 2703c0e3abdSOrson Zhai cluster0_funnel_in_port0: endpoint { 2713c0e3abdSOrson Zhai slave-mode; 2723c0e3abdSOrson Zhai remote-endpoint = <&etm0_out>; 2733c0e3abdSOrson Zhai }; 2743c0e3abdSOrson Zhai }; 2753c0e3abdSOrson Zhai 2763c0e3abdSOrson Zhai port@2 { 2773c0e3abdSOrson Zhai reg = <1>; 2783c0e3abdSOrson Zhai cluster0_funnel_in_port1: endpoint { 2793c0e3abdSOrson Zhai slave-mode; 2803c0e3abdSOrson Zhai remote-endpoint = <&etm1_out>; 2813c0e3abdSOrson Zhai }; 2823c0e3abdSOrson Zhai }; 2833c0e3abdSOrson Zhai 2843c0e3abdSOrson Zhai port@3 { 2853c0e3abdSOrson Zhai reg = <2>; 2863c0e3abdSOrson Zhai cluster0_funnel_in_port2: endpoint { 2873c0e3abdSOrson Zhai slave-mode; 2883c0e3abdSOrson Zhai remote-endpoint = <&etm2_out>; 2893c0e3abdSOrson Zhai }; 2903c0e3abdSOrson Zhai }; 2913c0e3abdSOrson Zhai 2923c0e3abdSOrson Zhai port@4 { 2933c0e3abdSOrson Zhai reg = <4>; 2943c0e3abdSOrson Zhai cluster0_funnel_in_port3: endpoint { 2953c0e3abdSOrson Zhai slave-mode; 2963c0e3abdSOrson Zhai remote-endpoint = <&etm3_out>; 2973c0e3abdSOrson Zhai }; 2983c0e3abdSOrson Zhai }; 2993c0e3abdSOrson Zhai }; 3003c0e3abdSOrson Zhai }; 3013c0e3abdSOrson Zhai 3023c0e3abdSOrson Zhai funnel@11002000 { /* Cluster1 Funnel */ 3033c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 3043c0e3abdSOrson Zhai reg = <0 0x11002000 0 0x1000>; 3053c0e3abdSOrson Zhai clocks = <&ext_26m>; 3063c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3073c0e3abdSOrson Zhai ports { 3083c0e3abdSOrson Zhai #address-cells = <1>; 3093c0e3abdSOrson Zhai #size-cells = <0>; 3103c0e3abdSOrson Zhai 3113c0e3abdSOrson Zhai port@0 { 3123c0e3abdSOrson Zhai reg = <0>; 3133c0e3abdSOrson Zhai cluster1_funnel_out_port: endpoint { 3143c0e3abdSOrson Zhai remote-endpoint = 3153c0e3abdSOrson Zhai <&cluster1_etf_in>; 3163c0e3abdSOrson Zhai }; 3173c0e3abdSOrson Zhai }; 3183c0e3abdSOrson Zhai 3193c0e3abdSOrson Zhai port@1 { 3203c0e3abdSOrson Zhai reg = <0>; 3213c0e3abdSOrson Zhai cluster1_funnel_in_port0: endpoint { 3223c0e3abdSOrson Zhai slave-mode; 3233c0e3abdSOrson Zhai remote-endpoint = <&etm4_out>; 3243c0e3abdSOrson Zhai }; 3253c0e3abdSOrson Zhai }; 3263c0e3abdSOrson Zhai 3273c0e3abdSOrson Zhai port@2 { 3283c0e3abdSOrson Zhai reg = <1>; 3293c0e3abdSOrson Zhai cluster1_funnel_in_port1: endpoint { 3303c0e3abdSOrson Zhai slave-mode; 3313c0e3abdSOrson Zhai remote-endpoint = <&etm5_out>; 3323c0e3abdSOrson Zhai }; 3333c0e3abdSOrson Zhai }; 3343c0e3abdSOrson Zhai 3353c0e3abdSOrson Zhai port@3 { 3363c0e3abdSOrson Zhai reg = <2>; 3373c0e3abdSOrson Zhai cluster1_funnel_in_port2: endpoint { 3383c0e3abdSOrson Zhai slave-mode; 3393c0e3abdSOrson Zhai remote-endpoint = <&etm6_out>; 3403c0e3abdSOrson Zhai }; 3413c0e3abdSOrson Zhai }; 3423c0e3abdSOrson Zhai 3433c0e3abdSOrson Zhai port@4 { 3443c0e3abdSOrson Zhai reg = <3>; 3453c0e3abdSOrson Zhai cluster1_funnel_in_port3: endpoint { 3463c0e3abdSOrson Zhai slave-mode; 3473c0e3abdSOrson Zhai remote-endpoint = <&etm7_out>; 3483c0e3abdSOrson Zhai }; 3493c0e3abdSOrson Zhai }; 3503c0e3abdSOrson Zhai }; 3513c0e3abdSOrson Zhai }; 3523c0e3abdSOrson Zhai 3533c0e3abdSOrson Zhai etf@11003000 { /* ETF on Cluster0 */ 3543c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 3553c0e3abdSOrson Zhai reg = <0 0x11003000 0 0x1000>; 3563c0e3abdSOrson Zhai clocks = <&ext_26m>; 3573c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3583c0e3abdSOrson Zhai 3593c0e3abdSOrson Zhai ports { 3603c0e3abdSOrson Zhai #address-cells = <1>; 3613c0e3abdSOrson Zhai #size-cells = <0>; 3623c0e3abdSOrson Zhai 3633c0e3abdSOrson Zhai port@0 { 3643c0e3abdSOrson Zhai reg = <0>; 3653c0e3abdSOrson Zhai cluster0_etf_out: endpoint { 3663c0e3abdSOrson Zhai remote-endpoint = 3673c0e3abdSOrson Zhai <&main_funnel_in_port0>; 3683c0e3abdSOrson Zhai }; 3693c0e3abdSOrson Zhai }; 3703c0e3abdSOrson Zhai 3713c0e3abdSOrson Zhai port@1 { 3723c0e3abdSOrson Zhai reg = <0>; 3733c0e3abdSOrson Zhai cluster0_etf_in: endpoint { 3743c0e3abdSOrson Zhai slave-mode; 3753c0e3abdSOrson Zhai remote-endpoint = 3763c0e3abdSOrson Zhai <&cluster0_funnel_out_port>; 3773c0e3abdSOrson Zhai }; 3783c0e3abdSOrson Zhai }; 3793c0e3abdSOrson Zhai }; 3803c0e3abdSOrson Zhai }; 3813c0e3abdSOrson Zhai 3823c0e3abdSOrson Zhai etf@11004000 { /* ETF on Cluster1 */ 3833c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 3843c0e3abdSOrson Zhai reg = <0 0x11004000 0 0x1000>; 3853c0e3abdSOrson Zhai clocks = <&ext_26m>; 3863c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3873c0e3abdSOrson Zhai 3883c0e3abdSOrson Zhai ports { 3893c0e3abdSOrson Zhai #address-cells = <1>; 3903c0e3abdSOrson Zhai #size-cells = <0>; 3913c0e3abdSOrson Zhai 3923c0e3abdSOrson Zhai port@0 { 3933c0e3abdSOrson Zhai reg = <0>; 3943c0e3abdSOrson Zhai cluster1_etf_out: endpoint { 3953c0e3abdSOrson Zhai remote-endpoint = 3963c0e3abdSOrson Zhai <&main_funnel_in_port1>; 3973c0e3abdSOrson Zhai }; 3983c0e3abdSOrson Zhai }; 3993c0e3abdSOrson Zhai 4003c0e3abdSOrson Zhai port@1 { 4013c0e3abdSOrson Zhai reg = <0>; 4023c0e3abdSOrson Zhai cluster1_etf_in: endpoint { 4033c0e3abdSOrson Zhai slave-mode; 4043c0e3abdSOrson Zhai remote-endpoint = 4053c0e3abdSOrson Zhai <&cluster1_funnel_out_port>; 4063c0e3abdSOrson Zhai }; 4073c0e3abdSOrson Zhai }; 4083c0e3abdSOrson Zhai }; 4093c0e3abdSOrson Zhai }; 4103c0e3abdSOrson Zhai 4113c0e3abdSOrson Zhai funnel@11005000 { /* Main Funnel */ 4123c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 4133c0e3abdSOrson Zhai reg = <0 0x11005000 0 0x1000>; 4143c0e3abdSOrson Zhai clocks = <&ext_26m>; 4153c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4163c0e3abdSOrson Zhai 4173c0e3abdSOrson Zhai ports { 4183c0e3abdSOrson Zhai #address-cells = <1>; 4193c0e3abdSOrson Zhai #size-cells = <0>; 4203c0e3abdSOrson Zhai 4213c0e3abdSOrson Zhai port@0 { 4223c0e3abdSOrson Zhai reg = <0>; 4233c0e3abdSOrson Zhai main_funnel_out_port: endpoint { 4243c0e3abdSOrson Zhai remote-endpoint = 4253c0e3abdSOrson Zhai <&soc_funnel_in_port0>; 4263c0e3abdSOrson Zhai }; 4273c0e3abdSOrson Zhai }; 4283c0e3abdSOrson Zhai 4293c0e3abdSOrson Zhai port@1 { 4303c0e3abdSOrson Zhai reg = <0>; 4313c0e3abdSOrson Zhai main_funnel_in_port0: endpoint { 4323c0e3abdSOrson Zhai slave-mode; 4333c0e3abdSOrson Zhai remote-endpoint = 4343c0e3abdSOrson Zhai <&cluster0_etf_out>; 4353c0e3abdSOrson Zhai }; 4363c0e3abdSOrson Zhai }; 4373c0e3abdSOrson Zhai 4383c0e3abdSOrson Zhai port@2 { 4393c0e3abdSOrson Zhai reg = <1>; 4403c0e3abdSOrson Zhai main_funnel_in_port1: endpoint { 4413c0e3abdSOrson Zhai slave-mode; 4423c0e3abdSOrson Zhai remote-endpoint = 4433c0e3abdSOrson Zhai <&cluster1_etf_out>; 4443c0e3abdSOrson Zhai }; 4453c0e3abdSOrson Zhai }; 4463c0e3abdSOrson Zhai }; 4473c0e3abdSOrson Zhai }; 4483c0e3abdSOrson Zhai 4493c0e3abdSOrson Zhai etm@11440000 { 4503c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 4513c0e3abdSOrson Zhai reg = <0 0x11440000 0 0x1000>; 4523c0e3abdSOrson Zhai cpu = <&CPU0>; 4533c0e3abdSOrson Zhai clocks = <&ext_26m>; 4543c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4553c0e3abdSOrson Zhai 4563c0e3abdSOrson Zhai port { 4573c0e3abdSOrson Zhai etm0_out: endpoint { 4583c0e3abdSOrson Zhai remote-endpoint = 4593c0e3abdSOrson Zhai <&cluster0_funnel_in_port0>; 4603c0e3abdSOrson Zhai }; 4613c0e3abdSOrson Zhai }; 4623c0e3abdSOrson Zhai }; 4633c0e3abdSOrson Zhai 4643c0e3abdSOrson Zhai etm@11540000 { 4653c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 4663c0e3abdSOrson Zhai reg = <0 0x11540000 0 0x1000>; 4673c0e3abdSOrson Zhai cpu = <&CPU1>; 4683c0e3abdSOrson Zhai clocks = <&ext_26m>; 4693c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4703c0e3abdSOrson Zhai 4713c0e3abdSOrson Zhai port { 4723c0e3abdSOrson Zhai etm1_out: endpoint { 4733c0e3abdSOrson Zhai remote-endpoint = 4743c0e3abdSOrson Zhai <&cluster0_funnel_in_port1>; 4753c0e3abdSOrson Zhai }; 4763c0e3abdSOrson Zhai }; 4773c0e3abdSOrson Zhai }; 4783c0e3abdSOrson Zhai 4793c0e3abdSOrson Zhai etm@11640000 { 4803c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 4813c0e3abdSOrson Zhai reg = <0 0x11640000 0 0x1000>; 4823c0e3abdSOrson Zhai cpu = <&CPU2>; 4833c0e3abdSOrson Zhai clocks = <&ext_26m>; 4843c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4853c0e3abdSOrson Zhai 4863c0e3abdSOrson Zhai port { 4873c0e3abdSOrson Zhai etm2_out: endpoint { 4883c0e3abdSOrson Zhai remote-endpoint = 4893c0e3abdSOrson Zhai <&cluster0_funnel_in_port2>; 4903c0e3abdSOrson Zhai }; 4913c0e3abdSOrson Zhai }; 4923c0e3abdSOrson Zhai }; 4933c0e3abdSOrson Zhai 4943c0e3abdSOrson Zhai etm@11740000 { 4953c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 4963c0e3abdSOrson Zhai reg = <0 0x11740000 0 0x1000>; 4973c0e3abdSOrson Zhai cpu = <&CPU3>; 4983c0e3abdSOrson Zhai clocks = <&ext_26m>; 4993c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5003c0e3abdSOrson Zhai 5013c0e3abdSOrson Zhai port { 5023c0e3abdSOrson Zhai etm3_out: endpoint { 5033c0e3abdSOrson Zhai remote-endpoint = 5043c0e3abdSOrson Zhai <&cluster0_funnel_in_port3>; 5053c0e3abdSOrson Zhai }; 5063c0e3abdSOrson Zhai }; 5073c0e3abdSOrson Zhai }; 5083c0e3abdSOrson Zhai 5093c0e3abdSOrson Zhai etm@11840000 { 5103c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5113c0e3abdSOrson Zhai reg = <0 0x11840000 0 0x1000>; 5123c0e3abdSOrson Zhai cpu = <&CPU4>; 5133c0e3abdSOrson Zhai clocks = <&ext_26m>; 5143c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5153c0e3abdSOrson Zhai 5163c0e3abdSOrson Zhai port { 5173c0e3abdSOrson Zhai etm4_out: endpoint { 5183c0e3abdSOrson Zhai remote-endpoint = 5193c0e3abdSOrson Zhai <&cluster1_funnel_in_port0>; 5203c0e3abdSOrson Zhai }; 5213c0e3abdSOrson Zhai }; 5223c0e3abdSOrson Zhai }; 5233c0e3abdSOrson Zhai 5243c0e3abdSOrson Zhai etm@11940000 { 5253c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5263c0e3abdSOrson Zhai reg = <0 0x11940000 0 0x1000>; 5273c0e3abdSOrson Zhai cpu = <&CPU5>; 5283c0e3abdSOrson Zhai clocks = <&ext_26m>; 5293c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5303c0e3abdSOrson Zhai 5313c0e3abdSOrson Zhai port { 5323c0e3abdSOrson Zhai etm5_out: endpoint { 5333c0e3abdSOrson Zhai remote-endpoint = 5343c0e3abdSOrson Zhai <&cluster1_funnel_in_port1>; 5353c0e3abdSOrson Zhai }; 5363c0e3abdSOrson Zhai }; 5373c0e3abdSOrson Zhai }; 5383c0e3abdSOrson Zhai 5393c0e3abdSOrson Zhai etm@11a40000 { 5403c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5413c0e3abdSOrson Zhai reg = <0 0x11a40000 0 0x1000>; 5423c0e3abdSOrson Zhai cpu = <&CPU6>; 5433c0e3abdSOrson Zhai clocks = <&ext_26m>; 5443c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5453c0e3abdSOrson Zhai 5463c0e3abdSOrson Zhai port { 5473c0e3abdSOrson Zhai etm6_out: endpoint { 5483c0e3abdSOrson Zhai remote-endpoint = 5493c0e3abdSOrson Zhai <&cluster1_funnel_in_port2>; 5503c0e3abdSOrson Zhai }; 5513c0e3abdSOrson Zhai }; 5523c0e3abdSOrson Zhai }; 5533c0e3abdSOrson Zhai 5543c0e3abdSOrson Zhai etm@11b40000 { 5553c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5563c0e3abdSOrson Zhai reg = <0 0x11b40000 0 0x1000>; 5573c0e3abdSOrson Zhai cpu = <&CPU7>; 5583c0e3abdSOrson Zhai clocks = <&ext_26m>; 5593c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5603c0e3abdSOrson Zhai 5613c0e3abdSOrson Zhai port { 5623c0e3abdSOrson Zhai etm7_out: endpoint { 5633c0e3abdSOrson Zhai remote-endpoint = 5643c0e3abdSOrson Zhai <&cluster1_funnel_in_port3>; 5653c0e3abdSOrson Zhai }; 5663c0e3abdSOrson Zhai }; 5673c0e3abdSOrson Zhai }; 5683c0e3abdSOrson Zhai }; 5693c0e3abdSOrson Zhai}; 570