13c0e3abdSOrson Zhai/* 23c0e3abdSOrson Zhai * Spreadtrum SC9860 SoC 33c0e3abdSOrson Zhai * 43c0e3abdSOrson Zhai * Copyright (C) 2016, Spreadtrum Communications Inc. 53c0e3abdSOrson Zhai * 63c0e3abdSOrson Zhai * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 73c0e3abdSOrson Zhai */ 83c0e3abdSOrson Zhai 93c0e3abdSOrson Zhai#include <dt-bindings/interrupt-controller/arm-gic.h> 1022f37a24SChunyan Zhang#include <dt-bindings/clock/sprd,sc9860-clk.h> 113c0e3abdSOrson Zhai#include "whale2.dtsi" 123c0e3abdSOrson Zhai 133c0e3abdSOrson Zhai/ { 143c0e3abdSOrson Zhai cpus { 153c0e3abdSOrson Zhai #address-cells = <2>; 163c0e3abdSOrson Zhai #size-cells = <0>; 173c0e3abdSOrson Zhai 183c0e3abdSOrson Zhai cpu-map { 193c0e3abdSOrson Zhai cluster0 { 203c0e3abdSOrson Zhai core0 { 213c0e3abdSOrson Zhai cpu = <&CPU0>; 223c0e3abdSOrson Zhai }; 233c0e3abdSOrson Zhai core1 { 243c0e3abdSOrson Zhai cpu = <&CPU1>; 253c0e3abdSOrson Zhai }; 263c0e3abdSOrson Zhai core2 { 273c0e3abdSOrson Zhai cpu = <&CPU2>; 283c0e3abdSOrson Zhai }; 293c0e3abdSOrson Zhai core3 { 303c0e3abdSOrson Zhai cpu = <&CPU3>; 313c0e3abdSOrson Zhai }; 323c0e3abdSOrson Zhai }; 333c0e3abdSOrson Zhai 343c0e3abdSOrson Zhai cluster1 { 353c0e3abdSOrson Zhai core0 { 363c0e3abdSOrson Zhai cpu = <&CPU4>; 373c0e3abdSOrson Zhai }; 383c0e3abdSOrson Zhai core1 { 393c0e3abdSOrson Zhai cpu = <&CPU5>; 403c0e3abdSOrson Zhai }; 413c0e3abdSOrson Zhai core2 { 423c0e3abdSOrson Zhai cpu = <&CPU6>; 433c0e3abdSOrson Zhai }; 443c0e3abdSOrson Zhai core3 { 453c0e3abdSOrson Zhai cpu = <&CPU7>; 463c0e3abdSOrson Zhai }; 473c0e3abdSOrson Zhai }; 483c0e3abdSOrson Zhai }; 493c0e3abdSOrson Zhai 503c0e3abdSOrson Zhai CPU0: cpu@530000 { 513c0e3abdSOrson Zhai device_type = "cpu"; 523c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 533c0e3abdSOrson Zhai reg = <0x0 0x530000>; 543c0e3abdSOrson Zhai enable-method = "psci"; 553c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 563c0e3abdSOrson Zhai }; 573c0e3abdSOrson Zhai 583c0e3abdSOrson Zhai CPU1: cpu@530001 { 593c0e3abdSOrson Zhai device_type = "cpu"; 603c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 613c0e3abdSOrson Zhai reg = <0x0 0x530001>; 623c0e3abdSOrson Zhai enable-method = "psci"; 633c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 643c0e3abdSOrson Zhai }; 653c0e3abdSOrson Zhai 663c0e3abdSOrson Zhai CPU2: cpu@530002 { 673c0e3abdSOrson Zhai device_type = "cpu"; 683c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 693c0e3abdSOrson Zhai reg = <0x0 0x530002>; 703c0e3abdSOrson Zhai enable-method = "psci"; 713c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 723c0e3abdSOrson Zhai }; 733c0e3abdSOrson Zhai 743c0e3abdSOrson Zhai CPU3: cpu@530003 { 753c0e3abdSOrson Zhai device_type = "cpu"; 763c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 773c0e3abdSOrson Zhai reg = <0x0 0x530003>; 783c0e3abdSOrson Zhai enable-method = "psci"; 793c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 803c0e3abdSOrson Zhai }; 813c0e3abdSOrson Zhai 823c0e3abdSOrson Zhai CPU4: cpu@530100 { 833c0e3abdSOrson Zhai device_type = "cpu"; 843c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 853c0e3abdSOrson Zhai reg = <0x0 0x530100>; 863c0e3abdSOrson Zhai enable-method = "psci"; 873c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 883c0e3abdSOrson Zhai }; 893c0e3abdSOrson Zhai 903c0e3abdSOrson Zhai CPU5: cpu@530101 { 913c0e3abdSOrson Zhai device_type = "cpu"; 923c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 933c0e3abdSOrson Zhai reg = <0x0 0x530101>; 943c0e3abdSOrson Zhai enable-method = "psci"; 953c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 963c0e3abdSOrson Zhai }; 973c0e3abdSOrson Zhai 983c0e3abdSOrson Zhai CPU6: cpu@530102 { 993c0e3abdSOrson Zhai device_type = "cpu"; 1003c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 1013c0e3abdSOrson Zhai reg = <0x0 0x530102>; 1023c0e3abdSOrson Zhai enable-method = "psci"; 1033c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 1043c0e3abdSOrson Zhai }; 1053c0e3abdSOrson Zhai 1063c0e3abdSOrson Zhai CPU7: cpu@530103 { 1073c0e3abdSOrson Zhai device_type = "cpu"; 1083c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 1093c0e3abdSOrson Zhai reg = <0x0 0x530103>; 1103c0e3abdSOrson Zhai enable-method = "psci"; 1113c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 1123c0e3abdSOrson Zhai }; 1133c0e3abdSOrson Zhai }; 1143c0e3abdSOrson Zhai 1153c0e3abdSOrson Zhai idle-states{ 1163c0e3abdSOrson Zhai entry-method = "arm,psci"; 1173c0e3abdSOrson Zhai 1183c0e3abdSOrson Zhai CORE_PD: core_pd { 1193c0e3abdSOrson Zhai compatible = "arm,idle-state"; 1203c0e3abdSOrson Zhai entry-latency-us = <1000>; 1213c0e3abdSOrson Zhai exit-latency-us = <700>; 1223c0e3abdSOrson Zhai min-residency-us = <2500>; 1233c0e3abdSOrson Zhai local-timer-stop; 1243c0e3abdSOrson Zhai arm,psci-suspend-param = <0x00010002>; 1253c0e3abdSOrson Zhai }; 1263c0e3abdSOrson Zhai 1273c0e3abdSOrson Zhai CLUSTER_PD: cluster_pd { 1283c0e3abdSOrson Zhai compatible = "arm,idle-state"; 1293c0e3abdSOrson Zhai entry-latency-us = <1000>; 1303c0e3abdSOrson Zhai exit-latency-us = <1000>; 1313c0e3abdSOrson Zhai min-residency-us = <3000>; 1323c0e3abdSOrson Zhai local-timer-stop; 1333c0e3abdSOrson Zhai arm,psci-suspend-param = <0x01010003>; 1343c0e3abdSOrson Zhai }; 1353c0e3abdSOrson Zhai }; 1363c0e3abdSOrson Zhai 1373c0e3abdSOrson Zhai gic: interrupt-controller@12001000 { 1383c0e3abdSOrson Zhai compatible = "arm,gic-400"; 1393c0e3abdSOrson Zhai reg = <0 0x12001000 0 0x1000>, 1403c0e3abdSOrson Zhai <0 0x12002000 0 0x2000>, 1413c0e3abdSOrson Zhai <0 0x12004000 0 0x2000>, 1423c0e3abdSOrson Zhai <0 0x12006000 0 0x2000>; 1433c0e3abdSOrson Zhai #interrupt-cells = <3>; 1443c0e3abdSOrson Zhai interrupt-controller; 1453c0e3abdSOrson Zhai interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) 1463c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_HIGH)>; 1473c0e3abdSOrson Zhai }; 1483c0e3abdSOrson Zhai 1493c0e3abdSOrson Zhai psci { 1503c0e3abdSOrson Zhai compatible = "arm,psci-0.2"; 1513c0e3abdSOrson Zhai method = "smc"; 1523c0e3abdSOrson Zhai }; 1533c0e3abdSOrson Zhai 1543c0e3abdSOrson Zhai timer { 1553c0e3abdSOrson Zhai compatible = "arm,armv8-timer"; 1563c0e3abdSOrson Zhai interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) 1573c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1583c0e3abdSOrson Zhai <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) 1593c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1603c0e3abdSOrson Zhai <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) 1613c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1623c0e3abdSOrson Zhai <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) 1633c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>; 1643c0e3abdSOrson Zhai }; 1653c0e3abdSOrson Zhai 1663c0e3abdSOrson Zhai pmu { 1673c0e3abdSOrson Zhai compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 1683c0e3abdSOrson Zhai interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1693c0e3abdSOrson Zhai <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1703c0e3abdSOrson Zhai <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1713c0e3abdSOrson Zhai <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1723c0e3abdSOrson Zhai <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1733c0e3abdSOrson Zhai <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1743c0e3abdSOrson Zhai <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1753c0e3abdSOrson Zhai <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1763c0e3abdSOrson Zhai interrupt-affinity = <&CPU0>, 1773c0e3abdSOrson Zhai <&CPU1>, 1783c0e3abdSOrson Zhai <&CPU2>, 1793c0e3abdSOrson Zhai <&CPU3>, 1803c0e3abdSOrson Zhai <&CPU4>, 1813c0e3abdSOrson Zhai <&CPU5>, 1823c0e3abdSOrson Zhai <&CPU6>, 1833c0e3abdSOrson Zhai <&CPU7>; 1843c0e3abdSOrson Zhai }; 1853c0e3abdSOrson Zhai 1863c0e3abdSOrson Zhai soc { 18722f37a24SChunyan Zhang pmu_gate: pmu-gate { 18822f37a24SChunyan Zhang compatible = "sprd,sc9860-pmu-gate"; 18922f37a24SChunyan Zhang sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ 19022f37a24SChunyan Zhang clocks = <&ext_26m>; 19122f37a24SChunyan Zhang #clock-cells = <1>; 19222f37a24SChunyan Zhang }; 19322f37a24SChunyan Zhang 19422f37a24SChunyan Zhang pll: pll { 19522f37a24SChunyan Zhang compatible = "sprd,sc9860-pll"; 19622f37a24SChunyan Zhang sprd,syscon = <&ana_regs>; /* 0x40400000 */ 19722f37a24SChunyan Zhang clocks = <&pmu_gate 0>; 19822f37a24SChunyan Zhang #clock-cells = <1>; 19922f37a24SChunyan Zhang }; 20022f37a24SChunyan Zhang 20122f37a24SChunyan Zhang ap_clk: clock-controller@20000000 { 20222f37a24SChunyan Zhang compatible = "sprd,sc9860-ap-clk"; 20322f37a24SChunyan Zhang reg = <0 0x20000000 0 0x400>; 20422f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>, 20522f37a24SChunyan Zhang <&pmu_gate 0>; 20622f37a24SChunyan Zhang #clock-cells = <1>; 20722f37a24SChunyan Zhang }; 20822f37a24SChunyan Zhang 20922f37a24SChunyan Zhang aon_prediv: aon-prediv { 21022f37a24SChunyan Zhang compatible = "sprd,sc9860-aon-prediv"; 21122f37a24SChunyan Zhang reg = <0 0x402d0000 0 0x400>; 21222f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>, 21322f37a24SChunyan Zhang <&pmu_gate 0>; 21422f37a24SChunyan Zhang #clock-cells = <1>; 21522f37a24SChunyan Zhang }; 21622f37a24SChunyan Zhang 21722f37a24SChunyan Zhang apahb_gate: apahb-gate { 21822f37a24SChunyan Zhang compatible = "sprd,sc9860-apahb-gate"; 21922f37a24SChunyan Zhang sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ 22022f37a24SChunyan Zhang clocks = <&aon_prediv 0>; 22122f37a24SChunyan Zhang #clock-cells = <1>; 22222f37a24SChunyan Zhang }; 22322f37a24SChunyan Zhang 22422f37a24SChunyan Zhang aon_gate: aon-gate { 22522f37a24SChunyan Zhang compatible = "sprd,sc9860-aon-gate"; 22622f37a24SChunyan Zhang sprd,syscon = <&aon_regs>; /* 0x402e0000 */ 22722f37a24SChunyan Zhang clocks = <&aon_prediv 0>; 22822f37a24SChunyan Zhang #clock-cells = <1>; 22922f37a24SChunyan Zhang }; 23022f37a24SChunyan Zhang 23122f37a24SChunyan Zhang aonsecure_clk: clock-controller@40880000 { 23222f37a24SChunyan Zhang compatible = "sprd,sc9860-aonsecure-clk"; 23322f37a24SChunyan Zhang reg = <0 0x40880000 0 0x400>; 23422f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>; 23522f37a24SChunyan Zhang #clock-cells = <1>; 23622f37a24SChunyan Zhang }; 23722f37a24SChunyan Zhang 23822f37a24SChunyan Zhang agcp_gate: agcp-gate { 23922f37a24SChunyan Zhang compatible = "sprd,sc9860-agcp-gate"; 24022f37a24SChunyan Zhang sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ 24122f37a24SChunyan Zhang clocks = <&aon_prediv 0>; 24222f37a24SChunyan Zhang #clock-cells = <1>; 24322f37a24SChunyan Zhang }; 24422f37a24SChunyan Zhang 24522f37a24SChunyan Zhang gpu_clk: clock-controller@60200000 { 24622f37a24SChunyan Zhang compatible = "sprd,sc9860-gpu-clk"; 24722f37a24SChunyan Zhang reg = <0 0x60200000 0 0x400>; 24822f37a24SChunyan Zhang clocks = <&pll 0>; 24922f37a24SChunyan Zhang #clock-cells = <1>; 25022f37a24SChunyan Zhang }; 25122f37a24SChunyan Zhang 25222f37a24SChunyan Zhang vsp_clk: clock-controller@61000000 { 25322f37a24SChunyan Zhang compatible = "sprd,sc9860-vsp-clk"; 25422f37a24SChunyan Zhang reg = <0 0x61000000 0 0x400>; 25522f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>; 25622f37a24SChunyan Zhang #clock-cells = <1>; 25722f37a24SChunyan Zhang }; 25822f37a24SChunyan Zhang 25922f37a24SChunyan Zhang vsp_gate: vsp-gate { 26022f37a24SChunyan Zhang compatible = "sprd,sc9860-vsp-gate"; 26122f37a24SChunyan Zhang sprd,syscon = <&vsp_regs>; /* 0x61100000 */ 26222f37a24SChunyan Zhang clocks = <&vsp_clk 0>; 26322f37a24SChunyan Zhang #clock-cells = <1>; 26422f37a24SChunyan Zhang }; 26522f37a24SChunyan Zhang 26622f37a24SChunyan Zhang cam_clk: clock-controller@62000000 { 26722f37a24SChunyan Zhang compatible = "sprd,sc9860-cam-clk"; 26822f37a24SChunyan Zhang reg = <0 0x62000000 0 0x4000>; 26922f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>; 27022f37a24SChunyan Zhang #clock-cells = <1>; 27122f37a24SChunyan Zhang }; 27222f37a24SChunyan Zhang 27322f37a24SChunyan Zhang cam_gate: cam-gate { 27422f37a24SChunyan Zhang compatible = "sprd,sc9860-cam-gate"; 27522f37a24SChunyan Zhang sprd,syscon = <&cam_regs>; /* 0x62100000 */ 27622f37a24SChunyan Zhang clocks = <&cam_clk 0>; 27722f37a24SChunyan Zhang #clock-cells = <1>; 27822f37a24SChunyan Zhang }; 27922f37a24SChunyan Zhang 28022f37a24SChunyan Zhang disp_clk: clock-controller@63000000 { 28122f37a24SChunyan Zhang compatible = "sprd,sc9860-disp-clk"; 28222f37a24SChunyan Zhang reg = <0 0x63000000 0 0x400>; 28322f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>; 28422f37a24SChunyan Zhang #clock-cells = <1>; 28522f37a24SChunyan Zhang }; 28622f37a24SChunyan Zhang 28722f37a24SChunyan Zhang disp_gate: disp-gate { 28822f37a24SChunyan Zhang compatible = "sprd,sc9860-disp-gate"; 28922f37a24SChunyan Zhang sprd,syscon = <&disp_regs>; /* 0x63100000 */ 29022f37a24SChunyan Zhang clocks = <&disp_clk 0>; 29122f37a24SChunyan Zhang #clock-cells = <1>; 29222f37a24SChunyan Zhang }; 29322f37a24SChunyan Zhang 29422f37a24SChunyan Zhang apapb_gate: apapb-gate { 29522f37a24SChunyan Zhang compatible = "sprd,sc9860-apapb-gate"; 29622f37a24SChunyan Zhang sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ 29722f37a24SChunyan Zhang clocks = <&ap_clk 0>; 29822f37a24SChunyan Zhang #clock-cells = <1>; 29922f37a24SChunyan Zhang }; 30022f37a24SChunyan Zhang 3013c0e3abdSOrson Zhai funnel@10001000 { /* SoC Funnel */ 3023c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 3033c0e3abdSOrson Zhai reg = <0 0x10001000 0 0x1000>; 3043c0e3abdSOrson Zhai clocks = <&ext_26m>; 3053c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3063c0e3abdSOrson Zhai ports { 3073c0e3abdSOrson Zhai #address-cells = <1>; 3083c0e3abdSOrson Zhai #size-cells = <0>; 3093c0e3abdSOrson Zhai 3103c0e3abdSOrson Zhai port@0 { 3113c0e3abdSOrson Zhai reg = <0>; 3123c0e3abdSOrson Zhai soc_funnel_out_port: endpoint { 3133c0e3abdSOrson Zhai remote-endpoint = <&etb_in>; 3143c0e3abdSOrson Zhai }; 3153c0e3abdSOrson Zhai }; 3163c0e3abdSOrson Zhai 3173c0e3abdSOrson Zhai port@1 { 3183c0e3abdSOrson Zhai reg = <0>; 3193c0e3abdSOrson Zhai soc_funnel_in_port0: endpoint { 3203c0e3abdSOrson Zhai slave-mode; 3213c0e3abdSOrson Zhai remote-endpoint = 3223c0e3abdSOrson Zhai <&main_funnel_out_port>; 3233c0e3abdSOrson Zhai }; 3243c0e3abdSOrson Zhai }; 3253c0e3abdSOrson Zhai 3263c0e3abdSOrson Zhai port@2 { 3273c0e3abdSOrson Zhai reg = <4>; 3283c0e3abdSOrson Zhai soc_funnel_in_port1: endpoint { 3293c0e3abdSOrson Zhai slave-mode; 3303c0e3abdSOrson Zhai remote-endpioint = 3313c0e3abdSOrson Zhai <&stm_out_port>; 3323c0e3abdSOrson Zhai }; 3333c0e3abdSOrson Zhai }; 3343c0e3abdSOrson Zhai }; 3353c0e3abdSOrson Zhai }; 3363c0e3abdSOrson Zhai 3373c0e3abdSOrson Zhai etb@10003000 { 3383c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 3393c0e3abdSOrson Zhai reg = <0 0x10003000 0 0x1000>; 3403c0e3abdSOrson Zhai clocks = <&ext_26m>; 3413c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3423c0e3abdSOrson Zhai port { 3433c0e3abdSOrson Zhai etb_in: endpoint { 3443c0e3abdSOrson Zhai slave-mode; 3453c0e3abdSOrson Zhai remote-endpoint = 3463c0e3abdSOrson Zhai <&soc_funnel_out_port>; 3473c0e3abdSOrson Zhai }; 3483c0e3abdSOrson Zhai }; 3493c0e3abdSOrson Zhai }; 3503c0e3abdSOrson Zhai 3513c0e3abdSOrson Zhai stm@10006000 { 3523c0e3abdSOrson Zhai compatible = "arm,coresight-stm", "arm,primecell"; 3533c0e3abdSOrson Zhai reg = <0 0x10006000 0 0x1000>, 3543c0e3abdSOrson Zhai <0 0x01000000 0 0x180000>; 3553c0e3abdSOrson Zhai reg-names = "stm-base", "stm-stimulus-base"; 3563c0e3abdSOrson Zhai clocks = <&ext_26m>; 3573c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3583c0e3abdSOrson Zhai port { 3593c0e3abdSOrson Zhai stm_out_port: endpoint { 3603c0e3abdSOrson Zhai remote-endpoint = 3613c0e3abdSOrson Zhai <&soc_funnel_in_port1>; 3623c0e3abdSOrson Zhai }; 3633c0e3abdSOrson Zhai }; 3643c0e3abdSOrson Zhai }; 3653c0e3abdSOrson Zhai 3663c0e3abdSOrson Zhai funnel@11001000 { /* Cluster0 Funnel */ 3673c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 3683c0e3abdSOrson Zhai reg = <0 0x11001000 0 0x1000>; 3693c0e3abdSOrson Zhai clocks = <&ext_26m>; 3703c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3713c0e3abdSOrson Zhai ports { 3723c0e3abdSOrson Zhai #address-cells = <1>; 3733c0e3abdSOrson Zhai #size-cells = <0>; 3743c0e3abdSOrson Zhai 3753c0e3abdSOrson Zhai port@0 { 3763c0e3abdSOrson Zhai reg = <0>; 3773c0e3abdSOrson Zhai cluster0_funnel_out_port: endpoint { 3783c0e3abdSOrson Zhai remote-endpoint = 3793c0e3abdSOrson Zhai <&cluster0_etf_in>; 3803c0e3abdSOrson Zhai }; 3813c0e3abdSOrson Zhai }; 3823c0e3abdSOrson Zhai 3833c0e3abdSOrson Zhai port@1 { 3843c0e3abdSOrson Zhai reg = <0>; 3853c0e3abdSOrson Zhai cluster0_funnel_in_port0: endpoint { 3863c0e3abdSOrson Zhai slave-mode; 3873c0e3abdSOrson Zhai remote-endpoint = <&etm0_out>; 3883c0e3abdSOrson Zhai }; 3893c0e3abdSOrson Zhai }; 3903c0e3abdSOrson Zhai 3913c0e3abdSOrson Zhai port@2 { 3923c0e3abdSOrson Zhai reg = <1>; 3933c0e3abdSOrson Zhai cluster0_funnel_in_port1: endpoint { 3943c0e3abdSOrson Zhai slave-mode; 3953c0e3abdSOrson Zhai remote-endpoint = <&etm1_out>; 3963c0e3abdSOrson Zhai }; 3973c0e3abdSOrson Zhai }; 3983c0e3abdSOrson Zhai 3993c0e3abdSOrson Zhai port@3 { 4003c0e3abdSOrson Zhai reg = <2>; 4013c0e3abdSOrson Zhai cluster0_funnel_in_port2: endpoint { 4023c0e3abdSOrson Zhai slave-mode; 4033c0e3abdSOrson Zhai remote-endpoint = <&etm2_out>; 4043c0e3abdSOrson Zhai }; 4053c0e3abdSOrson Zhai }; 4063c0e3abdSOrson Zhai 4073c0e3abdSOrson Zhai port@4 { 4083c0e3abdSOrson Zhai reg = <4>; 4093c0e3abdSOrson Zhai cluster0_funnel_in_port3: endpoint { 4103c0e3abdSOrson Zhai slave-mode; 4113c0e3abdSOrson Zhai remote-endpoint = <&etm3_out>; 4123c0e3abdSOrson Zhai }; 4133c0e3abdSOrson Zhai }; 4143c0e3abdSOrson Zhai }; 4153c0e3abdSOrson Zhai }; 4163c0e3abdSOrson Zhai 4173c0e3abdSOrson Zhai funnel@11002000 { /* Cluster1 Funnel */ 4183c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 4193c0e3abdSOrson Zhai reg = <0 0x11002000 0 0x1000>; 4203c0e3abdSOrson Zhai clocks = <&ext_26m>; 4213c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4223c0e3abdSOrson Zhai ports { 4233c0e3abdSOrson Zhai #address-cells = <1>; 4243c0e3abdSOrson Zhai #size-cells = <0>; 4253c0e3abdSOrson Zhai 4263c0e3abdSOrson Zhai port@0 { 4273c0e3abdSOrson Zhai reg = <0>; 4283c0e3abdSOrson Zhai cluster1_funnel_out_port: endpoint { 4293c0e3abdSOrson Zhai remote-endpoint = 4303c0e3abdSOrson Zhai <&cluster1_etf_in>; 4313c0e3abdSOrson Zhai }; 4323c0e3abdSOrson Zhai }; 4333c0e3abdSOrson Zhai 4343c0e3abdSOrson Zhai port@1 { 4353c0e3abdSOrson Zhai reg = <0>; 4363c0e3abdSOrson Zhai cluster1_funnel_in_port0: endpoint { 4373c0e3abdSOrson Zhai slave-mode; 4383c0e3abdSOrson Zhai remote-endpoint = <&etm4_out>; 4393c0e3abdSOrson Zhai }; 4403c0e3abdSOrson Zhai }; 4413c0e3abdSOrson Zhai 4423c0e3abdSOrson Zhai port@2 { 4433c0e3abdSOrson Zhai reg = <1>; 4443c0e3abdSOrson Zhai cluster1_funnel_in_port1: endpoint { 4453c0e3abdSOrson Zhai slave-mode; 4463c0e3abdSOrson Zhai remote-endpoint = <&etm5_out>; 4473c0e3abdSOrson Zhai }; 4483c0e3abdSOrson Zhai }; 4493c0e3abdSOrson Zhai 4503c0e3abdSOrson Zhai port@3 { 4513c0e3abdSOrson Zhai reg = <2>; 4523c0e3abdSOrson Zhai cluster1_funnel_in_port2: endpoint { 4533c0e3abdSOrson Zhai slave-mode; 4543c0e3abdSOrson Zhai remote-endpoint = <&etm6_out>; 4553c0e3abdSOrson Zhai }; 4563c0e3abdSOrson Zhai }; 4573c0e3abdSOrson Zhai 4583c0e3abdSOrson Zhai port@4 { 4593c0e3abdSOrson Zhai reg = <3>; 4603c0e3abdSOrson Zhai cluster1_funnel_in_port3: endpoint { 4613c0e3abdSOrson Zhai slave-mode; 4623c0e3abdSOrson Zhai remote-endpoint = <&etm7_out>; 4633c0e3abdSOrson Zhai }; 4643c0e3abdSOrson Zhai }; 4653c0e3abdSOrson Zhai }; 4663c0e3abdSOrson Zhai }; 4673c0e3abdSOrson Zhai 4683c0e3abdSOrson Zhai etf@11003000 { /* ETF on Cluster0 */ 4693c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 4703c0e3abdSOrson Zhai reg = <0 0x11003000 0 0x1000>; 4713c0e3abdSOrson Zhai clocks = <&ext_26m>; 4723c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4733c0e3abdSOrson Zhai 4743c0e3abdSOrson Zhai ports { 4753c0e3abdSOrson Zhai #address-cells = <1>; 4763c0e3abdSOrson Zhai #size-cells = <0>; 4773c0e3abdSOrson Zhai 4783c0e3abdSOrson Zhai port@0 { 4793c0e3abdSOrson Zhai reg = <0>; 4803c0e3abdSOrson Zhai cluster0_etf_out: endpoint { 4813c0e3abdSOrson Zhai remote-endpoint = 4823c0e3abdSOrson Zhai <&main_funnel_in_port0>; 4833c0e3abdSOrson Zhai }; 4843c0e3abdSOrson Zhai }; 4853c0e3abdSOrson Zhai 4863c0e3abdSOrson Zhai port@1 { 4873c0e3abdSOrson Zhai reg = <0>; 4883c0e3abdSOrson Zhai cluster0_etf_in: endpoint { 4893c0e3abdSOrson Zhai slave-mode; 4903c0e3abdSOrson Zhai remote-endpoint = 4913c0e3abdSOrson Zhai <&cluster0_funnel_out_port>; 4923c0e3abdSOrson Zhai }; 4933c0e3abdSOrson Zhai }; 4943c0e3abdSOrson Zhai }; 4953c0e3abdSOrson Zhai }; 4963c0e3abdSOrson Zhai 4973c0e3abdSOrson Zhai etf@11004000 { /* ETF on Cluster1 */ 4983c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 4993c0e3abdSOrson Zhai reg = <0 0x11004000 0 0x1000>; 5003c0e3abdSOrson Zhai clocks = <&ext_26m>; 5013c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5023c0e3abdSOrson Zhai 5033c0e3abdSOrson Zhai ports { 5043c0e3abdSOrson Zhai #address-cells = <1>; 5053c0e3abdSOrson Zhai #size-cells = <0>; 5063c0e3abdSOrson Zhai 5073c0e3abdSOrson Zhai port@0 { 5083c0e3abdSOrson Zhai reg = <0>; 5093c0e3abdSOrson Zhai cluster1_etf_out: endpoint { 5103c0e3abdSOrson Zhai remote-endpoint = 5113c0e3abdSOrson Zhai <&main_funnel_in_port1>; 5123c0e3abdSOrson Zhai }; 5133c0e3abdSOrson Zhai }; 5143c0e3abdSOrson Zhai 5153c0e3abdSOrson Zhai port@1 { 5163c0e3abdSOrson Zhai reg = <0>; 5173c0e3abdSOrson Zhai cluster1_etf_in: endpoint { 5183c0e3abdSOrson Zhai slave-mode; 5193c0e3abdSOrson Zhai remote-endpoint = 5203c0e3abdSOrson Zhai <&cluster1_funnel_out_port>; 5213c0e3abdSOrson Zhai }; 5223c0e3abdSOrson Zhai }; 5233c0e3abdSOrson Zhai }; 5243c0e3abdSOrson Zhai }; 5253c0e3abdSOrson Zhai 5263c0e3abdSOrson Zhai funnel@11005000 { /* Main Funnel */ 5273c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 5283c0e3abdSOrson Zhai reg = <0 0x11005000 0 0x1000>; 5293c0e3abdSOrson Zhai clocks = <&ext_26m>; 5303c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5313c0e3abdSOrson Zhai 5323c0e3abdSOrson Zhai ports { 5333c0e3abdSOrson Zhai #address-cells = <1>; 5343c0e3abdSOrson Zhai #size-cells = <0>; 5353c0e3abdSOrson Zhai 5363c0e3abdSOrson Zhai port@0 { 5373c0e3abdSOrson Zhai reg = <0>; 5383c0e3abdSOrson Zhai main_funnel_out_port: endpoint { 5393c0e3abdSOrson Zhai remote-endpoint = 5403c0e3abdSOrson Zhai <&soc_funnel_in_port0>; 5413c0e3abdSOrson Zhai }; 5423c0e3abdSOrson Zhai }; 5433c0e3abdSOrson Zhai 5443c0e3abdSOrson Zhai port@1 { 5453c0e3abdSOrson Zhai reg = <0>; 5463c0e3abdSOrson Zhai main_funnel_in_port0: endpoint { 5473c0e3abdSOrson Zhai slave-mode; 5483c0e3abdSOrson Zhai remote-endpoint = 5493c0e3abdSOrson Zhai <&cluster0_etf_out>; 5503c0e3abdSOrson Zhai }; 5513c0e3abdSOrson Zhai }; 5523c0e3abdSOrson Zhai 5533c0e3abdSOrson Zhai port@2 { 5543c0e3abdSOrson Zhai reg = <1>; 5553c0e3abdSOrson Zhai main_funnel_in_port1: endpoint { 5563c0e3abdSOrson Zhai slave-mode; 5573c0e3abdSOrson Zhai remote-endpoint = 5583c0e3abdSOrson Zhai <&cluster1_etf_out>; 5593c0e3abdSOrson Zhai }; 5603c0e3abdSOrson Zhai }; 5613c0e3abdSOrson Zhai }; 5623c0e3abdSOrson Zhai }; 5633c0e3abdSOrson Zhai 5643c0e3abdSOrson Zhai etm@11440000 { 5653c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5663c0e3abdSOrson Zhai reg = <0 0x11440000 0 0x1000>; 5673c0e3abdSOrson Zhai cpu = <&CPU0>; 5683c0e3abdSOrson Zhai clocks = <&ext_26m>; 5693c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5703c0e3abdSOrson Zhai 5713c0e3abdSOrson Zhai port { 5723c0e3abdSOrson Zhai etm0_out: endpoint { 5733c0e3abdSOrson Zhai remote-endpoint = 5743c0e3abdSOrson Zhai <&cluster0_funnel_in_port0>; 5753c0e3abdSOrson Zhai }; 5763c0e3abdSOrson Zhai }; 5773c0e3abdSOrson Zhai }; 5783c0e3abdSOrson Zhai 5793c0e3abdSOrson Zhai etm@11540000 { 5803c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5813c0e3abdSOrson Zhai reg = <0 0x11540000 0 0x1000>; 5823c0e3abdSOrson Zhai cpu = <&CPU1>; 5833c0e3abdSOrson Zhai clocks = <&ext_26m>; 5843c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5853c0e3abdSOrson Zhai 5863c0e3abdSOrson Zhai port { 5873c0e3abdSOrson Zhai etm1_out: endpoint { 5883c0e3abdSOrson Zhai remote-endpoint = 5893c0e3abdSOrson Zhai <&cluster0_funnel_in_port1>; 5903c0e3abdSOrson Zhai }; 5913c0e3abdSOrson Zhai }; 5923c0e3abdSOrson Zhai }; 5933c0e3abdSOrson Zhai 5943c0e3abdSOrson Zhai etm@11640000 { 5953c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5963c0e3abdSOrson Zhai reg = <0 0x11640000 0 0x1000>; 5973c0e3abdSOrson Zhai cpu = <&CPU2>; 5983c0e3abdSOrson Zhai clocks = <&ext_26m>; 5993c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6003c0e3abdSOrson Zhai 6013c0e3abdSOrson Zhai port { 6023c0e3abdSOrson Zhai etm2_out: endpoint { 6033c0e3abdSOrson Zhai remote-endpoint = 6043c0e3abdSOrson Zhai <&cluster0_funnel_in_port2>; 6053c0e3abdSOrson Zhai }; 6063c0e3abdSOrson Zhai }; 6073c0e3abdSOrson Zhai }; 6083c0e3abdSOrson Zhai 6093c0e3abdSOrson Zhai etm@11740000 { 6103c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6113c0e3abdSOrson Zhai reg = <0 0x11740000 0 0x1000>; 6123c0e3abdSOrson Zhai cpu = <&CPU3>; 6133c0e3abdSOrson Zhai clocks = <&ext_26m>; 6143c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6153c0e3abdSOrson Zhai 6163c0e3abdSOrson Zhai port { 6173c0e3abdSOrson Zhai etm3_out: endpoint { 6183c0e3abdSOrson Zhai remote-endpoint = 6193c0e3abdSOrson Zhai <&cluster0_funnel_in_port3>; 6203c0e3abdSOrson Zhai }; 6213c0e3abdSOrson Zhai }; 6223c0e3abdSOrson Zhai }; 6233c0e3abdSOrson Zhai 6243c0e3abdSOrson Zhai etm@11840000 { 6253c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6263c0e3abdSOrson Zhai reg = <0 0x11840000 0 0x1000>; 6273c0e3abdSOrson Zhai cpu = <&CPU4>; 6283c0e3abdSOrson Zhai clocks = <&ext_26m>; 6293c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6303c0e3abdSOrson Zhai 6313c0e3abdSOrson Zhai port { 6323c0e3abdSOrson Zhai etm4_out: endpoint { 6333c0e3abdSOrson Zhai remote-endpoint = 6343c0e3abdSOrson Zhai <&cluster1_funnel_in_port0>; 6353c0e3abdSOrson Zhai }; 6363c0e3abdSOrson Zhai }; 6373c0e3abdSOrson Zhai }; 6383c0e3abdSOrson Zhai 6393c0e3abdSOrson Zhai etm@11940000 { 6403c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6413c0e3abdSOrson Zhai reg = <0 0x11940000 0 0x1000>; 6423c0e3abdSOrson Zhai cpu = <&CPU5>; 6433c0e3abdSOrson Zhai clocks = <&ext_26m>; 6443c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6453c0e3abdSOrson Zhai 6463c0e3abdSOrson Zhai port { 6473c0e3abdSOrson Zhai etm5_out: endpoint { 6483c0e3abdSOrson Zhai remote-endpoint = 6493c0e3abdSOrson Zhai <&cluster1_funnel_in_port1>; 6503c0e3abdSOrson Zhai }; 6513c0e3abdSOrson Zhai }; 6523c0e3abdSOrson Zhai }; 6533c0e3abdSOrson Zhai 6543c0e3abdSOrson Zhai etm@11a40000 { 6553c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6563c0e3abdSOrson Zhai reg = <0 0x11a40000 0 0x1000>; 6573c0e3abdSOrson Zhai cpu = <&CPU6>; 6583c0e3abdSOrson Zhai clocks = <&ext_26m>; 6593c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6603c0e3abdSOrson Zhai 6613c0e3abdSOrson Zhai port { 6623c0e3abdSOrson Zhai etm6_out: endpoint { 6633c0e3abdSOrson Zhai remote-endpoint = 6643c0e3abdSOrson Zhai <&cluster1_funnel_in_port2>; 6653c0e3abdSOrson Zhai }; 6663c0e3abdSOrson Zhai }; 6673c0e3abdSOrson Zhai }; 6683c0e3abdSOrson Zhai 6693c0e3abdSOrson Zhai etm@11b40000 { 6703c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6713c0e3abdSOrson Zhai reg = <0 0x11b40000 0 0x1000>; 6723c0e3abdSOrson Zhai cpu = <&CPU7>; 6733c0e3abdSOrson Zhai clocks = <&ext_26m>; 6743c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6753c0e3abdSOrson Zhai 6763c0e3abdSOrson Zhai port { 6773c0e3abdSOrson Zhai etm7_out: endpoint { 6783c0e3abdSOrson Zhai remote-endpoint = 6793c0e3abdSOrson Zhai <&cluster1_funnel_in_port3>; 6803c0e3abdSOrson Zhai }; 6813c0e3abdSOrson Zhai }; 6823c0e3abdSOrson Zhai }; 6833c0e3abdSOrson Zhai }; 6843c0e3abdSOrson Zhai}; 685