13c0e3abdSOrson Zhai/* 23c0e3abdSOrson Zhai * Spreadtrum SC9860 SoC 33c0e3abdSOrson Zhai * 43c0e3abdSOrson Zhai * Copyright (C) 2016, Spreadtrum Communications Inc. 53c0e3abdSOrson Zhai * 63c0e3abdSOrson Zhai * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 73c0e3abdSOrson Zhai */ 83c0e3abdSOrson Zhai 93c0e3abdSOrson Zhai#include <dt-bindings/interrupt-controller/arm-gic.h> 101cea2c22SBaolin Wang#include <dt-bindings/input/input.h> 111cea2c22SBaolin Wang#include <dt-bindings/gpio/gpio.h> 123c0e3abdSOrson Zhai#include "whale2.dtsi" 133c0e3abdSOrson Zhai 143c0e3abdSOrson Zhai/ { 153c0e3abdSOrson Zhai cpus { 163c0e3abdSOrson Zhai #address-cells = <2>; 173c0e3abdSOrson Zhai #size-cells = <0>; 183c0e3abdSOrson Zhai 193c0e3abdSOrson Zhai cpu-map { 203c0e3abdSOrson Zhai cluster0 { 213c0e3abdSOrson Zhai core0 { 223c0e3abdSOrson Zhai cpu = <&CPU0>; 233c0e3abdSOrson Zhai }; 243c0e3abdSOrson Zhai core1 { 253c0e3abdSOrson Zhai cpu = <&CPU1>; 263c0e3abdSOrson Zhai }; 273c0e3abdSOrson Zhai core2 { 283c0e3abdSOrson Zhai cpu = <&CPU2>; 293c0e3abdSOrson Zhai }; 303c0e3abdSOrson Zhai core3 { 313c0e3abdSOrson Zhai cpu = <&CPU3>; 323c0e3abdSOrson Zhai }; 333c0e3abdSOrson Zhai }; 343c0e3abdSOrson Zhai 353c0e3abdSOrson Zhai cluster1 { 363c0e3abdSOrson Zhai core0 { 373c0e3abdSOrson Zhai cpu = <&CPU4>; 383c0e3abdSOrson Zhai }; 393c0e3abdSOrson Zhai core1 { 403c0e3abdSOrson Zhai cpu = <&CPU5>; 413c0e3abdSOrson Zhai }; 423c0e3abdSOrson Zhai core2 { 433c0e3abdSOrson Zhai cpu = <&CPU6>; 443c0e3abdSOrson Zhai }; 453c0e3abdSOrson Zhai core3 { 463c0e3abdSOrson Zhai cpu = <&CPU7>; 473c0e3abdSOrson Zhai }; 483c0e3abdSOrson Zhai }; 493c0e3abdSOrson Zhai }; 503c0e3abdSOrson Zhai 513c0e3abdSOrson Zhai CPU0: cpu@530000 { 523c0e3abdSOrson Zhai device_type = "cpu"; 533c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 543c0e3abdSOrson Zhai reg = <0x0 0x530000>; 553c0e3abdSOrson Zhai enable-method = "psci"; 563c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 573c0e3abdSOrson Zhai }; 583c0e3abdSOrson Zhai 593c0e3abdSOrson Zhai CPU1: cpu@530001 { 603c0e3abdSOrson Zhai device_type = "cpu"; 613c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 623c0e3abdSOrson Zhai reg = <0x0 0x530001>; 633c0e3abdSOrson Zhai enable-method = "psci"; 643c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 653c0e3abdSOrson Zhai }; 663c0e3abdSOrson Zhai 673c0e3abdSOrson Zhai CPU2: cpu@530002 { 683c0e3abdSOrson Zhai device_type = "cpu"; 693c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 703c0e3abdSOrson Zhai reg = <0x0 0x530002>; 713c0e3abdSOrson Zhai enable-method = "psci"; 723c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 733c0e3abdSOrson Zhai }; 743c0e3abdSOrson Zhai 753c0e3abdSOrson Zhai CPU3: cpu@530003 { 763c0e3abdSOrson Zhai device_type = "cpu"; 773c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 783c0e3abdSOrson Zhai reg = <0x0 0x530003>; 793c0e3abdSOrson Zhai enable-method = "psci"; 803c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 813c0e3abdSOrson Zhai }; 823c0e3abdSOrson Zhai 833c0e3abdSOrson Zhai CPU4: cpu@530100 { 843c0e3abdSOrson Zhai device_type = "cpu"; 853c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 863c0e3abdSOrson Zhai reg = <0x0 0x530100>; 873c0e3abdSOrson Zhai enable-method = "psci"; 883c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 893c0e3abdSOrson Zhai }; 903c0e3abdSOrson Zhai 913c0e3abdSOrson Zhai CPU5: cpu@530101 { 923c0e3abdSOrson Zhai device_type = "cpu"; 933c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 943c0e3abdSOrson Zhai reg = <0x0 0x530101>; 953c0e3abdSOrson Zhai enable-method = "psci"; 963c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 973c0e3abdSOrson Zhai }; 983c0e3abdSOrson Zhai 993c0e3abdSOrson Zhai CPU6: cpu@530102 { 1003c0e3abdSOrson Zhai device_type = "cpu"; 1013c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 1023c0e3abdSOrson Zhai reg = <0x0 0x530102>; 1033c0e3abdSOrson Zhai enable-method = "psci"; 1043c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 1053c0e3abdSOrson Zhai }; 1063c0e3abdSOrson Zhai 1073c0e3abdSOrson Zhai CPU7: cpu@530103 { 1083c0e3abdSOrson Zhai device_type = "cpu"; 1093c0e3abdSOrson Zhai compatible = "arm,cortex-a53", "arm,armv8"; 1103c0e3abdSOrson Zhai reg = <0x0 0x530103>; 1113c0e3abdSOrson Zhai enable-method = "psci"; 1123c0e3abdSOrson Zhai cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 1133c0e3abdSOrson Zhai }; 1143c0e3abdSOrson Zhai }; 1153c0e3abdSOrson Zhai 1163c0e3abdSOrson Zhai idle-states{ 117e9880240SAmit Kucheria entry-method = "psci"; 1183c0e3abdSOrson Zhai 1193c0e3abdSOrson Zhai CORE_PD: core_pd { 1203c0e3abdSOrson Zhai compatible = "arm,idle-state"; 1213c0e3abdSOrson Zhai entry-latency-us = <1000>; 1223c0e3abdSOrson Zhai exit-latency-us = <700>; 1233c0e3abdSOrson Zhai min-residency-us = <2500>; 1243c0e3abdSOrson Zhai local-timer-stop; 1253c0e3abdSOrson Zhai arm,psci-suspend-param = <0x00010002>; 1263c0e3abdSOrson Zhai }; 1273c0e3abdSOrson Zhai 1283c0e3abdSOrson Zhai CLUSTER_PD: cluster_pd { 1293c0e3abdSOrson Zhai compatible = "arm,idle-state"; 1303c0e3abdSOrson Zhai entry-latency-us = <1000>; 1313c0e3abdSOrson Zhai exit-latency-us = <1000>; 1323c0e3abdSOrson Zhai min-residency-us = <3000>; 1333c0e3abdSOrson Zhai local-timer-stop; 1343c0e3abdSOrson Zhai arm,psci-suspend-param = <0x01010003>; 1353c0e3abdSOrson Zhai }; 1363c0e3abdSOrson Zhai }; 1373c0e3abdSOrson Zhai 1383c0e3abdSOrson Zhai gic: interrupt-controller@12001000 { 1393c0e3abdSOrson Zhai compatible = "arm,gic-400"; 1403c0e3abdSOrson Zhai reg = <0 0x12001000 0 0x1000>, 1413c0e3abdSOrson Zhai <0 0x12002000 0 0x2000>, 1423c0e3abdSOrson Zhai <0 0x12004000 0 0x2000>, 1433c0e3abdSOrson Zhai <0 0x12006000 0 0x2000>; 1443c0e3abdSOrson Zhai #interrupt-cells = <3>; 1453c0e3abdSOrson Zhai interrupt-controller; 1463c0e3abdSOrson Zhai interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) 1473c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_HIGH)>; 1483c0e3abdSOrson Zhai }; 1493c0e3abdSOrson Zhai 1503c0e3abdSOrson Zhai psci { 1513c0e3abdSOrson Zhai compatible = "arm,psci-0.2"; 1523c0e3abdSOrson Zhai method = "smc"; 1533c0e3abdSOrson Zhai }; 1543c0e3abdSOrson Zhai 1553c0e3abdSOrson Zhai timer { 1563c0e3abdSOrson Zhai compatible = "arm,armv8-timer"; 1573c0e3abdSOrson Zhai interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) 1583c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1593c0e3abdSOrson Zhai <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) 1603c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1613c0e3abdSOrson Zhai <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) 1623c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>, 1633c0e3abdSOrson Zhai <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) 1643c0e3abdSOrson Zhai | IRQ_TYPE_LEVEL_LOW)>; 1653c0e3abdSOrson Zhai }; 1663c0e3abdSOrson Zhai 1673c0e3abdSOrson Zhai pmu { 1683c0e3abdSOrson Zhai compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; 1693c0e3abdSOrson Zhai interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1703c0e3abdSOrson Zhai <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1713c0e3abdSOrson Zhai <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1723c0e3abdSOrson Zhai <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1733c0e3abdSOrson Zhai <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1743c0e3abdSOrson Zhai <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1753c0e3abdSOrson Zhai <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1763c0e3abdSOrson Zhai <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1773c0e3abdSOrson Zhai interrupt-affinity = <&CPU0>, 1783c0e3abdSOrson Zhai <&CPU1>, 1793c0e3abdSOrson Zhai <&CPU2>, 1803c0e3abdSOrson Zhai <&CPU3>, 1813c0e3abdSOrson Zhai <&CPU4>, 1823c0e3abdSOrson Zhai <&CPU5>, 1833c0e3abdSOrson Zhai <&CPU6>, 1843c0e3abdSOrson Zhai <&CPU7>; 1853c0e3abdSOrson Zhai }; 1863c0e3abdSOrson Zhai 1873c0e3abdSOrson Zhai soc { 18822f37a24SChunyan Zhang pmu_gate: pmu-gate { 18922f37a24SChunyan Zhang compatible = "sprd,sc9860-pmu-gate"; 19022f37a24SChunyan Zhang sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ 19122f37a24SChunyan Zhang clocks = <&ext_26m>; 19222f37a24SChunyan Zhang #clock-cells = <1>; 19322f37a24SChunyan Zhang }; 19422f37a24SChunyan Zhang 19522f37a24SChunyan Zhang pll: pll { 19622f37a24SChunyan Zhang compatible = "sprd,sc9860-pll"; 19722f37a24SChunyan Zhang sprd,syscon = <&ana_regs>; /* 0x40400000 */ 19822f37a24SChunyan Zhang clocks = <&pmu_gate 0>; 19922f37a24SChunyan Zhang #clock-cells = <1>; 20022f37a24SChunyan Zhang }; 20122f37a24SChunyan Zhang 20222f37a24SChunyan Zhang ap_clk: clock-controller@20000000 { 20322f37a24SChunyan Zhang compatible = "sprd,sc9860-ap-clk"; 20422f37a24SChunyan Zhang reg = <0 0x20000000 0 0x400>; 20522f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>, 20622f37a24SChunyan Zhang <&pmu_gate 0>; 20722f37a24SChunyan Zhang #clock-cells = <1>; 20822f37a24SChunyan Zhang }; 20922f37a24SChunyan Zhang 21022f37a24SChunyan Zhang aon_prediv: aon-prediv { 21122f37a24SChunyan Zhang compatible = "sprd,sc9860-aon-prediv"; 21222f37a24SChunyan Zhang reg = <0 0x402d0000 0 0x400>; 21322f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>, 21422f37a24SChunyan Zhang <&pmu_gate 0>; 21522f37a24SChunyan Zhang #clock-cells = <1>; 21622f37a24SChunyan Zhang }; 21722f37a24SChunyan Zhang 21822f37a24SChunyan Zhang apahb_gate: apahb-gate { 21922f37a24SChunyan Zhang compatible = "sprd,sc9860-apahb-gate"; 22022f37a24SChunyan Zhang sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ 22122f37a24SChunyan Zhang clocks = <&aon_prediv 0>; 22222f37a24SChunyan Zhang #clock-cells = <1>; 22322f37a24SChunyan Zhang }; 22422f37a24SChunyan Zhang 22522f37a24SChunyan Zhang aon_gate: aon-gate { 22622f37a24SChunyan Zhang compatible = "sprd,sc9860-aon-gate"; 22722f37a24SChunyan Zhang sprd,syscon = <&aon_regs>; /* 0x402e0000 */ 22822f37a24SChunyan Zhang clocks = <&aon_prediv 0>; 22922f37a24SChunyan Zhang #clock-cells = <1>; 23022f37a24SChunyan Zhang }; 23122f37a24SChunyan Zhang 23222f37a24SChunyan Zhang aonsecure_clk: clock-controller@40880000 { 23322f37a24SChunyan Zhang compatible = "sprd,sc9860-aonsecure-clk"; 23422f37a24SChunyan Zhang reg = <0 0x40880000 0 0x400>; 23522f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>; 23622f37a24SChunyan Zhang #clock-cells = <1>; 23722f37a24SChunyan Zhang }; 23822f37a24SChunyan Zhang 23922f37a24SChunyan Zhang agcp_gate: agcp-gate { 24022f37a24SChunyan Zhang compatible = "sprd,sc9860-agcp-gate"; 24122f37a24SChunyan Zhang sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ 24222f37a24SChunyan Zhang clocks = <&aon_prediv 0>; 24322f37a24SChunyan Zhang #clock-cells = <1>; 24422f37a24SChunyan Zhang }; 24522f37a24SChunyan Zhang 24622f37a24SChunyan Zhang gpu_clk: clock-controller@60200000 { 24722f37a24SChunyan Zhang compatible = "sprd,sc9860-gpu-clk"; 24822f37a24SChunyan Zhang reg = <0 0x60200000 0 0x400>; 24922f37a24SChunyan Zhang clocks = <&pll 0>; 25022f37a24SChunyan Zhang #clock-cells = <1>; 25122f37a24SChunyan Zhang }; 25222f37a24SChunyan Zhang 25322f37a24SChunyan Zhang vsp_clk: clock-controller@61000000 { 25422f37a24SChunyan Zhang compatible = "sprd,sc9860-vsp-clk"; 25522f37a24SChunyan Zhang reg = <0 0x61000000 0 0x400>; 25622f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>; 25722f37a24SChunyan Zhang #clock-cells = <1>; 25822f37a24SChunyan Zhang }; 25922f37a24SChunyan Zhang 26022f37a24SChunyan Zhang vsp_gate: vsp-gate { 26122f37a24SChunyan Zhang compatible = "sprd,sc9860-vsp-gate"; 26222f37a24SChunyan Zhang sprd,syscon = <&vsp_regs>; /* 0x61100000 */ 26322f37a24SChunyan Zhang clocks = <&vsp_clk 0>; 26422f37a24SChunyan Zhang #clock-cells = <1>; 26522f37a24SChunyan Zhang }; 26622f37a24SChunyan Zhang 26722f37a24SChunyan Zhang cam_clk: clock-controller@62000000 { 26822f37a24SChunyan Zhang compatible = "sprd,sc9860-cam-clk"; 26922f37a24SChunyan Zhang reg = <0 0x62000000 0 0x4000>; 27022f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>; 27122f37a24SChunyan Zhang #clock-cells = <1>; 27222f37a24SChunyan Zhang }; 27322f37a24SChunyan Zhang 27422f37a24SChunyan Zhang cam_gate: cam-gate { 27522f37a24SChunyan Zhang compatible = "sprd,sc9860-cam-gate"; 27622f37a24SChunyan Zhang sprd,syscon = <&cam_regs>; /* 0x62100000 */ 27722f37a24SChunyan Zhang clocks = <&cam_clk 0>; 27822f37a24SChunyan Zhang #clock-cells = <1>; 27922f37a24SChunyan Zhang }; 28022f37a24SChunyan Zhang 28122f37a24SChunyan Zhang disp_clk: clock-controller@63000000 { 28222f37a24SChunyan Zhang compatible = "sprd,sc9860-disp-clk"; 28322f37a24SChunyan Zhang reg = <0 0x63000000 0 0x400>; 28422f37a24SChunyan Zhang clocks = <&ext_26m>, <&pll 0>; 28522f37a24SChunyan Zhang #clock-cells = <1>; 28622f37a24SChunyan Zhang }; 28722f37a24SChunyan Zhang 28822f37a24SChunyan Zhang disp_gate: disp-gate { 28922f37a24SChunyan Zhang compatible = "sprd,sc9860-disp-gate"; 29022f37a24SChunyan Zhang sprd,syscon = <&disp_regs>; /* 0x63100000 */ 29122f37a24SChunyan Zhang clocks = <&disp_clk 0>; 29222f37a24SChunyan Zhang #clock-cells = <1>; 29322f37a24SChunyan Zhang }; 29422f37a24SChunyan Zhang 29522f37a24SChunyan Zhang apapb_gate: apapb-gate { 29622f37a24SChunyan Zhang compatible = "sprd,sc9860-apapb-gate"; 29722f37a24SChunyan Zhang sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ 29822f37a24SChunyan Zhang clocks = <&ap_clk 0>; 29922f37a24SChunyan Zhang #clock-cells = <1>; 30022f37a24SChunyan Zhang }; 30122f37a24SChunyan Zhang 3023c0e3abdSOrson Zhai funnel@10001000 { /* SoC Funnel */ 3033c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 3043c0e3abdSOrson Zhai reg = <0 0x10001000 0 0x1000>; 3053c0e3abdSOrson Zhai clocks = <&ext_26m>; 3063c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3071a9e7796SSuzuki K Poulose out-ports { 3081a9e7796SSuzuki K Poulose port { 3091a9e7796SSuzuki K Poulose soc_funnel_out_port: endpoint { 3101a9e7796SSuzuki K Poulose remote-endpoint = <&etb_in>; 3111a9e7796SSuzuki K Poulose }; 3121a9e7796SSuzuki K Poulose }; 3131a9e7796SSuzuki K Poulose }; 3141a9e7796SSuzuki K Poulose 3151a9e7796SSuzuki K Poulose in-ports { 3163c0e3abdSOrson Zhai #address-cells = <1>; 3173c0e3abdSOrson Zhai #size-cells = <0>; 3183c0e3abdSOrson Zhai 3193c0e3abdSOrson Zhai port@0 { 3203c0e3abdSOrson Zhai reg = <0>; 3213c0e3abdSOrson Zhai soc_funnel_in_port0: endpoint { 3223c0e3abdSOrson Zhai remote-endpoint = 3233c0e3abdSOrson Zhai <&main_funnel_out_port>; 3243c0e3abdSOrson Zhai }; 3253c0e3abdSOrson Zhai }; 3263c0e3abdSOrson Zhai 3271a9e7796SSuzuki K Poulose port@4 { 3283c0e3abdSOrson Zhai reg = <4>; 3293c0e3abdSOrson Zhai soc_funnel_in_port1: endpoint { 330e0c66d34SRob Herring remote-endpoint = 3313c0e3abdSOrson Zhai <&stm_out_port>; 3323c0e3abdSOrson Zhai }; 3333c0e3abdSOrson Zhai }; 3343c0e3abdSOrson Zhai }; 3353c0e3abdSOrson Zhai }; 3363c0e3abdSOrson Zhai 3373c0e3abdSOrson Zhai etb@10003000 { 3383c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 3393c0e3abdSOrson Zhai reg = <0 0x10003000 0 0x1000>; 3403c0e3abdSOrson Zhai clocks = <&ext_26m>; 3413c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3421a9e7796SSuzuki K Poulose out-ports { 3433c0e3abdSOrson Zhai port { 3443c0e3abdSOrson Zhai etb_in: endpoint { 3453c0e3abdSOrson Zhai remote-endpoint = 3463c0e3abdSOrson Zhai <&soc_funnel_out_port>; 3473c0e3abdSOrson Zhai }; 3483c0e3abdSOrson Zhai }; 3493c0e3abdSOrson Zhai }; 3501a9e7796SSuzuki K Poulose }; 3513c0e3abdSOrson Zhai 3523c0e3abdSOrson Zhai stm@10006000 { 3533c0e3abdSOrson Zhai compatible = "arm,coresight-stm", "arm,primecell"; 3543c0e3abdSOrson Zhai reg = <0 0x10006000 0 0x1000>, 3553c0e3abdSOrson Zhai <0 0x01000000 0 0x180000>; 3563c0e3abdSOrson Zhai reg-names = "stm-base", "stm-stimulus-base"; 3573c0e3abdSOrson Zhai clocks = <&ext_26m>; 3583c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3591a9e7796SSuzuki K Poulose out-ports { 3603c0e3abdSOrson Zhai port { 3613c0e3abdSOrson Zhai stm_out_port: endpoint { 3623c0e3abdSOrson Zhai remote-endpoint = 3633c0e3abdSOrson Zhai <&soc_funnel_in_port1>; 3643c0e3abdSOrson Zhai }; 3653c0e3abdSOrson Zhai }; 3663c0e3abdSOrson Zhai }; 3671a9e7796SSuzuki K Poulose }; 3683c0e3abdSOrson Zhai 3693c0e3abdSOrson Zhai funnel@11001000 { /* Cluster0 Funnel */ 3703c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 3713c0e3abdSOrson Zhai reg = <0 0x11001000 0 0x1000>; 3723c0e3abdSOrson Zhai clocks = <&ext_26m>; 3733c0e3abdSOrson Zhai clock-names = "apb_pclk"; 3741a9e7796SSuzuki K Poulose out-ports { 3751a9e7796SSuzuki K Poulose port { 3763c0e3abdSOrson Zhai cluster0_funnel_out_port: endpoint { 3773c0e3abdSOrson Zhai remote-endpoint = 3783c0e3abdSOrson Zhai <&cluster0_etf_in>; 3793c0e3abdSOrson Zhai }; 3803c0e3abdSOrson Zhai }; 3811a9e7796SSuzuki K Poulose }; 3823c0e3abdSOrson Zhai 3831a9e7796SSuzuki K Poulose in-ports { 3841a9e7796SSuzuki K Poulose #address-cells = <1>; 3851a9e7796SSuzuki K Poulose #size-cells = <0>; 3861a9e7796SSuzuki K Poulose 3871a9e7796SSuzuki K Poulose port@0 { 3883c0e3abdSOrson Zhai reg = <0>; 3893c0e3abdSOrson Zhai cluster0_funnel_in_port0: endpoint { 3903c0e3abdSOrson Zhai remote-endpoint = <&etm0_out>; 3913c0e3abdSOrson Zhai }; 3923c0e3abdSOrson Zhai }; 3933c0e3abdSOrson Zhai 3941a9e7796SSuzuki K Poulose port@1 { 3953c0e3abdSOrson Zhai reg = <1>; 3963c0e3abdSOrson Zhai cluster0_funnel_in_port1: endpoint { 3973c0e3abdSOrson Zhai remote-endpoint = <&etm1_out>; 3983c0e3abdSOrson Zhai }; 3993c0e3abdSOrson Zhai }; 4003c0e3abdSOrson Zhai 4011a9e7796SSuzuki K Poulose port@2 { 4023c0e3abdSOrson Zhai reg = <2>; 4033c0e3abdSOrson Zhai cluster0_funnel_in_port2: endpoint { 4043c0e3abdSOrson Zhai remote-endpoint = <&etm2_out>; 4053c0e3abdSOrson Zhai }; 4063c0e3abdSOrson Zhai }; 4073c0e3abdSOrson Zhai 4083c0e3abdSOrson Zhai port@4 { 4093c0e3abdSOrson Zhai reg = <4>; 4103c0e3abdSOrson Zhai cluster0_funnel_in_port3: endpoint { 4113c0e3abdSOrson Zhai remote-endpoint = <&etm3_out>; 4123c0e3abdSOrson Zhai }; 4133c0e3abdSOrson Zhai }; 4143c0e3abdSOrson Zhai }; 4153c0e3abdSOrson Zhai }; 4163c0e3abdSOrson Zhai 4173c0e3abdSOrson Zhai funnel@11002000 { /* Cluster1 Funnel */ 4183c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 4193c0e3abdSOrson Zhai reg = <0 0x11002000 0 0x1000>; 4203c0e3abdSOrson Zhai clocks = <&ext_26m>; 4213c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4221a9e7796SSuzuki K Poulose out-ports { 4231a9e7796SSuzuki K Poulose port { 4243c0e3abdSOrson Zhai cluster1_funnel_out_port: endpoint { 4253c0e3abdSOrson Zhai remote-endpoint = 4263c0e3abdSOrson Zhai <&cluster1_etf_in>; 4273c0e3abdSOrson Zhai }; 4283c0e3abdSOrson Zhai }; 4291a9e7796SSuzuki K Poulose }; 4303c0e3abdSOrson Zhai 4311a9e7796SSuzuki K Poulose in-ports { 4321a9e7796SSuzuki K Poulose #address-cells = <1>; 4331a9e7796SSuzuki K Poulose #size-cells = <0>; 4341a9e7796SSuzuki K Poulose 4351a9e7796SSuzuki K Poulose port@0 { 4363c0e3abdSOrson Zhai reg = <0>; 4373c0e3abdSOrson Zhai cluster1_funnel_in_port0: endpoint { 4383c0e3abdSOrson Zhai remote-endpoint = <&etm4_out>; 4393c0e3abdSOrson Zhai }; 4403c0e3abdSOrson Zhai }; 4413c0e3abdSOrson Zhai 4421a9e7796SSuzuki K Poulose port@1 { 4433c0e3abdSOrson Zhai reg = <1>; 4443c0e3abdSOrson Zhai cluster1_funnel_in_port1: endpoint { 4453c0e3abdSOrson Zhai remote-endpoint = <&etm5_out>; 4463c0e3abdSOrson Zhai }; 4473c0e3abdSOrson Zhai }; 4483c0e3abdSOrson Zhai 4491a9e7796SSuzuki K Poulose port@2 { 4503c0e3abdSOrson Zhai reg = <2>; 4513c0e3abdSOrson Zhai cluster1_funnel_in_port2: endpoint { 4523c0e3abdSOrson Zhai remote-endpoint = <&etm6_out>; 4533c0e3abdSOrson Zhai }; 4543c0e3abdSOrson Zhai }; 4553c0e3abdSOrson Zhai 4561a9e7796SSuzuki K Poulose port@3 { 4573c0e3abdSOrson Zhai reg = <3>; 4583c0e3abdSOrson Zhai cluster1_funnel_in_port3: endpoint { 4593c0e3abdSOrson Zhai remote-endpoint = <&etm7_out>; 4603c0e3abdSOrson Zhai }; 4613c0e3abdSOrson Zhai }; 4623c0e3abdSOrson Zhai }; 4633c0e3abdSOrson Zhai }; 4643c0e3abdSOrson Zhai 4653c0e3abdSOrson Zhai etf@11003000 { /* ETF on Cluster0 */ 4663c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 4673c0e3abdSOrson Zhai reg = <0 0x11003000 0 0x1000>; 4683c0e3abdSOrson Zhai clocks = <&ext_26m>; 4693c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4703c0e3abdSOrson Zhai 4711a9e7796SSuzuki K Poulose out-ports { 4721a9e7796SSuzuki K Poulose port { 4733c0e3abdSOrson Zhai cluster0_etf_out: endpoint { 4743c0e3abdSOrson Zhai remote-endpoint = 4753c0e3abdSOrson Zhai <&main_funnel_in_port0>; 4763c0e3abdSOrson Zhai }; 4773c0e3abdSOrson Zhai }; 4781a9e7796SSuzuki K Poulose }; 4793c0e3abdSOrson Zhai 4801a9e7796SSuzuki K Poulose in-ports { 4811a9e7796SSuzuki K Poulose port { 4823c0e3abdSOrson Zhai cluster0_etf_in: endpoint { 4833c0e3abdSOrson Zhai remote-endpoint = 4843c0e3abdSOrson Zhai <&cluster0_funnel_out_port>; 4853c0e3abdSOrson Zhai }; 4863c0e3abdSOrson Zhai }; 4873c0e3abdSOrson Zhai }; 4883c0e3abdSOrson Zhai }; 4893c0e3abdSOrson Zhai 4903c0e3abdSOrson Zhai etf@11004000 { /* ETF on Cluster1 */ 4913c0e3abdSOrson Zhai compatible = "arm,coresight-tmc", "arm,primecell"; 4923c0e3abdSOrson Zhai reg = <0 0x11004000 0 0x1000>; 4933c0e3abdSOrson Zhai clocks = <&ext_26m>; 4943c0e3abdSOrson Zhai clock-names = "apb_pclk"; 4953c0e3abdSOrson Zhai 4961a9e7796SSuzuki K Poulose out-ports { 4971a9e7796SSuzuki K Poulose port { 4983c0e3abdSOrson Zhai cluster1_etf_out: endpoint { 4993c0e3abdSOrson Zhai remote-endpoint = 5003c0e3abdSOrson Zhai <&main_funnel_in_port1>; 5013c0e3abdSOrson Zhai }; 5023c0e3abdSOrson Zhai }; 5031a9e7796SSuzuki K Poulose }; 5043c0e3abdSOrson Zhai 5051a9e7796SSuzuki K Poulose in-ports { 5061a9e7796SSuzuki K Poulose port { 5073c0e3abdSOrson Zhai cluster1_etf_in: endpoint { 5083c0e3abdSOrson Zhai remote-endpoint = 5093c0e3abdSOrson Zhai <&cluster1_funnel_out_port>; 5103c0e3abdSOrson Zhai }; 5113c0e3abdSOrson Zhai }; 5123c0e3abdSOrson Zhai }; 5133c0e3abdSOrson Zhai }; 5143c0e3abdSOrson Zhai 5153c0e3abdSOrson Zhai funnel@11005000 { /* Main Funnel */ 5163c0e3abdSOrson Zhai compatible = "arm,coresight-funnel", "arm,primecell"; 5173c0e3abdSOrson Zhai reg = <0 0x11005000 0 0x1000>; 5183c0e3abdSOrson Zhai clocks = <&ext_26m>; 5193c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5203c0e3abdSOrson Zhai 5211a9e7796SSuzuki K Poulose out-ports { 5221a9e7796SSuzuki K Poulose port { 5233c0e3abdSOrson Zhai main_funnel_out_port: endpoint { 5243c0e3abdSOrson Zhai remote-endpoint = 5253c0e3abdSOrson Zhai <&soc_funnel_in_port0>; 5263c0e3abdSOrson Zhai }; 5273c0e3abdSOrson Zhai }; 5281a9e7796SSuzuki K Poulose }; 5293c0e3abdSOrson Zhai 5301a9e7796SSuzuki K Poulose in-ports { 5311a9e7796SSuzuki K Poulose #address-cells = <1>; 5321a9e7796SSuzuki K Poulose #size-cells = <0>; 5331a9e7796SSuzuki K Poulose 5341a9e7796SSuzuki K Poulose port@0 { 5353c0e3abdSOrson Zhai reg = <0>; 5363c0e3abdSOrson Zhai main_funnel_in_port0: endpoint { 5373c0e3abdSOrson Zhai remote-endpoint = 5383c0e3abdSOrson Zhai <&cluster0_etf_out>; 5393c0e3abdSOrson Zhai }; 5403c0e3abdSOrson Zhai }; 5413c0e3abdSOrson Zhai 5421a9e7796SSuzuki K Poulose port@1 { 5433c0e3abdSOrson Zhai reg = <1>; 5443c0e3abdSOrson Zhai main_funnel_in_port1: endpoint { 5453c0e3abdSOrson Zhai remote-endpoint = 5463c0e3abdSOrson Zhai <&cluster1_etf_out>; 5473c0e3abdSOrson Zhai }; 5483c0e3abdSOrson Zhai }; 5493c0e3abdSOrson Zhai }; 5503c0e3abdSOrson Zhai }; 5513c0e3abdSOrson Zhai 5523c0e3abdSOrson Zhai etm@11440000 { 5533c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5543c0e3abdSOrson Zhai reg = <0 0x11440000 0 0x1000>; 5553c0e3abdSOrson Zhai cpu = <&CPU0>; 5563c0e3abdSOrson Zhai clocks = <&ext_26m>; 5573c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5583c0e3abdSOrson Zhai 5591a9e7796SSuzuki K Poulose out-ports { 5603c0e3abdSOrson Zhai port { 5613c0e3abdSOrson Zhai etm0_out: endpoint { 5623c0e3abdSOrson Zhai remote-endpoint = 5633c0e3abdSOrson Zhai <&cluster0_funnel_in_port0>; 5643c0e3abdSOrson Zhai }; 5653c0e3abdSOrson Zhai }; 5663c0e3abdSOrson Zhai }; 5671a9e7796SSuzuki K Poulose }; 5683c0e3abdSOrson Zhai 5693c0e3abdSOrson Zhai etm@11540000 { 5703c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5713c0e3abdSOrson Zhai reg = <0 0x11540000 0 0x1000>; 5723c0e3abdSOrson Zhai cpu = <&CPU1>; 5733c0e3abdSOrson Zhai clocks = <&ext_26m>; 5743c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5753c0e3abdSOrson Zhai 5761a9e7796SSuzuki K Poulose out-ports { 5773c0e3abdSOrson Zhai port { 5783c0e3abdSOrson Zhai etm1_out: endpoint { 5793c0e3abdSOrson Zhai remote-endpoint = 5803c0e3abdSOrson Zhai <&cluster0_funnel_in_port1>; 5813c0e3abdSOrson Zhai }; 5823c0e3abdSOrson Zhai }; 5833c0e3abdSOrson Zhai }; 5841a9e7796SSuzuki K Poulose }; 5853c0e3abdSOrson Zhai 5863c0e3abdSOrson Zhai etm@11640000 { 5873c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 5883c0e3abdSOrson Zhai reg = <0 0x11640000 0 0x1000>; 5893c0e3abdSOrson Zhai cpu = <&CPU2>; 5903c0e3abdSOrson Zhai clocks = <&ext_26m>; 5913c0e3abdSOrson Zhai clock-names = "apb_pclk"; 5923c0e3abdSOrson Zhai 5931a9e7796SSuzuki K Poulose out-ports { 5943c0e3abdSOrson Zhai port { 5953c0e3abdSOrson Zhai etm2_out: endpoint { 5963c0e3abdSOrson Zhai remote-endpoint = 5973c0e3abdSOrson Zhai <&cluster0_funnel_in_port2>; 5983c0e3abdSOrson Zhai }; 5993c0e3abdSOrson Zhai }; 6003c0e3abdSOrson Zhai }; 6011a9e7796SSuzuki K Poulose }; 6023c0e3abdSOrson Zhai 6033c0e3abdSOrson Zhai etm@11740000 { 6043c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6053c0e3abdSOrson Zhai reg = <0 0x11740000 0 0x1000>; 6063c0e3abdSOrson Zhai cpu = <&CPU3>; 6073c0e3abdSOrson Zhai clocks = <&ext_26m>; 6083c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6093c0e3abdSOrson Zhai 6101a9e7796SSuzuki K Poulose out-ports { 6113c0e3abdSOrson Zhai port { 6123c0e3abdSOrson Zhai etm3_out: endpoint { 6133c0e3abdSOrson Zhai remote-endpoint = 6143c0e3abdSOrson Zhai <&cluster0_funnel_in_port3>; 6153c0e3abdSOrson Zhai }; 6163c0e3abdSOrson Zhai }; 6173c0e3abdSOrson Zhai }; 6181a9e7796SSuzuki K Poulose }; 6193c0e3abdSOrson Zhai 6203c0e3abdSOrson Zhai etm@11840000 { 6213c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6223c0e3abdSOrson Zhai reg = <0 0x11840000 0 0x1000>; 6233c0e3abdSOrson Zhai cpu = <&CPU4>; 6243c0e3abdSOrson Zhai clocks = <&ext_26m>; 6253c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6263c0e3abdSOrson Zhai 6271a9e7796SSuzuki K Poulose out-ports { 6283c0e3abdSOrson Zhai port { 6293c0e3abdSOrson Zhai etm4_out: endpoint { 6303c0e3abdSOrson Zhai remote-endpoint = 6313c0e3abdSOrson Zhai <&cluster1_funnel_in_port0>; 6323c0e3abdSOrson Zhai }; 6333c0e3abdSOrson Zhai }; 6343c0e3abdSOrson Zhai }; 6351a9e7796SSuzuki K Poulose }; 6363c0e3abdSOrson Zhai 6373c0e3abdSOrson Zhai etm@11940000 { 6383c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6393c0e3abdSOrson Zhai reg = <0 0x11940000 0 0x1000>; 6403c0e3abdSOrson Zhai cpu = <&CPU5>; 6413c0e3abdSOrson Zhai clocks = <&ext_26m>; 6423c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6433c0e3abdSOrson Zhai 6441a9e7796SSuzuki K Poulose out-ports { 6453c0e3abdSOrson Zhai port { 6463c0e3abdSOrson Zhai etm5_out: endpoint { 6473c0e3abdSOrson Zhai remote-endpoint = 6483c0e3abdSOrson Zhai <&cluster1_funnel_in_port1>; 6493c0e3abdSOrson Zhai }; 6503c0e3abdSOrson Zhai }; 6513c0e3abdSOrson Zhai }; 6521a9e7796SSuzuki K Poulose }; 6533c0e3abdSOrson Zhai 6543c0e3abdSOrson Zhai etm@11a40000 { 6553c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6563c0e3abdSOrson Zhai reg = <0 0x11a40000 0 0x1000>; 6573c0e3abdSOrson Zhai cpu = <&CPU6>; 6583c0e3abdSOrson Zhai clocks = <&ext_26m>; 6593c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6603c0e3abdSOrson Zhai 6611a9e7796SSuzuki K Poulose out-ports { 6623c0e3abdSOrson Zhai port { 6633c0e3abdSOrson Zhai etm6_out: endpoint { 6643c0e3abdSOrson Zhai remote-endpoint = 6653c0e3abdSOrson Zhai <&cluster1_funnel_in_port2>; 6663c0e3abdSOrson Zhai }; 6673c0e3abdSOrson Zhai }; 6683c0e3abdSOrson Zhai }; 6691a9e7796SSuzuki K Poulose }; 6703c0e3abdSOrson Zhai 6713c0e3abdSOrson Zhai etm@11b40000 { 6723c0e3abdSOrson Zhai compatible = "arm,coresight-etm4x", "arm,primecell"; 6733c0e3abdSOrson Zhai reg = <0 0x11b40000 0 0x1000>; 6743c0e3abdSOrson Zhai cpu = <&CPU7>; 6753c0e3abdSOrson Zhai clocks = <&ext_26m>; 6763c0e3abdSOrson Zhai clock-names = "apb_pclk"; 6773c0e3abdSOrson Zhai 6781a9e7796SSuzuki K Poulose out-ports { 6793c0e3abdSOrson Zhai port { 6803c0e3abdSOrson Zhai etm7_out: endpoint { 6813c0e3abdSOrson Zhai remote-endpoint = 6823c0e3abdSOrson Zhai <&cluster1_funnel_in_port3>; 6833c0e3abdSOrson Zhai }; 6843c0e3abdSOrson Zhai }; 6853c0e3abdSOrson Zhai }; 6861a9e7796SSuzuki K Poulose }; 6871cea2c22SBaolin Wang 6881cea2c22SBaolin Wang gpio-keys { 6891cea2c22SBaolin Wang compatible = "gpio-keys"; 6901cea2c22SBaolin Wang 6911cea2c22SBaolin Wang key-volumedown { 6921cea2c22SBaolin Wang label = "Volume Down Key"; 6931cea2c22SBaolin Wang linux,code = <KEY_VOLUMEDOWN>; 6941cea2c22SBaolin Wang gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; 6951cea2c22SBaolin Wang debounce-interval = <2>; 6961cea2c22SBaolin Wang wakeup-source; 6971cea2c22SBaolin Wang }; 6981cea2c22SBaolin Wang 6991cea2c22SBaolin Wang key-volumeup { 7001cea2c22SBaolin Wang label = "Volume Up Key"; 7011cea2c22SBaolin Wang linux,code = <KEY_VOLUMEUP>; 7021cea2c22SBaolin Wang gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; 7031cea2c22SBaolin Wang debounce-interval = <2>; 7041cea2c22SBaolin Wang wakeup-source; 7051cea2c22SBaolin Wang }; 7061cea2c22SBaolin Wang 7071cea2c22SBaolin Wang key-power { 7081cea2c22SBaolin Wang label = "Power Key"; 7091cea2c22SBaolin Wang linux,code = <KEY_POWER>; 7101cea2c22SBaolin Wang gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; 7111cea2c22SBaolin Wang debounce-interval = <2>; 7121cea2c22SBaolin Wang wakeup-source; 7131cea2c22SBaolin Wang }; 7141cea2c22SBaolin Wang }; 7153c0e3abdSOrson Zhai }; 7163c0e3abdSOrson Zhai}; 717