1c28adcb5SMasahiro Yamada/* 2c28adcb5SMasahiro Yamada * Device Tree Source for UniPhier PXs3 SoC 3c28adcb5SMasahiro Yamada * 4c28adcb5SMasahiro Yamada * Copyright (C) 2017 Socionext Inc. 5c28adcb5SMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6c28adcb5SMasahiro Yamada * 7c28adcb5SMasahiro Yamada * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8c28adcb5SMasahiro Yamada */ 9c28adcb5SMasahiro Yamada 10c28adcb5SMasahiro Yamada/memreserve/ 0x80000000 0x02000000; 11c28adcb5SMasahiro Yamada 12c28adcb5SMasahiro Yamada/ { 13c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3"; 14c28adcb5SMasahiro Yamada #address-cells = <2>; 15c28adcb5SMasahiro Yamada #size-cells = <2>; 16c28adcb5SMasahiro Yamada interrupt-parent = <&gic>; 17c28adcb5SMasahiro Yamada 18c28adcb5SMasahiro Yamada cpus { 19c28adcb5SMasahiro Yamada #address-cells = <2>; 20c28adcb5SMasahiro Yamada #size-cells = <0>; 21c28adcb5SMasahiro Yamada 22c28adcb5SMasahiro Yamada cpu-map { 23c28adcb5SMasahiro Yamada cluster0 { 24c28adcb5SMasahiro Yamada core0 { 25c28adcb5SMasahiro Yamada cpu = <&cpu0>; 26c28adcb5SMasahiro Yamada }; 27c28adcb5SMasahiro Yamada core1 { 28c28adcb5SMasahiro Yamada cpu = <&cpu1>; 29c28adcb5SMasahiro Yamada }; 30c28adcb5SMasahiro Yamada core2 { 31c28adcb5SMasahiro Yamada cpu = <&cpu2>; 32c28adcb5SMasahiro Yamada }; 33c28adcb5SMasahiro Yamada core3 { 34c28adcb5SMasahiro Yamada cpu = <&cpu3>; 35c28adcb5SMasahiro Yamada }; 36c28adcb5SMasahiro Yamada }; 37c28adcb5SMasahiro Yamada }; 38c28adcb5SMasahiro Yamada 39c28adcb5SMasahiro Yamada cpu0: cpu@0 { 40c28adcb5SMasahiro Yamada device_type = "cpu"; 41c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 42c28adcb5SMasahiro Yamada reg = <0 0x000>; 43c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 44c28adcb5SMasahiro Yamada enable-method = "psci"; 45c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 46c28adcb5SMasahiro Yamada }; 47c28adcb5SMasahiro Yamada 48c28adcb5SMasahiro Yamada cpu1: cpu@1 { 49c28adcb5SMasahiro Yamada device_type = "cpu"; 50c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 51c28adcb5SMasahiro Yamada reg = <0 0x001>; 52c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 53c28adcb5SMasahiro Yamada enable-method = "psci"; 54c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 55c28adcb5SMasahiro Yamada }; 56c28adcb5SMasahiro Yamada 57c28adcb5SMasahiro Yamada cpu2: cpu@2 { 58c28adcb5SMasahiro Yamada device_type = "cpu"; 59c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 60c28adcb5SMasahiro Yamada reg = <0 0x002>; 61c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 62c28adcb5SMasahiro Yamada enable-method = "psci"; 63c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 64c28adcb5SMasahiro Yamada }; 65c28adcb5SMasahiro Yamada 66c28adcb5SMasahiro Yamada cpu3: cpu@3 { 67c28adcb5SMasahiro Yamada device_type = "cpu"; 68c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 69c28adcb5SMasahiro Yamada reg = <0 0x003>; 70c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 71c28adcb5SMasahiro Yamada enable-method = "psci"; 72c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 73c28adcb5SMasahiro Yamada }; 74c28adcb5SMasahiro Yamada }; 75c28adcb5SMasahiro Yamada 76c28adcb5SMasahiro Yamada cluster0_opp: opp_table { 77c28adcb5SMasahiro Yamada compatible = "operating-points-v2"; 78c28adcb5SMasahiro Yamada opp-shared; 79c28adcb5SMasahiro Yamada 80c28adcb5SMasahiro Yamada opp-250000000 { 81c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 82c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 83c28adcb5SMasahiro Yamada }; 84c28adcb5SMasahiro Yamada opp-325000000 { 85c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <325000000>; 86c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 87c28adcb5SMasahiro Yamada }; 88c28adcb5SMasahiro Yamada opp-500000000 { 89c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 90c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 91c28adcb5SMasahiro Yamada }; 92c28adcb5SMasahiro Yamada opp-650000000 { 93c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <650000000>; 94c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 95c28adcb5SMasahiro Yamada }; 96c28adcb5SMasahiro Yamada opp-666667000 { 97c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 98c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 99c28adcb5SMasahiro Yamada }; 100c28adcb5SMasahiro Yamada opp-866667000 { 101c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <866667000>; 102c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 103c28adcb5SMasahiro Yamada }; 104c28adcb5SMasahiro Yamada opp-1000000000 { 105c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 106c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 107c28adcb5SMasahiro Yamada }; 108c28adcb5SMasahiro Yamada opp-1300000000 { 109c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1300000000>; 110c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 111c28adcb5SMasahiro Yamada }; 112c28adcb5SMasahiro Yamada }; 113c28adcb5SMasahiro Yamada 114c28adcb5SMasahiro Yamada psci { 115c28adcb5SMasahiro Yamada compatible = "arm,psci-1.0"; 116c28adcb5SMasahiro Yamada method = "smc"; 117c28adcb5SMasahiro Yamada }; 118c28adcb5SMasahiro Yamada 119c28adcb5SMasahiro Yamada clocks { 120c28adcb5SMasahiro Yamada refclk: ref { 121c28adcb5SMasahiro Yamada compatible = "fixed-clock"; 122c28adcb5SMasahiro Yamada #clock-cells = <0>; 123c28adcb5SMasahiro Yamada clock-frequency = <25000000>; 124c28adcb5SMasahiro Yamada }; 125c28adcb5SMasahiro Yamada }; 126c28adcb5SMasahiro Yamada 127c28adcb5SMasahiro Yamada timer { 128c28adcb5SMasahiro Yamada compatible = "arm,armv8-timer"; 129c28adcb5SMasahiro Yamada interrupts = <1 13 4>, 130c28adcb5SMasahiro Yamada <1 14 4>, 131c28adcb5SMasahiro Yamada <1 11 4>, 132c28adcb5SMasahiro Yamada <1 10 4>; 133c28adcb5SMasahiro Yamada }; 134c28adcb5SMasahiro Yamada 135c28adcb5SMasahiro Yamada soc@0 { 136c28adcb5SMasahiro Yamada compatible = "simple-bus"; 137c28adcb5SMasahiro Yamada #address-cells = <1>; 138c28adcb5SMasahiro Yamada #size-cells = <1>; 139c28adcb5SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 140c28adcb5SMasahiro Yamada 141c28adcb5SMasahiro Yamada serial0: serial@54006800 { 142c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 143c28adcb5SMasahiro Yamada status = "disabled"; 144c28adcb5SMasahiro Yamada reg = <0x54006800 0x40>; 145c28adcb5SMasahiro Yamada interrupts = <0 33 4>; 146c28adcb5SMasahiro Yamada pinctrl-names = "default"; 147c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 148c28adcb5SMasahiro Yamada clocks = <&peri_clk 0>; 149c28adcb5SMasahiro Yamada }; 150c28adcb5SMasahiro Yamada 151c28adcb5SMasahiro Yamada serial1: serial@54006900 { 152c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 153c28adcb5SMasahiro Yamada status = "disabled"; 154c28adcb5SMasahiro Yamada reg = <0x54006900 0x40>; 155c28adcb5SMasahiro Yamada interrupts = <0 35 4>; 156c28adcb5SMasahiro Yamada pinctrl-names = "default"; 157c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 158c28adcb5SMasahiro Yamada clocks = <&peri_clk 1>; 159c28adcb5SMasahiro Yamada }; 160c28adcb5SMasahiro Yamada 161c28adcb5SMasahiro Yamada serial2: serial@54006a00 { 162c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 163c28adcb5SMasahiro Yamada status = "disabled"; 164c28adcb5SMasahiro Yamada reg = <0x54006a00 0x40>; 165c28adcb5SMasahiro Yamada interrupts = <0 37 4>; 166c28adcb5SMasahiro Yamada pinctrl-names = "default"; 167c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 168c28adcb5SMasahiro Yamada clocks = <&peri_clk 2>; 169c28adcb5SMasahiro Yamada }; 170c28adcb5SMasahiro Yamada 171c28adcb5SMasahiro Yamada serial3: serial@54006b00 { 172c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 173c28adcb5SMasahiro Yamada status = "disabled"; 174c28adcb5SMasahiro Yamada reg = <0x54006b00 0x40>; 175c28adcb5SMasahiro Yamada interrupts = <0 177 4>; 176c28adcb5SMasahiro Yamada pinctrl-names = "default"; 177c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 178c28adcb5SMasahiro Yamada clocks = <&peri_clk 3>; 179c28adcb5SMasahiro Yamada }; 180c28adcb5SMasahiro Yamada 181c28adcb5SMasahiro Yamada i2c0: i2c@58780000 { 182c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 183c28adcb5SMasahiro Yamada status = "disabled"; 184c28adcb5SMasahiro Yamada reg = <0x58780000 0x80>; 185c28adcb5SMasahiro Yamada #address-cells = <1>; 186c28adcb5SMasahiro Yamada #size-cells = <0>; 187c28adcb5SMasahiro Yamada interrupts = <0 41 4>; 188c28adcb5SMasahiro Yamada pinctrl-names = "default"; 189c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 190c28adcb5SMasahiro Yamada clocks = <&peri_clk 4>; 191c28adcb5SMasahiro Yamada clock-frequency = <100000>; 192c28adcb5SMasahiro Yamada }; 193c28adcb5SMasahiro Yamada 194c28adcb5SMasahiro Yamada i2c1: i2c@58781000 { 195c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 196c28adcb5SMasahiro Yamada status = "disabled"; 197c28adcb5SMasahiro Yamada reg = <0x58781000 0x80>; 198c28adcb5SMasahiro Yamada #address-cells = <1>; 199c28adcb5SMasahiro Yamada #size-cells = <0>; 200c28adcb5SMasahiro Yamada interrupts = <0 42 4>; 201c28adcb5SMasahiro Yamada pinctrl-names = "default"; 202c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 203c28adcb5SMasahiro Yamada clocks = <&peri_clk 5>; 204c28adcb5SMasahiro Yamada clock-frequency = <100000>; 205c28adcb5SMasahiro Yamada }; 206c28adcb5SMasahiro Yamada 207c28adcb5SMasahiro Yamada i2c2: i2c@58782000 { 208c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 209c28adcb5SMasahiro Yamada status = "disabled"; 210c28adcb5SMasahiro Yamada reg = <0x58782000 0x80>; 211c28adcb5SMasahiro Yamada #address-cells = <1>; 212c28adcb5SMasahiro Yamada #size-cells = <0>; 213c28adcb5SMasahiro Yamada interrupts = <0 43 4>; 214c28adcb5SMasahiro Yamada pinctrl-names = "default"; 215c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c2>; 216c28adcb5SMasahiro Yamada clocks = <&peri_clk 6>; 217c28adcb5SMasahiro Yamada clock-frequency = <100000>; 218c28adcb5SMasahiro Yamada }; 219c28adcb5SMasahiro Yamada 220c28adcb5SMasahiro Yamada i2c3: i2c@58783000 { 221c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 222c28adcb5SMasahiro Yamada status = "disabled"; 223c28adcb5SMasahiro Yamada reg = <0x58783000 0x80>; 224c28adcb5SMasahiro Yamada #address-cells = <1>; 225c28adcb5SMasahiro Yamada #size-cells = <0>; 226c28adcb5SMasahiro Yamada interrupts = <0 44 4>; 227c28adcb5SMasahiro Yamada pinctrl-names = "default"; 228c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 229c28adcb5SMasahiro Yamada clocks = <&peri_clk 7>; 230c28adcb5SMasahiro Yamada clock-frequency = <100000>; 231c28adcb5SMasahiro Yamada }; 232c28adcb5SMasahiro Yamada 233c28adcb5SMasahiro Yamada /* chip-internal connection for HDMI */ 234c28adcb5SMasahiro Yamada i2c6: i2c@58786000 { 235c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 236c28adcb5SMasahiro Yamada reg = <0x58786000 0x80>; 237c28adcb5SMasahiro Yamada #address-cells = <1>; 238c28adcb5SMasahiro Yamada #size-cells = <0>; 239c28adcb5SMasahiro Yamada interrupts = <0 26 4>; 240c28adcb5SMasahiro Yamada clocks = <&peri_clk 10>; 241c28adcb5SMasahiro Yamada clock-frequency = <400000>; 242c28adcb5SMasahiro Yamada }; 243c28adcb5SMasahiro Yamada 244c28adcb5SMasahiro Yamada system_bus: system-bus@58c00000 { 245c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 246c28adcb5SMasahiro Yamada status = "disabled"; 247c28adcb5SMasahiro Yamada reg = <0x58c00000 0x400>; 248c28adcb5SMasahiro Yamada #address-cells = <2>; 249c28adcb5SMasahiro Yamada #size-cells = <1>; 250c28adcb5SMasahiro Yamada pinctrl-names = "default"; 251c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 252c28adcb5SMasahiro Yamada }; 253c28adcb5SMasahiro Yamada 254c28adcb5SMasahiro Yamada smpctrl@59801000 { 255c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 256c28adcb5SMasahiro Yamada reg = <0x59801000 0x400>; 257c28adcb5SMasahiro Yamada }; 258c28adcb5SMasahiro Yamada 259c28adcb5SMasahiro Yamada sdctrl@59810000 { 260c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sdctrl", 261c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 262c28adcb5SMasahiro Yamada reg = <0x59810000 0x400>; 263c28adcb5SMasahiro Yamada 264c28adcb5SMasahiro Yamada sd_clk: clock { 265c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-clock"; 266c28adcb5SMasahiro Yamada #clock-cells = <1>; 267c28adcb5SMasahiro Yamada }; 268c28adcb5SMasahiro Yamada 269c28adcb5SMasahiro Yamada sd_rst: reset { 270c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-reset"; 271c28adcb5SMasahiro Yamada #reset-cells = <1>; 272c28adcb5SMasahiro Yamada }; 273c28adcb5SMasahiro Yamada }; 274c28adcb5SMasahiro Yamada 275c28adcb5SMasahiro Yamada perictrl@59820000 { 276c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-perictrl", 277c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 278c28adcb5SMasahiro Yamada reg = <0x59820000 0x200>; 279c28adcb5SMasahiro Yamada 280c28adcb5SMasahiro Yamada peri_clk: clock { 281c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-clock"; 282c28adcb5SMasahiro Yamada #clock-cells = <1>; 283c28adcb5SMasahiro Yamada }; 284c28adcb5SMasahiro Yamada 285c28adcb5SMasahiro Yamada peri_rst: reset { 286c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-reset"; 287c28adcb5SMasahiro Yamada #reset-cells = <1>; 288c28adcb5SMasahiro Yamada }; 289c28adcb5SMasahiro Yamada }; 290c28adcb5SMasahiro Yamada 291c28adcb5SMasahiro Yamada emmc: sdhc@5a000000 { 292c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 293c28adcb5SMasahiro Yamada reg = <0x5a000000 0x400>; 294c28adcb5SMasahiro Yamada interrupts = <0 78 4>; 295c28adcb5SMasahiro Yamada pinctrl-names = "default"; 296c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 297c28adcb5SMasahiro Yamada clocks = <&sys_clk 4>; 298c28adcb5SMasahiro Yamada bus-width = <8>; 299c28adcb5SMasahiro Yamada mmc-ddr-1_8v; 300c28adcb5SMasahiro Yamada mmc-hs200-1_8v; 301c28adcb5SMasahiro Yamada cdns,phy-input-delay-legacy = <4>; 302c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 303c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 304c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 305c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 306c28adcb5SMasahiro Yamada }; 307c28adcb5SMasahiro Yamada 308c28adcb5SMasahiro Yamada soc-glue@5f800000 { 309c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-soc-glue", 310c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 311c28adcb5SMasahiro Yamada reg = <0x5f800000 0x2000>; 312c28adcb5SMasahiro Yamada 313c28adcb5SMasahiro Yamada pinctrl: pinctrl { 314c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-pinctrl"; 315c28adcb5SMasahiro Yamada }; 316c28adcb5SMasahiro Yamada }; 317c28adcb5SMasahiro Yamada 318c28adcb5SMasahiro Yamada aidet: aidet@5fc20000 { 319c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-aidet"; 320c28adcb5SMasahiro Yamada reg = <0x5fc20000 0x200>; 321c28adcb5SMasahiro Yamada interrupt-controller; 322c28adcb5SMasahiro Yamada #interrupt-cells = <2>; 323c28adcb5SMasahiro Yamada }; 324c28adcb5SMasahiro Yamada 325c28adcb5SMasahiro Yamada gic: interrupt-controller@5fe00000 { 326c28adcb5SMasahiro Yamada compatible = "arm,gic-v3"; 327c28adcb5SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 328c28adcb5SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 329c28adcb5SMasahiro Yamada interrupt-controller; 330c28adcb5SMasahiro Yamada #interrupt-cells = <3>; 331c28adcb5SMasahiro Yamada interrupts = <1 9 4>; 332c28adcb5SMasahiro Yamada }; 333c28adcb5SMasahiro Yamada 334c28adcb5SMasahiro Yamada sysctrl@61840000 { 335c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sysctrl", 336c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 337c28adcb5SMasahiro Yamada reg = <0x61840000 0x10000>; 338c28adcb5SMasahiro Yamada 339c28adcb5SMasahiro Yamada sys_clk: clock { 340c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-clock"; 341c28adcb5SMasahiro Yamada #clock-cells = <1>; 342c28adcb5SMasahiro Yamada }; 343c28adcb5SMasahiro Yamada 344c28adcb5SMasahiro Yamada sys_rst: reset { 345c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-reset"; 346c28adcb5SMasahiro Yamada #reset-cells = <1>; 347c28adcb5SMasahiro Yamada }; 348c28adcb5SMasahiro Yamada 349c28adcb5SMasahiro Yamada watchdog { 350c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-wdt"; 351c28adcb5SMasahiro Yamada }; 352c28adcb5SMasahiro Yamada }; 353c28adcb5SMasahiro Yamada 354c28adcb5SMasahiro Yamada nand: nand@68000000 { 355c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 356c28adcb5SMasahiro Yamada status = "disabled"; 357c28adcb5SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 358c28adcb5SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 359c28adcb5SMasahiro Yamada interrupts = <0 65 4>; 360c28adcb5SMasahiro Yamada pinctrl-names = "default"; 361c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 362c28adcb5SMasahiro Yamada clocks = <&sys_clk 2>; 363c28adcb5SMasahiro Yamada }; 364c28adcb5SMasahiro Yamada }; 365c28adcb5SMasahiro Yamada}; 366c28adcb5SMasahiro Yamada 367c28adcb5SMasahiro Yamada#include "uniphier-pinctrl.dtsi" 368