105f7e3d1SMasahiro Yamada// SPDX-License-Identifier: GPL-2.0+ OR MIT 205f7e3d1SMasahiro Yamada// 305f7e3d1SMasahiro Yamada// Device Tree Source for UniPhier PXs3 SoC 405f7e3d1SMasahiro Yamada// 505f7e3d1SMasahiro Yamada// Copyright (C) 2017 Socionext Inc. 605f7e3d1SMasahiro Yamada// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7c28adcb5SMasahiro Yamada 8b6e5ec20SMasahiro Yamada#include <dt-bindings/gpio/gpio.h> 98311ca57SMasahiro Yamada#include <dt-bindings/gpio/uniphier-gpio.h> 10b6e5ec20SMasahiro Yamada 11c28adcb5SMasahiro Yamada/memreserve/ 0x80000000 0x02000000; 12c28adcb5SMasahiro Yamada 13c28adcb5SMasahiro Yamada/ { 14c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3"; 15c28adcb5SMasahiro Yamada #address-cells = <2>; 16c28adcb5SMasahiro Yamada #size-cells = <2>; 17c28adcb5SMasahiro Yamada interrupt-parent = <&gic>; 18c28adcb5SMasahiro Yamada 19c28adcb5SMasahiro Yamada cpus { 20c28adcb5SMasahiro Yamada #address-cells = <2>; 21c28adcb5SMasahiro Yamada #size-cells = <0>; 22c28adcb5SMasahiro Yamada 23c28adcb5SMasahiro Yamada cpu-map { 24c28adcb5SMasahiro Yamada cluster0 { 25c28adcb5SMasahiro Yamada core0 { 26c28adcb5SMasahiro Yamada cpu = <&cpu0>; 27c28adcb5SMasahiro Yamada }; 28c28adcb5SMasahiro Yamada core1 { 29c28adcb5SMasahiro Yamada cpu = <&cpu1>; 30c28adcb5SMasahiro Yamada }; 31c28adcb5SMasahiro Yamada core2 { 32c28adcb5SMasahiro Yamada cpu = <&cpu2>; 33c28adcb5SMasahiro Yamada }; 34c28adcb5SMasahiro Yamada core3 { 35c28adcb5SMasahiro Yamada cpu = <&cpu3>; 36c28adcb5SMasahiro Yamada }; 37c28adcb5SMasahiro Yamada }; 38c28adcb5SMasahiro Yamada }; 39c28adcb5SMasahiro Yamada 40c28adcb5SMasahiro Yamada cpu0: cpu@0 { 41c28adcb5SMasahiro Yamada device_type = "cpu"; 42c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 43c28adcb5SMasahiro Yamada reg = <0 0x000>; 44c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 45c28adcb5SMasahiro Yamada enable-method = "psci"; 46c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 47c28adcb5SMasahiro Yamada }; 48c28adcb5SMasahiro Yamada 49c28adcb5SMasahiro Yamada cpu1: cpu@1 { 50c28adcb5SMasahiro Yamada device_type = "cpu"; 51c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 52c28adcb5SMasahiro Yamada reg = <0 0x001>; 53c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 54c28adcb5SMasahiro Yamada enable-method = "psci"; 55c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 56c28adcb5SMasahiro Yamada }; 57c28adcb5SMasahiro Yamada 58c28adcb5SMasahiro Yamada cpu2: cpu@2 { 59c28adcb5SMasahiro Yamada device_type = "cpu"; 60c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 61c28adcb5SMasahiro Yamada reg = <0 0x002>; 62c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 63c28adcb5SMasahiro Yamada enable-method = "psci"; 64c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 65c28adcb5SMasahiro Yamada }; 66c28adcb5SMasahiro Yamada 67c28adcb5SMasahiro Yamada cpu3: cpu@3 { 68c28adcb5SMasahiro Yamada device_type = "cpu"; 69c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 70c28adcb5SMasahiro Yamada reg = <0 0x003>; 71c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 72c28adcb5SMasahiro Yamada enable-method = "psci"; 73c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 74c28adcb5SMasahiro Yamada }; 75c28adcb5SMasahiro Yamada }; 76c28adcb5SMasahiro Yamada 779cd7d03fSMasahiro Yamada cluster0_opp: opp-table { 78c28adcb5SMasahiro Yamada compatible = "operating-points-v2"; 79c28adcb5SMasahiro Yamada opp-shared; 80c28adcb5SMasahiro Yamada 81c28adcb5SMasahiro Yamada opp-250000000 { 82c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 83c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 84c28adcb5SMasahiro Yamada }; 85c28adcb5SMasahiro Yamada opp-325000000 { 86c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <325000000>; 87c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 88c28adcb5SMasahiro Yamada }; 89c28adcb5SMasahiro Yamada opp-500000000 { 90c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 91c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 92c28adcb5SMasahiro Yamada }; 93c28adcb5SMasahiro Yamada opp-650000000 { 94c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <650000000>; 95c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 96c28adcb5SMasahiro Yamada }; 97c28adcb5SMasahiro Yamada opp-666667000 { 98c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 99c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 100c28adcb5SMasahiro Yamada }; 101c28adcb5SMasahiro Yamada opp-866667000 { 102c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <866667000>; 103c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 104c28adcb5SMasahiro Yamada }; 105c28adcb5SMasahiro Yamada opp-1000000000 { 106c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 107c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 108c28adcb5SMasahiro Yamada }; 109c28adcb5SMasahiro Yamada opp-1300000000 { 110c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1300000000>; 111c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 112c28adcb5SMasahiro Yamada }; 113c28adcb5SMasahiro Yamada }; 114c28adcb5SMasahiro Yamada 115c28adcb5SMasahiro Yamada psci { 116c28adcb5SMasahiro Yamada compatible = "arm,psci-1.0"; 117c28adcb5SMasahiro Yamada method = "smc"; 118c28adcb5SMasahiro Yamada }; 119c28adcb5SMasahiro Yamada 120c28adcb5SMasahiro Yamada clocks { 121c28adcb5SMasahiro Yamada refclk: ref { 122c28adcb5SMasahiro Yamada compatible = "fixed-clock"; 123c28adcb5SMasahiro Yamada #clock-cells = <0>; 124c28adcb5SMasahiro Yamada clock-frequency = <25000000>; 125c28adcb5SMasahiro Yamada }; 126c28adcb5SMasahiro Yamada }; 127c28adcb5SMasahiro Yamada 128b6e5ec20SMasahiro Yamada emmc_pwrseq: emmc-pwrseq { 129b6e5ec20SMasahiro Yamada compatible = "mmc-pwrseq-emmc"; 1308311ca57SMasahiro Yamada reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 131b6e5ec20SMasahiro Yamada }; 132b6e5ec20SMasahiro Yamada 133c28adcb5SMasahiro Yamada timer { 134c28adcb5SMasahiro Yamada compatible = "arm,armv8-timer"; 135c28adcb5SMasahiro Yamada interrupts = <1 13 4>, 136c28adcb5SMasahiro Yamada <1 14 4>, 137c28adcb5SMasahiro Yamada <1 11 4>, 138c28adcb5SMasahiro Yamada <1 10 4>; 139c28adcb5SMasahiro Yamada }; 140c28adcb5SMasahiro Yamada 141c28adcb5SMasahiro Yamada soc@0 { 142c28adcb5SMasahiro Yamada compatible = "simple-bus"; 143c28adcb5SMasahiro Yamada #address-cells = <1>; 144c28adcb5SMasahiro Yamada #size-cells = <1>; 145c28adcb5SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 146c28adcb5SMasahiro Yamada 147c28adcb5SMasahiro Yamada serial0: serial@54006800 { 148c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 149c28adcb5SMasahiro Yamada status = "disabled"; 150c28adcb5SMasahiro Yamada reg = <0x54006800 0x40>; 151c28adcb5SMasahiro Yamada interrupts = <0 33 4>; 152c28adcb5SMasahiro Yamada pinctrl-names = "default"; 153c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 154c28adcb5SMasahiro Yamada clocks = <&peri_clk 0>; 15576c48e1eSMasahiro Yamada resets = <&peri_rst 0>; 156c28adcb5SMasahiro Yamada }; 157c28adcb5SMasahiro Yamada 158c28adcb5SMasahiro Yamada serial1: serial@54006900 { 159c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 160c28adcb5SMasahiro Yamada status = "disabled"; 161c28adcb5SMasahiro Yamada reg = <0x54006900 0x40>; 162c28adcb5SMasahiro Yamada interrupts = <0 35 4>; 163c28adcb5SMasahiro Yamada pinctrl-names = "default"; 164c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 165c28adcb5SMasahiro Yamada clocks = <&peri_clk 1>; 16676c48e1eSMasahiro Yamada resets = <&peri_rst 1>; 167c28adcb5SMasahiro Yamada }; 168c28adcb5SMasahiro Yamada 169c28adcb5SMasahiro Yamada serial2: serial@54006a00 { 170c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 171c28adcb5SMasahiro Yamada status = "disabled"; 172c28adcb5SMasahiro Yamada reg = <0x54006a00 0x40>; 173c28adcb5SMasahiro Yamada interrupts = <0 37 4>; 174c28adcb5SMasahiro Yamada pinctrl-names = "default"; 175c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 176c28adcb5SMasahiro Yamada clocks = <&peri_clk 2>; 17776c48e1eSMasahiro Yamada resets = <&peri_rst 2>; 178c28adcb5SMasahiro Yamada }; 179c28adcb5SMasahiro Yamada 180c28adcb5SMasahiro Yamada serial3: serial@54006b00 { 181c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 182c28adcb5SMasahiro Yamada status = "disabled"; 183c28adcb5SMasahiro Yamada reg = <0x54006b00 0x40>; 184c28adcb5SMasahiro Yamada interrupts = <0 177 4>; 185c28adcb5SMasahiro Yamada pinctrl-names = "default"; 186c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 187c28adcb5SMasahiro Yamada clocks = <&peri_clk 3>; 18876c48e1eSMasahiro Yamada resets = <&peri_rst 3>; 189c28adcb5SMasahiro Yamada }; 190c28adcb5SMasahiro Yamada 191277b51e7SMasahiro Yamada gpio: gpio@55000000 { 192277b51e7SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 193277b51e7SMasahiro Yamada reg = <0x55000000 0x200>; 194277b51e7SMasahiro Yamada interrupt-parent = <&aidet>; 195277b51e7SMasahiro Yamada interrupt-controller; 196277b51e7SMasahiro Yamada #interrupt-cells = <2>; 197277b51e7SMasahiro Yamada gpio-controller; 198277b51e7SMasahiro Yamada #gpio-cells = <2>; 199277b51e7SMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 200abb62c46SMasahiro Yamada <&pinctrl 104 0 0>, 201abb62c46SMasahiro Yamada <&pinctrl 168 0 0>; 202277b51e7SMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 203277b51e7SMasahiro Yamada "gpio_range1", 204277b51e7SMasahiro Yamada "gpio_range2"; 205277b51e7SMasahiro Yamada ngpios = <286>; 206277b51e7SMasahiro Yamada socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 207277b51e7SMasahiro Yamada <21 217 3>; 208277b51e7SMasahiro Yamada }; 209277b51e7SMasahiro Yamada 210c28adcb5SMasahiro Yamada i2c0: i2c@58780000 { 211c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 212c28adcb5SMasahiro Yamada status = "disabled"; 213c28adcb5SMasahiro Yamada reg = <0x58780000 0x80>; 214c28adcb5SMasahiro Yamada #address-cells = <1>; 215c28adcb5SMasahiro Yamada #size-cells = <0>; 216c28adcb5SMasahiro Yamada interrupts = <0 41 4>; 217c28adcb5SMasahiro Yamada pinctrl-names = "default"; 218c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 219c28adcb5SMasahiro Yamada clocks = <&peri_clk 4>; 22076c48e1eSMasahiro Yamada resets = <&peri_rst 4>; 221c28adcb5SMasahiro Yamada clock-frequency = <100000>; 222c28adcb5SMasahiro Yamada }; 223c28adcb5SMasahiro Yamada 224c28adcb5SMasahiro Yamada i2c1: i2c@58781000 { 225c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 226c28adcb5SMasahiro Yamada status = "disabled"; 227c28adcb5SMasahiro Yamada reg = <0x58781000 0x80>; 228c28adcb5SMasahiro Yamada #address-cells = <1>; 229c28adcb5SMasahiro Yamada #size-cells = <0>; 230c28adcb5SMasahiro Yamada interrupts = <0 42 4>; 231c28adcb5SMasahiro Yamada pinctrl-names = "default"; 232c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 233c28adcb5SMasahiro Yamada clocks = <&peri_clk 5>; 23476c48e1eSMasahiro Yamada resets = <&peri_rst 5>; 235c28adcb5SMasahiro Yamada clock-frequency = <100000>; 236c28adcb5SMasahiro Yamada }; 237c28adcb5SMasahiro Yamada 238c28adcb5SMasahiro Yamada i2c2: i2c@58782000 { 239c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 240c28adcb5SMasahiro Yamada status = "disabled"; 241c28adcb5SMasahiro Yamada reg = <0x58782000 0x80>; 242c28adcb5SMasahiro Yamada #address-cells = <1>; 243c28adcb5SMasahiro Yamada #size-cells = <0>; 244c28adcb5SMasahiro Yamada interrupts = <0 43 4>; 245c28adcb5SMasahiro Yamada pinctrl-names = "default"; 246c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c2>; 247c28adcb5SMasahiro Yamada clocks = <&peri_clk 6>; 24876c48e1eSMasahiro Yamada resets = <&peri_rst 6>; 249c28adcb5SMasahiro Yamada clock-frequency = <100000>; 250c28adcb5SMasahiro Yamada }; 251c28adcb5SMasahiro Yamada 252c28adcb5SMasahiro Yamada i2c3: i2c@58783000 { 253c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 254c28adcb5SMasahiro Yamada status = "disabled"; 255c28adcb5SMasahiro Yamada reg = <0x58783000 0x80>; 256c28adcb5SMasahiro Yamada #address-cells = <1>; 257c28adcb5SMasahiro Yamada #size-cells = <0>; 258c28adcb5SMasahiro Yamada interrupts = <0 44 4>; 259c28adcb5SMasahiro Yamada pinctrl-names = "default"; 260c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 261c28adcb5SMasahiro Yamada clocks = <&peri_clk 7>; 26276c48e1eSMasahiro Yamada resets = <&peri_rst 7>; 263c28adcb5SMasahiro Yamada clock-frequency = <100000>; 264c28adcb5SMasahiro Yamada }; 265c28adcb5SMasahiro Yamada 266c28adcb5SMasahiro Yamada /* chip-internal connection for HDMI */ 267c28adcb5SMasahiro Yamada i2c6: i2c@58786000 { 268c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 269c28adcb5SMasahiro Yamada reg = <0x58786000 0x80>; 270c28adcb5SMasahiro Yamada #address-cells = <1>; 271c28adcb5SMasahiro Yamada #size-cells = <0>; 272c28adcb5SMasahiro Yamada interrupts = <0 26 4>; 273c28adcb5SMasahiro Yamada clocks = <&peri_clk 10>; 27476c48e1eSMasahiro Yamada resets = <&peri_rst 10>; 275c28adcb5SMasahiro Yamada clock-frequency = <400000>; 276c28adcb5SMasahiro Yamada }; 277c28adcb5SMasahiro Yamada 278c28adcb5SMasahiro Yamada system_bus: system-bus@58c00000 { 279c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 280c28adcb5SMasahiro Yamada status = "disabled"; 281c28adcb5SMasahiro Yamada reg = <0x58c00000 0x400>; 282c28adcb5SMasahiro Yamada #address-cells = <2>; 283c28adcb5SMasahiro Yamada #size-cells = <1>; 284c28adcb5SMasahiro Yamada pinctrl-names = "default"; 285c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 286c28adcb5SMasahiro Yamada }; 287c28adcb5SMasahiro Yamada 288c28adcb5SMasahiro Yamada smpctrl@59801000 { 289c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 290c28adcb5SMasahiro Yamada reg = <0x59801000 0x400>; 291c28adcb5SMasahiro Yamada }; 292c28adcb5SMasahiro Yamada 293c28adcb5SMasahiro Yamada sdctrl@59810000 { 294c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sdctrl", 295c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 296c28adcb5SMasahiro Yamada reg = <0x59810000 0x400>; 297c28adcb5SMasahiro Yamada 298c28adcb5SMasahiro Yamada sd_clk: clock { 299c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-clock"; 300c28adcb5SMasahiro Yamada #clock-cells = <1>; 301c28adcb5SMasahiro Yamada }; 302c28adcb5SMasahiro Yamada 303c28adcb5SMasahiro Yamada sd_rst: reset { 304c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-reset"; 305c28adcb5SMasahiro Yamada #reset-cells = <1>; 306c28adcb5SMasahiro Yamada }; 307c28adcb5SMasahiro Yamada }; 308c28adcb5SMasahiro Yamada 309c28adcb5SMasahiro Yamada perictrl@59820000 { 310c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-perictrl", 311c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 312c28adcb5SMasahiro Yamada reg = <0x59820000 0x200>; 313c28adcb5SMasahiro Yamada 314c28adcb5SMasahiro Yamada peri_clk: clock { 315c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-clock"; 316c28adcb5SMasahiro Yamada #clock-cells = <1>; 317c28adcb5SMasahiro Yamada }; 318c28adcb5SMasahiro Yamada 319c28adcb5SMasahiro Yamada peri_rst: reset { 320c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-reset"; 321c28adcb5SMasahiro Yamada #reset-cells = <1>; 322c28adcb5SMasahiro Yamada }; 323c28adcb5SMasahiro Yamada }; 324c28adcb5SMasahiro Yamada 325c28adcb5SMasahiro Yamada emmc: sdhc@5a000000 { 326c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 327c28adcb5SMasahiro Yamada reg = <0x5a000000 0x400>; 328c28adcb5SMasahiro Yamada interrupts = <0 78 4>; 329c28adcb5SMasahiro Yamada pinctrl-names = "default"; 330c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 331c28adcb5SMasahiro Yamada clocks = <&sys_clk 4>; 33276c48e1eSMasahiro Yamada resets = <&sys_rst 4>; 333c28adcb5SMasahiro Yamada bus-width = <8>; 334c28adcb5SMasahiro Yamada mmc-ddr-1_8v; 335c28adcb5SMasahiro Yamada mmc-hs200-1_8v; 336b6e5ec20SMasahiro Yamada mmc-pwrseq = <&emmc_pwrseq>; 337c28adcb5SMasahiro Yamada cdns,phy-input-delay-legacy = <4>; 338c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 339c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 340c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 341c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 342c28adcb5SMasahiro Yamada }; 343c28adcb5SMasahiro Yamada 344c28adcb5SMasahiro Yamada soc-glue@5f800000 { 345c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-soc-glue", 346c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 347c28adcb5SMasahiro Yamada reg = <0x5f800000 0x2000>; 348c28adcb5SMasahiro Yamada 349c28adcb5SMasahiro Yamada pinctrl: pinctrl { 350c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-pinctrl"; 351c28adcb5SMasahiro Yamada }; 352c28adcb5SMasahiro Yamada }; 353c28adcb5SMasahiro Yamada 354f05851e1SKeiji Hayashibara soc-glue@5f900000 { 355f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-pxs3-soc-glue-debug", 356f05851e1SKeiji Hayashibara "simple-mfd"; 357f05851e1SKeiji Hayashibara #address-cells = <1>; 358f05851e1SKeiji Hayashibara #size-cells = <1>; 359f05851e1SKeiji Hayashibara ranges = <0 0x5f900000 0x2000>; 360f05851e1SKeiji Hayashibara 361f05851e1SKeiji Hayashibara efuse@100 { 362f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 363f05851e1SKeiji Hayashibara reg = <0x100 0x28>; 364f05851e1SKeiji Hayashibara }; 365f05851e1SKeiji Hayashibara 366f05851e1SKeiji Hayashibara efuse@200 { 367f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 368f05851e1SKeiji Hayashibara reg = <0x200 0x68>; 369f05851e1SKeiji Hayashibara }; 370f05851e1SKeiji Hayashibara }; 371f05851e1SKeiji Hayashibara 372c28adcb5SMasahiro Yamada aidet: aidet@5fc20000 { 373c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-aidet"; 374c28adcb5SMasahiro Yamada reg = <0x5fc20000 0x200>; 375c28adcb5SMasahiro Yamada interrupt-controller; 376c28adcb5SMasahiro Yamada #interrupt-cells = <2>; 377c28adcb5SMasahiro Yamada }; 378c28adcb5SMasahiro Yamada 379c28adcb5SMasahiro Yamada gic: interrupt-controller@5fe00000 { 380c28adcb5SMasahiro Yamada compatible = "arm,gic-v3"; 381c28adcb5SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 382c28adcb5SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 383c28adcb5SMasahiro Yamada interrupt-controller; 384c28adcb5SMasahiro Yamada #interrupt-cells = <3>; 385c28adcb5SMasahiro Yamada interrupts = <1 9 4>; 386c28adcb5SMasahiro Yamada }; 387c28adcb5SMasahiro Yamada 388c28adcb5SMasahiro Yamada sysctrl@61840000 { 389c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sysctrl", 390c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 391c28adcb5SMasahiro Yamada reg = <0x61840000 0x10000>; 392c28adcb5SMasahiro Yamada 393c28adcb5SMasahiro Yamada sys_clk: clock { 394c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-clock"; 395c28adcb5SMasahiro Yamada #clock-cells = <1>; 396c28adcb5SMasahiro Yamada }; 397c28adcb5SMasahiro Yamada 398c28adcb5SMasahiro Yamada sys_rst: reset { 399c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-reset"; 400c28adcb5SMasahiro Yamada #reset-cells = <1>; 401c28adcb5SMasahiro Yamada }; 402c28adcb5SMasahiro Yamada 403c28adcb5SMasahiro Yamada watchdog { 404c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-wdt"; 405c28adcb5SMasahiro Yamada }; 406c28adcb5SMasahiro Yamada }; 407c28adcb5SMasahiro Yamada 408aba054a1SKunihiko Hayashi eth0: ethernet@65000000 { 409aba054a1SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ave4"; 410aba054a1SKunihiko Hayashi status = "disabled"; 411aba054a1SKunihiko Hayashi reg = <0x65000000 0x8500>; 412aba054a1SKunihiko Hayashi interrupts = <0 66 4>; 413aba054a1SKunihiko Hayashi pinctrl-names = "default"; 414aba054a1SKunihiko Hayashi pinctrl-0 = <&pinctrl_ether_rgmii>; 415a34a464dSKunihiko Hayashi clock-names = "ether"; 416aba054a1SKunihiko Hayashi clocks = <&sys_clk 6>; 417a34a464dSKunihiko Hayashi reset-names = "ether"; 418aba054a1SKunihiko Hayashi resets = <&sys_rst 6>; 419aba054a1SKunihiko Hayashi phy-mode = "rgmii"; 420aba054a1SKunihiko Hayashi local-mac-address = [00 00 00 00 00 00]; 421aba054a1SKunihiko Hayashi 422aba054a1SKunihiko Hayashi mdio0: mdio { 423aba054a1SKunihiko Hayashi #address-cells = <1>; 424aba054a1SKunihiko Hayashi #size-cells = <0>; 425aba054a1SKunihiko Hayashi }; 426aba054a1SKunihiko Hayashi }; 427aba054a1SKunihiko Hayashi 428aba054a1SKunihiko Hayashi eth1: ethernet@65200000 { 429aba054a1SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ave4"; 430aba054a1SKunihiko Hayashi status = "disabled"; 431aba054a1SKunihiko Hayashi reg = <0x65200000 0x8500>; 432aba054a1SKunihiko Hayashi interrupts = <0 67 4>; 433aba054a1SKunihiko Hayashi pinctrl-names = "default"; 434aba054a1SKunihiko Hayashi pinctrl-0 = <&pinctrl_ether1_rgmii>; 435a34a464dSKunihiko Hayashi clock-names = "ether"; 436aba054a1SKunihiko Hayashi clocks = <&sys_clk 7>; 437a34a464dSKunihiko Hayashi reset-names = "ether"; 438aba054a1SKunihiko Hayashi resets = <&sys_rst 7>; 439aba054a1SKunihiko Hayashi phy-mode = "rgmii"; 440aba054a1SKunihiko Hayashi local-mac-address = [00 00 00 00 00 00]; 441aba054a1SKunihiko Hayashi 442aba054a1SKunihiko Hayashi mdio1: mdio { 443aba054a1SKunihiko Hayashi #address-cells = <1>; 444aba054a1SKunihiko Hayashi #size-cells = <0>; 445aba054a1SKunihiko Hayashi }; 446aba054a1SKunihiko Hayashi }; 447aba054a1SKunihiko Hayashi 448c28adcb5SMasahiro Yamada nand: nand@68000000 { 449c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 450c28adcb5SMasahiro Yamada status = "disabled"; 451c28adcb5SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 452c28adcb5SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 453c28adcb5SMasahiro Yamada interrupts = <0 65 4>; 454c28adcb5SMasahiro Yamada pinctrl-names = "default"; 455c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 456c28adcb5SMasahiro Yamada clocks = <&sys_clk 2>; 45776c48e1eSMasahiro Yamada resets = <&sys_rst 2>; 458c28adcb5SMasahiro Yamada }; 459c28adcb5SMasahiro Yamada }; 460c28adcb5SMasahiro Yamada}; 461c28adcb5SMasahiro Yamada 462c28adcb5SMasahiro Yamada#include "uniphier-pinctrl.dtsi" 463