105f7e3d1SMasahiro Yamada// SPDX-License-Identifier: GPL-2.0+ OR MIT 205f7e3d1SMasahiro Yamada// 305f7e3d1SMasahiro Yamada// Device Tree Source for UniPhier PXs3 SoC 405f7e3d1SMasahiro Yamada// 505f7e3d1SMasahiro Yamada// Copyright (C) 2017 Socionext Inc. 605f7e3d1SMasahiro Yamada// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7c28adcb5SMasahiro Yamada 8b6e5ec20SMasahiro Yamada#include <dt-bindings/gpio/gpio.h> 98311ca57SMasahiro Yamada#include <dt-bindings/gpio/uniphier-gpio.h> 10b6e5ec20SMasahiro Yamada 11c28adcb5SMasahiro Yamada/memreserve/ 0x80000000 0x02000000; 12c28adcb5SMasahiro Yamada 13c28adcb5SMasahiro Yamada/ { 14c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3"; 15c28adcb5SMasahiro Yamada #address-cells = <2>; 16c28adcb5SMasahiro Yamada #size-cells = <2>; 17c28adcb5SMasahiro Yamada interrupt-parent = <&gic>; 18c28adcb5SMasahiro Yamada 19c28adcb5SMasahiro Yamada cpus { 20c28adcb5SMasahiro Yamada #address-cells = <2>; 21c28adcb5SMasahiro Yamada #size-cells = <0>; 22c28adcb5SMasahiro Yamada 23c28adcb5SMasahiro Yamada cpu-map { 24c28adcb5SMasahiro Yamada cluster0 { 25c28adcb5SMasahiro Yamada core0 { 26c28adcb5SMasahiro Yamada cpu = <&cpu0>; 27c28adcb5SMasahiro Yamada }; 28c28adcb5SMasahiro Yamada core1 { 29c28adcb5SMasahiro Yamada cpu = <&cpu1>; 30c28adcb5SMasahiro Yamada }; 31c28adcb5SMasahiro Yamada core2 { 32c28adcb5SMasahiro Yamada cpu = <&cpu2>; 33c28adcb5SMasahiro Yamada }; 34c28adcb5SMasahiro Yamada core3 { 35c28adcb5SMasahiro Yamada cpu = <&cpu3>; 36c28adcb5SMasahiro Yamada }; 37c28adcb5SMasahiro Yamada }; 38c28adcb5SMasahiro Yamada }; 39c28adcb5SMasahiro Yamada 40c28adcb5SMasahiro Yamada cpu0: cpu@0 { 41c28adcb5SMasahiro Yamada device_type = "cpu"; 42c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 43c28adcb5SMasahiro Yamada reg = <0 0x000>; 44c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 45c28adcb5SMasahiro Yamada enable-method = "psci"; 46c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 47c28adcb5SMasahiro Yamada }; 48c28adcb5SMasahiro Yamada 49c28adcb5SMasahiro Yamada cpu1: cpu@1 { 50c28adcb5SMasahiro Yamada device_type = "cpu"; 51c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 52c28adcb5SMasahiro Yamada reg = <0 0x001>; 53c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 54c28adcb5SMasahiro Yamada enable-method = "psci"; 55c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 56c28adcb5SMasahiro Yamada }; 57c28adcb5SMasahiro Yamada 58c28adcb5SMasahiro Yamada cpu2: cpu@2 { 59c28adcb5SMasahiro Yamada device_type = "cpu"; 60c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 61c28adcb5SMasahiro Yamada reg = <0 0x002>; 62c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 63c28adcb5SMasahiro Yamada enable-method = "psci"; 64c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 65c28adcb5SMasahiro Yamada }; 66c28adcb5SMasahiro Yamada 67c28adcb5SMasahiro Yamada cpu3: cpu@3 { 68c28adcb5SMasahiro Yamada device_type = "cpu"; 69c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 70c28adcb5SMasahiro Yamada reg = <0 0x003>; 71c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 72c28adcb5SMasahiro Yamada enable-method = "psci"; 73c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 74c28adcb5SMasahiro Yamada }; 75c28adcb5SMasahiro Yamada }; 76c28adcb5SMasahiro Yamada 779cd7d03fSMasahiro Yamada cluster0_opp: opp-table { 78c28adcb5SMasahiro Yamada compatible = "operating-points-v2"; 79c28adcb5SMasahiro Yamada opp-shared; 80c28adcb5SMasahiro Yamada 81c28adcb5SMasahiro Yamada opp-250000000 { 82c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 83c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 84c28adcb5SMasahiro Yamada }; 85c28adcb5SMasahiro Yamada opp-325000000 { 86c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <325000000>; 87c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 88c28adcb5SMasahiro Yamada }; 89c28adcb5SMasahiro Yamada opp-500000000 { 90c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 91c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 92c28adcb5SMasahiro Yamada }; 93c28adcb5SMasahiro Yamada opp-650000000 { 94c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <650000000>; 95c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 96c28adcb5SMasahiro Yamada }; 97c28adcb5SMasahiro Yamada opp-666667000 { 98c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 99c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 100c28adcb5SMasahiro Yamada }; 101c28adcb5SMasahiro Yamada opp-866667000 { 102c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <866667000>; 103c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 104c28adcb5SMasahiro Yamada }; 105c28adcb5SMasahiro Yamada opp-1000000000 { 106c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 107c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 108c28adcb5SMasahiro Yamada }; 109c28adcb5SMasahiro Yamada opp-1300000000 { 110c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1300000000>; 111c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 112c28adcb5SMasahiro Yamada }; 113c28adcb5SMasahiro Yamada }; 114c28adcb5SMasahiro Yamada 115c28adcb5SMasahiro Yamada psci { 116c28adcb5SMasahiro Yamada compatible = "arm,psci-1.0"; 117c28adcb5SMasahiro Yamada method = "smc"; 118c28adcb5SMasahiro Yamada }; 119c28adcb5SMasahiro Yamada 120c28adcb5SMasahiro Yamada clocks { 121c28adcb5SMasahiro Yamada refclk: ref { 122c28adcb5SMasahiro Yamada compatible = "fixed-clock"; 123c28adcb5SMasahiro Yamada #clock-cells = <0>; 124c28adcb5SMasahiro Yamada clock-frequency = <25000000>; 125c28adcb5SMasahiro Yamada }; 126c28adcb5SMasahiro Yamada }; 127c28adcb5SMasahiro Yamada 128b6e5ec20SMasahiro Yamada emmc_pwrseq: emmc-pwrseq { 129b6e5ec20SMasahiro Yamada compatible = "mmc-pwrseq-emmc"; 1308311ca57SMasahiro Yamada reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 131b6e5ec20SMasahiro Yamada }; 132b6e5ec20SMasahiro Yamada 133c28adcb5SMasahiro Yamada timer { 134c28adcb5SMasahiro Yamada compatible = "arm,armv8-timer"; 135c28adcb5SMasahiro Yamada interrupts = <1 13 4>, 136c28adcb5SMasahiro Yamada <1 14 4>, 137c28adcb5SMasahiro Yamada <1 11 4>, 138c28adcb5SMasahiro Yamada <1 10 4>; 139c28adcb5SMasahiro Yamada }; 140c28adcb5SMasahiro Yamada 141c28adcb5SMasahiro Yamada soc@0 { 142c28adcb5SMasahiro Yamada compatible = "simple-bus"; 143c28adcb5SMasahiro Yamada #address-cells = <1>; 144c28adcb5SMasahiro Yamada #size-cells = <1>; 145c28adcb5SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 146c28adcb5SMasahiro Yamada 147925c5c32SKunihiko Hayashi spi0: spi@54006000 { 148925c5c32SKunihiko Hayashi compatible = "socionext,uniphier-scssi"; 149925c5c32SKunihiko Hayashi status = "disabled"; 150925c5c32SKunihiko Hayashi reg = <0x54006000 0x100>; 151925c5c32SKunihiko Hayashi interrupts = <0 39 4>; 152925c5c32SKunihiko Hayashi pinctrl-names = "default"; 153925c5c32SKunihiko Hayashi pinctrl-0 = <&pinctrl_spi0>; 154925c5c32SKunihiko Hayashi clocks = <&peri_clk 11>; 155925c5c32SKunihiko Hayashi resets = <&peri_rst 11>; 156925c5c32SKunihiko Hayashi }; 157925c5c32SKunihiko Hayashi 158925c5c32SKunihiko Hayashi spi1: spi@54006100 { 159925c5c32SKunihiko Hayashi compatible = "socionext,uniphier-scssi"; 160925c5c32SKunihiko Hayashi status = "disabled"; 161925c5c32SKunihiko Hayashi reg = <0x54006100 0x100>; 162925c5c32SKunihiko Hayashi interrupts = <0 216 4>; 163925c5c32SKunihiko Hayashi pinctrl-names = "default"; 164925c5c32SKunihiko Hayashi pinctrl-0 = <&pinctrl_spi1>; 165925c5c32SKunihiko Hayashi clocks = <&peri_clk 11>; 166925c5c32SKunihiko Hayashi resets = <&peri_rst 11>; 167925c5c32SKunihiko Hayashi }; 168925c5c32SKunihiko Hayashi 169c28adcb5SMasahiro Yamada serial0: serial@54006800 { 170c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 171c28adcb5SMasahiro Yamada status = "disabled"; 172c28adcb5SMasahiro Yamada reg = <0x54006800 0x40>; 173c28adcb5SMasahiro Yamada interrupts = <0 33 4>; 174c28adcb5SMasahiro Yamada pinctrl-names = "default"; 175c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 176c28adcb5SMasahiro Yamada clocks = <&peri_clk 0>; 17776c48e1eSMasahiro Yamada resets = <&peri_rst 0>; 178c28adcb5SMasahiro Yamada }; 179c28adcb5SMasahiro Yamada 180c28adcb5SMasahiro Yamada serial1: serial@54006900 { 181c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 182c28adcb5SMasahiro Yamada status = "disabled"; 183c28adcb5SMasahiro Yamada reg = <0x54006900 0x40>; 184c28adcb5SMasahiro Yamada interrupts = <0 35 4>; 185c28adcb5SMasahiro Yamada pinctrl-names = "default"; 186c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 187c28adcb5SMasahiro Yamada clocks = <&peri_clk 1>; 18876c48e1eSMasahiro Yamada resets = <&peri_rst 1>; 189c28adcb5SMasahiro Yamada }; 190c28adcb5SMasahiro Yamada 191c28adcb5SMasahiro Yamada serial2: serial@54006a00 { 192c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 193c28adcb5SMasahiro Yamada status = "disabled"; 194c28adcb5SMasahiro Yamada reg = <0x54006a00 0x40>; 195c28adcb5SMasahiro Yamada interrupts = <0 37 4>; 196c28adcb5SMasahiro Yamada pinctrl-names = "default"; 197c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 198c28adcb5SMasahiro Yamada clocks = <&peri_clk 2>; 19976c48e1eSMasahiro Yamada resets = <&peri_rst 2>; 200c28adcb5SMasahiro Yamada }; 201c28adcb5SMasahiro Yamada 202c28adcb5SMasahiro Yamada serial3: serial@54006b00 { 203c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 204c28adcb5SMasahiro Yamada status = "disabled"; 205c28adcb5SMasahiro Yamada reg = <0x54006b00 0x40>; 206c28adcb5SMasahiro Yamada interrupts = <0 177 4>; 207c28adcb5SMasahiro Yamada pinctrl-names = "default"; 208c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 209c28adcb5SMasahiro Yamada clocks = <&peri_clk 3>; 21076c48e1eSMasahiro Yamada resets = <&peri_rst 3>; 211c28adcb5SMasahiro Yamada }; 212c28adcb5SMasahiro Yamada 213277b51e7SMasahiro Yamada gpio: gpio@55000000 { 214277b51e7SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 215277b51e7SMasahiro Yamada reg = <0x55000000 0x200>; 216277b51e7SMasahiro Yamada interrupt-parent = <&aidet>; 217277b51e7SMasahiro Yamada interrupt-controller; 218277b51e7SMasahiro Yamada #interrupt-cells = <2>; 219277b51e7SMasahiro Yamada gpio-controller; 220277b51e7SMasahiro Yamada #gpio-cells = <2>; 221277b51e7SMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 222abb62c46SMasahiro Yamada <&pinctrl 104 0 0>, 223abb62c46SMasahiro Yamada <&pinctrl 168 0 0>; 224277b51e7SMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 225277b51e7SMasahiro Yamada "gpio_range1", 226277b51e7SMasahiro Yamada "gpio_range2"; 227277b51e7SMasahiro Yamada ngpios = <286>; 228277b51e7SMasahiro Yamada socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 229277b51e7SMasahiro Yamada <21 217 3>; 230277b51e7SMasahiro Yamada }; 231277b51e7SMasahiro Yamada 232c28adcb5SMasahiro Yamada i2c0: i2c@58780000 { 233c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 234c28adcb5SMasahiro Yamada status = "disabled"; 235c28adcb5SMasahiro Yamada reg = <0x58780000 0x80>; 236c28adcb5SMasahiro Yamada #address-cells = <1>; 237c28adcb5SMasahiro Yamada #size-cells = <0>; 238c28adcb5SMasahiro Yamada interrupts = <0 41 4>; 239c28adcb5SMasahiro Yamada pinctrl-names = "default"; 240c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 241c28adcb5SMasahiro Yamada clocks = <&peri_clk 4>; 24276c48e1eSMasahiro Yamada resets = <&peri_rst 4>; 243c28adcb5SMasahiro Yamada clock-frequency = <100000>; 244c28adcb5SMasahiro Yamada }; 245c28adcb5SMasahiro Yamada 246c28adcb5SMasahiro Yamada i2c1: i2c@58781000 { 247c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 248c28adcb5SMasahiro Yamada status = "disabled"; 249c28adcb5SMasahiro Yamada reg = <0x58781000 0x80>; 250c28adcb5SMasahiro Yamada #address-cells = <1>; 251c28adcb5SMasahiro Yamada #size-cells = <0>; 252c28adcb5SMasahiro Yamada interrupts = <0 42 4>; 253c28adcb5SMasahiro Yamada pinctrl-names = "default"; 254c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 255c28adcb5SMasahiro Yamada clocks = <&peri_clk 5>; 25676c48e1eSMasahiro Yamada resets = <&peri_rst 5>; 257c28adcb5SMasahiro Yamada clock-frequency = <100000>; 258c28adcb5SMasahiro Yamada }; 259c28adcb5SMasahiro Yamada 260c28adcb5SMasahiro Yamada i2c2: i2c@58782000 { 261c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 262c28adcb5SMasahiro Yamada status = "disabled"; 263c28adcb5SMasahiro Yamada reg = <0x58782000 0x80>; 264c28adcb5SMasahiro Yamada #address-cells = <1>; 265c28adcb5SMasahiro Yamada #size-cells = <0>; 266c28adcb5SMasahiro Yamada interrupts = <0 43 4>; 267c28adcb5SMasahiro Yamada pinctrl-names = "default"; 268c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c2>; 269c28adcb5SMasahiro Yamada clocks = <&peri_clk 6>; 27076c48e1eSMasahiro Yamada resets = <&peri_rst 6>; 271c28adcb5SMasahiro Yamada clock-frequency = <100000>; 272c28adcb5SMasahiro Yamada }; 273c28adcb5SMasahiro Yamada 274c28adcb5SMasahiro Yamada i2c3: i2c@58783000 { 275c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 276c28adcb5SMasahiro Yamada status = "disabled"; 277c28adcb5SMasahiro Yamada reg = <0x58783000 0x80>; 278c28adcb5SMasahiro Yamada #address-cells = <1>; 279c28adcb5SMasahiro Yamada #size-cells = <0>; 280c28adcb5SMasahiro Yamada interrupts = <0 44 4>; 281c28adcb5SMasahiro Yamada pinctrl-names = "default"; 282c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 283c28adcb5SMasahiro Yamada clocks = <&peri_clk 7>; 28476c48e1eSMasahiro Yamada resets = <&peri_rst 7>; 285c28adcb5SMasahiro Yamada clock-frequency = <100000>; 286c28adcb5SMasahiro Yamada }; 287c28adcb5SMasahiro Yamada 288c28adcb5SMasahiro Yamada /* chip-internal connection for HDMI */ 289c28adcb5SMasahiro Yamada i2c6: i2c@58786000 { 290c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 291c28adcb5SMasahiro Yamada reg = <0x58786000 0x80>; 292c28adcb5SMasahiro Yamada #address-cells = <1>; 293c28adcb5SMasahiro Yamada #size-cells = <0>; 294c28adcb5SMasahiro Yamada interrupts = <0 26 4>; 295c28adcb5SMasahiro Yamada clocks = <&peri_clk 10>; 29676c48e1eSMasahiro Yamada resets = <&peri_rst 10>; 297c28adcb5SMasahiro Yamada clock-frequency = <400000>; 298c28adcb5SMasahiro Yamada }; 299c28adcb5SMasahiro Yamada 300c28adcb5SMasahiro Yamada system_bus: system-bus@58c00000 { 301c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 302c28adcb5SMasahiro Yamada status = "disabled"; 303c28adcb5SMasahiro Yamada reg = <0x58c00000 0x400>; 304c28adcb5SMasahiro Yamada #address-cells = <2>; 305c28adcb5SMasahiro Yamada #size-cells = <1>; 306c28adcb5SMasahiro Yamada pinctrl-names = "default"; 307c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 308c28adcb5SMasahiro Yamada }; 309c28adcb5SMasahiro Yamada 310c28adcb5SMasahiro Yamada smpctrl@59801000 { 311c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 312c28adcb5SMasahiro Yamada reg = <0x59801000 0x400>; 313c28adcb5SMasahiro Yamada }; 314c28adcb5SMasahiro Yamada 315c28adcb5SMasahiro Yamada sdctrl@59810000 { 316c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sdctrl", 317c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 318c28adcb5SMasahiro Yamada reg = <0x59810000 0x400>; 319c28adcb5SMasahiro Yamada 320c28adcb5SMasahiro Yamada sd_clk: clock { 321c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-clock"; 322c28adcb5SMasahiro Yamada #clock-cells = <1>; 323c28adcb5SMasahiro Yamada }; 324c28adcb5SMasahiro Yamada 325c28adcb5SMasahiro Yamada sd_rst: reset { 326c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-reset"; 327c28adcb5SMasahiro Yamada #reset-cells = <1>; 328c28adcb5SMasahiro Yamada }; 329c28adcb5SMasahiro Yamada }; 330c28adcb5SMasahiro Yamada 331c28adcb5SMasahiro Yamada perictrl@59820000 { 332c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-perictrl", 333c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 334c28adcb5SMasahiro Yamada reg = <0x59820000 0x200>; 335c28adcb5SMasahiro Yamada 336c28adcb5SMasahiro Yamada peri_clk: clock { 337c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-clock"; 338c28adcb5SMasahiro Yamada #clock-cells = <1>; 339c28adcb5SMasahiro Yamada }; 340c28adcb5SMasahiro Yamada 341c28adcb5SMasahiro Yamada peri_rst: reset { 342c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-reset"; 343c28adcb5SMasahiro Yamada #reset-cells = <1>; 344c28adcb5SMasahiro Yamada }; 345c28adcb5SMasahiro Yamada }; 346c28adcb5SMasahiro Yamada 347c28adcb5SMasahiro Yamada emmc: sdhc@5a000000 { 348c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 349c28adcb5SMasahiro Yamada reg = <0x5a000000 0x400>; 350c28adcb5SMasahiro Yamada interrupts = <0 78 4>; 351c28adcb5SMasahiro Yamada pinctrl-names = "default"; 352c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 353c28adcb5SMasahiro Yamada clocks = <&sys_clk 4>; 35476c48e1eSMasahiro Yamada resets = <&sys_rst 4>; 355c28adcb5SMasahiro Yamada bus-width = <8>; 356c28adcb5SMasahiro Yamada mmc-ddr-1_8v; 357c28adcb5SMasahiro Yamada mmc-hs200-1_8v; 358b6e5ec20SMasahiro Yamada mmc-pwrseq = <&emmc_pwrseq>; 359f4e5200fSMasahiro Yamada cdns,phy-input-delay-legacy = <9>; 360c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 361c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 362c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 363c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 364c28adcb5SMasahiro Yamada }; 365c28adcb5SMasahiro Yamada 36684a9c4d5SMasahiro Yamada sd: sdhc@5a400000 { 36784a9c4d5SMasahiro Yamada compatible = "socionext,uniphier-sd-v3.1.1"; 36884a9c4d5SMasahiro Yamada status = "disabled"; 36984a9c4d5SMasahiro Yamada reg = <0x5a400000 0x800>; 37084a9c4d5SMasahiro Yamada interrupts = <0 76 4>; 37184a9c4d5SMasahiro Yamada pinctrl-names = "default", "uhs"; 37284a9c4d5SMasahiro Yamada pinctrl-0 = <&pinctrl_sd>; 37384a9c4d5SMasahiro Yamada pinctrl-1 = <&pinctrl_sd_uhs>; 37484a9c4d5SMasahiro Yamada clocks = <&sd_clk 0>; 37584a9c4d5SMasahiro Yamada reset-names = "host"; 37684a9c4d5SMasahiro Yamada resets = <&sd_rst 0>; 37784a9c4d5SMasahiro Yamada bus-width = <4>; 37884a9c4d5SMasahiro Yamada cap-sd-highspeed; 37984a9c4d5SMasahiro Yamada sd-uhs-sdr12; 38084a9c4d5SMasahiro Yamada sd-uhs-sdr25; 38184a9c4d5SMasahiro Yamada sd-uhs-sdr50; 38284a9c4d5SMasahiro Yamada }; 38384a9c4d5SMasahiro Yamada 384b076ff8bSKunihiko Hayashi soc_glue: soc-glue@5f800000 { 385c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-soc-glue", 386c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 387c28adcb5SMasahiro Yamada reg = <0x5f800000 0x2000>; 388c28adcb5SMasahiro Yamada 389c28adcb5SMasahiro Yamada pinctrl: pinctrl { 390c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-pinctrl"; 391c28adcb5SMasahiro Yamada }; 392c28adcb5SMasahiro Yamada }; 393c28adcb5SMasahiro Yamada 394f05851e1SKeiji Hayashibara soc-glue@5f900000 { 395f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-pxs3-soc-glue-debug", 396f05851e1SKeiji Hayashibara "simple-mfd"; 397f05851e1SKeiji Hayashibara #address-cells = <1>; 398f05851e1SKeiji Hayashibara #size-cells = <1>; 399f05851e1SKeiji Hayashibara ranges = <0 0x5f900000 0x2000>; 400f05851e1SKeiji Hayashibara 401f05851e1SKeiji Hayashibara efuse@100 { 402f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 403f05851e1SKeiji Hayashibara reg = <0x100 0x28>; 404f05851e1SKeiji Hayashibara }; 405f05851e1SKeiji Hayashibara 406f05851e1SKeiji Hayashibara efuse@200 { 407f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 408f05851e1SKeiji Hayashibara reg = <0x200 0x68>; 409f05851e1SKeiji Hayashibara }; 410f05851e1SKeiji Hayashibara }; 411f05851e1SKeiji Hayashibara 412c28adcb5SMasahiro Yamada aidet: aidet@5fc20000 { 413c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-aidet"; 414c28adcb5SMasahiro Yamada reg = <0x5fc20000 0x200>; 415c28adcb5SMasahiro Yamada interrupt-controller; 416c28adcb5SMasahiro Yamada #interrupt-cells = <2>; 417c28adcb5SMasahiro Yamada }; 418c28adcb5SMasahiro Yamada 419c28adcb5SMasahiro Yamada gic: interrupt-controller@5fe00000 { 420c28adcb5SMasahiro Yamada compatible = "arm,gic-v3"; 421c28adcb5SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 422c28adcb5SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 423c28adcb5SMasahiro Yamada interrupt-controller; 424c28adcb5SMasahiro Yamada #interrupt-cells = <3>; 425c28adcb5SMasahiro Yamada interrupts = <1 9 4>; 426c28adcb5SMasahiro Yamada }; 427c28adcb5SMasahiro Yamada 428c28adcb5SMasahiro Yamada sysctrl@61840000 { 429c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sysctrl", 430c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 431c28adcb5SMasahiro Yamada reg = <0x61840000 0x10000>; 432c28adcb5SMasahiro Yamada 433c28adcb5SMasahiro Yamada sys_clk: clock { 434c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-clock"; 435c28adcb5SMasahiro Yamada #clock-cells = <1>; 436c28adcb5SMasahiro Yamada }; 437c28adcb5SMasahiro Yamada 438c28adcb5SMasahiro Yamada sys_rst: reset { 439c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-reset"; 440c28adcb5SMasahiro Yamada #reset-cells = <1>; 441c28adcb5SMasahiro Yamada }; 442c28adcb5SMasahiro Yamada 443c28adcb5SMasahiro Yamada watchdog { 444c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-wdt"; 445c28adcb5SMasahiro Yamada }; 446c28adcb5SMasahiro Yamada }; 447c28adcb5SMasahiro Yamada 448aba054a1SKunihiko Hayashi eth0: ethernet@65000000 { 449aba054a1SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ave4"; 450aba054a1SKunihiko Hayashi status = "disabled"; 451aba054a1SKunihiko Hayashi reg = <0x65000000 0x8500>; 452aba054a1SKunihiko Hayashi interrupts = <0 66 4>; 453aba054a1SKunihiko Hayashi pinctrl-names = "default"; 454aba054a1SKunihiko Hayashi pinctrl-0 = <&pinctrl_ether_rgmii>; 455a34a464dSKunihiko Hayashi clock-names = "ether"; 456aba054a1SKunihiko Hayashi clocks = <&sys_clk 6>; 457a34a464dSKunihiko Hayashi reset-names = "ether"; 458aba054a1SKunihiko Hayashi resets = <&sys_rst 6>; 459aba054a1SKunihiko Hayashi phy-mode = "rgmii"; 460aba054a1SKunihiko Hayashi local-mac-address = [00 00 00 00 00 00]; 461b076ff8bSKunihiko Hayashi socionext,syscon-phy-mode = <&soc_glue 0>; 462aba054a1SKunihiko Hayashi 463aba054a1SKunihiko Hayashi mdio0: mdio { 464aba054a1SKunihiko Hayashi #address-cells = <1>; 465aba054a1SKunihiko Hayashi #size-cells = <0>; 466aba054a1SKunihiko Hayashi }; 467aba054a1SKunihiko Hayashi }; 468aba054a1SKunihiko Hayashi 469aba054a1SKunihiko Hayashi eth1: ethernet@65200000 { 470aba054a1SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ave4"; 471aba054a1SKunihiko Hayashi status = "disabled"; 472aba054a1SKunihiko Hayashi reg = <0x65200000 0x8500>; 473aba054a1SKunihiko Hayashi interrupts = <0 67 4>; 474aba054a1SKunihiko Hayashi pinctrl-names = "default"; 475aba054a1SKunihiko Hayashi pinctrl-0 = <&pinctrl_ether1_rgmii>; 476a34a464dSKunihiko Hayashi clock-names = "ether"; 477aba054a1SKunihiko Hayashi clocks = <&sys_clk 7>; 478a34a464dSKunihiko Hayashi reset-names = "ether"; 479aba054a1SKunihiko Hayashi resets = <&sys_rst 7>; 480aba054a1SKunihiko Hayashi phy-mode = "rgmii"; 481aba054a1SKunihiko Hayashi local-mac-address = [00 00 00 00 00 00]; 482b076ff8bSKunihiko Hayashi socionext,syscon-phy-mode = <&soc_glue 1>; 483aba054a1SKunihiko Hayashi 484aba054a1SKunihiko Hayashi mdio1: mdio { 485aba054a1SKunihiko Hayashi #address-cells = <1>; 486aba054a1SKunihiko Hayashi #size-cells = <0>; 487aba054a1SKunihiko Hayashi }; 488aba054a1SKunihiko Hayashi }; 489aba054a1SKunihiko Hayashi 490c28adcb5SMasahiro Yamada nand: nand@68000000 { 491c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 492c28adcb5SMasahiro Yamada status = "disabled"; 493c28adcb5SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 494c28adcb5SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 495c28adcb5SMasahiro Yamada interrupts = <0 65 4>; 496c28adcb5SMasahiro Yamada pinctrl-names = "default"; 497c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 498bae120f8SMasahiro Yamada clock-names = "nand", "nand_x", "ecc"; 499bae120f8SMasahiro Yamada clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 50076c48e1eSMasahiro Yamada resets = <&sys_rst 2>; 501c28adcb5SMasahiro Yamada }; 502c28adcb5SMasahiro Yamada }; 503c28adcb5SMasahiro Yamada}; 504c28adcb5SMasahiro Yamada 505c28adcb5SMasahiro Yamada#include "uniphier-pinctrl.dtsi" 506