1c28adcb5SMasahiro Yamada/* 2c28adcb5SMasahiro Yamada * Device Tree Source for UniPhier PXs3 SoC 3c28adcb5SMasahiro Yamada * 4c28adcb5SMasahiro Yamada * Copyright (C) 2017 Socionext Inc. 5c28adcb5SMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6c28adcb5SMasahiro Yamada * 7c28adcb5SMasahiro Yamada * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8c28adcb5SMasahiro Yamada */ 9c28adcb5SMasahiro Yamada 10b6e5ec20SMasahiro Yamada#include <dt-bindings/gpio/gpio.h> 11b6e5ec20SMasahiro Yamada 12c28adcb5SMasahiro Yamada/memreserve/ 0x80000000 0x02000000; 13c28adcb5SMasahiro Yamada 14c28adcb5SMasahiro Yamada/ { 15c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3"; 16c28adcb5SMasahiro Yamada #address-cells = <2>; 17c28adcb5SMasahiro Yamada #size-cells = <2>; 18c28adcb5SMasahiro Yamada interrupt-parent = <&gic>; 19c28adcb5SMasahiro Yamada 20c28adcb5SMasahiro Yamada cpus { 21c28adcb5SMasahiro Yamada #address-cells = <2>; 22c28adcb5SMasahiro Yamada #size-cells = <0>; 23c28adcb5SMasahiro Yamada 24c28adcb5SMasahiro Yamada cpu-map { 25c28adcb5SMasahiro Yamada cluster0 { 26c28adcb5SMasahiro Yamada core0 { 27c28adcb5SMasahiro Yamada cpu = <&cpu0>; 28c28adcb5SMasahiro Yamada }; 29c28adcb5SMasahiro Yamada core1 { 30c28adcb5SMasahiro Yamada cpu = <&cpu1>; 31c28adcb5SMasahiro Yamada }; 32c28adcb5SMasahiro Yamada core2 { 33c28adcb5SMasahiro Yamada cpu = <&cpu2>; 34c28adcb5SMasahiro Yamada }; 35c28adcb5SMasahiro Yamada core3 { 36c28adcb5SMasahiro Yamada cpu = <&cpu3>; 37c28adcb5SMasahiro Yamada }; 38c28adcb5SMasahiro Yamada }; 39c28adcb5SMasahiro Yamada }; 40c28adcb5SMasahiro Yamada 41c28adcb5SMasahiro Yamada cpu0: cpu@0 { 42c28adcb5SMasahiro Yamada device_type = "cpu"; 43c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 44c28adcb5SMasahiro Yamada reg = <0 0x000>; 45c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 46c28adcb5SMasahiro Yamada enable-method = "psci"; 47c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 48c28adcb5SMasahiro Yamada }; 49c28adcb5SMasahiro Yamada 50c28adcb5SMasahiro Yamada cpu1: cpu@1 { 51c28adcb5SMasahiro Yamada device_type = "cpu"; 52c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 53c28adcb5SMasahiro Yamada reg = <0 0x001>; 54c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 55c28adcb5SMasahiro Yamada enable-method = "psci"; 56c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 57c28adcb5SMasahiro Yamada }; 58c28adcb5SMasahiro Yamada 59c28adcb5SMasahiro Yamada cpu2: cpu@2 { 60c28adcb5SMasahiro Yamada device_type = "cpu"; 61c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 62c28adcb5SMasahiro Yamada reg = <0 0x002>; 63c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 64c28adcb5SMasahiro Yamada enable-method = "psci"; 65c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 66c28adcb5SMasahiro Yamada }; 67c28adcb5SMasahiro Yamada 68c28adcb5SMasahiro Yamada cpu3: cpu@3 { 69c28adcb5SMasahiro Yamada device_type = "cpu"; 70c28adcb5SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 71c28adcb5SMasahiro Yamada reg = <0 0x003>; 72c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 73c28adcb5SMasahiro Yamada enable-method = "psci"; 74c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 75c28adcb5SMasahiro Yamada }; 76c28adcb5SMasahiro Yamada }; 77c28adcb5SMasahiro Yamada 789cd7d03fSMasahiro Yamada cluster0_opp: opp-table { 79c28adcb5SMasahiro Yamada compatible = "operating-points-v2"; 80c28adcb5SMasahiro Yamada opp-shared; 81c28adcb5SMasahiro Yamada 82c28adcb5SMasahiro Yamada opp-250000000 { 83c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 84c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 85c28adcb5SMasahiro Yamada }; 86c28adcb5SMasahiro Yamada opp-325000000 { 87c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <325000000>; 88c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 89c28adcb5SMasahiro Yamada }; 90c28adcb5SMasahiro Yamada opp-500000000 { 91c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 92c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 93c28adcb5SMasahiro Yamada }; 94c28adcb5SMasahiro Yamada opp-650000000 { 95c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <650000000>; 96c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 97c28adcb5SMasahiro Yamada }; 98c28adcb5SMasahiro Yamada opp-666667000 { 99c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 100c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 101c28adcb5SMasahiro Yamada }; 102c28adcb5SMasahiro Yamada opp-866667000 { 103c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <866667000>; 104c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 105c28adcb5SMasahiro Yamada }; 106c28adcb5SMasahiro Yamada opp-1000000000 { 107c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 108c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 109c28adcb5SMasahiro Yamada }; 110c28adcb5SMasahiro Yamada opp-1300000000 { 111c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1300000000>; 112c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 113c28adcb5SMasahiro Yamada }; 114c28adcb5SMasahiro Yamada }; 115c28adcb5SMasahiro Yamada 116c28adcb5SMasahiro Yamada psci { 117c28adcb5SMasahiro Yamada compatible = "arm,psci-1.0"; 118c28adcb5SMasahiro Yamada method = "smc"; 119c28adcb5SMasahiro Yamada }; 120c28adcb5SMasahiro Yamada 121c28adcb5SMasahiro Yamada clocks { 122c28adcb5SMasahiro Yamada refclk: ref { 123c28adcb5SMasahiro Yamada compatible = "fixed-clock"; 124c28adcb5SMasahiro Yamada #clock-cells = <0>; 125c28adcb5SMasahiro Yamada clock-frequency = <25000000>; 126c28adcb5SMasahiro Yamada }; 127c28adcb5SMasahiro Yamada }; 128c28adcb5SMasahiro Yamada 129b6e5ec20SMasahiro Yamada emmc_pwrseq: emmc-pwrseq { 130b6e5ec20SMasahiro Yamada compatible = "mmc-pwrseq-emmc"; 131b6e5ec20SMasahiro Yamada reset-gpios = <&gpio 47 GPIO_ACTIVE_LOW>; 132b6e5ec20SMasahiro Yamada }; 133b6e5ec20SMasahiro Yamada 134c28adcb5SMasahiro Yamada timer { 135c28adcb5SMasahiro Yamada compatible = "arm,armv8-timer"; 136c28adcb5SMasahiro Yamada interrupts = <1 13 4>, 137c28adcb5SMasahiro Yamada <1 14 4>, 138c28adcb5SMasahiro Yamada <1 11 4>, 139c28adcb5SMasahiro Yamada <1 10 4>; 140c28adcb5SMasahiro Yamada }; 141c28adcb5SMasahiro Yamada 142c28adcb5SMasahiro Yamada soc@0 { 143c28adcb5SMasahiro Yamada compatible = "simple-bus"; 144c28adcb5SMasahiro Yamada #address-cells = <1>; 145c28adcb5SMasahiro Yamada #size-cells = <1>; 146c28adcb5SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 147c28adcb5SMasahiro Yamada 148c28adcb5SMasahiro Yamada serial0: serial@54006800 { 149c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 150c28adcb5SMasahiro Yamada status = "disabled"; 151c28adcb5SMasahiro Yamada reg = <0x54006800 0x40>; 152c28adcb5SMasahiro Yamada interrupts = <0 33 4>; 153c28adcb5SMasahiro Yamada pinctrl-names = "default"; 154c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 155c28adcb5SMasahiro Yamada clocks = <&peri_clk 0>; 15676c48e1eSMasahiro Yamada resets = <&peri_rst 0>; 157c28adcb5SMasahiro Yamada }; 158c28adcb5SMasahiro Yamada 159c28adcb5SMasahiro Yamada serial1: serial@54006900 { 160c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 161c28adcb5SMasahiro Yamada status = "disabled"; 162c28adcb5SMasahiro Yamada reg = <0x54006900 0x40>; 163c28adcb5SMasahiro Yamada interrupts = <0 35 4>; 164c28adcb5SMasahiro Yamada pinctrl-names = "default"; 165c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 166c28adcb5SMasahiro Yamada clocks = <&peri_clk 1>; 16776c48e1eSMasahiro Yamada resets = <&peri_rst 1>; 168c28adcb5SMasahiro Yamada }; 169c28adcb5SMasahiro Yamada 170c28adcb5SMasahiro Yamada serial2: serial@54006a00 { 171c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 172c28adcb5SMasahiro Yamada status = "disabled"; 173c28adcb5SMasahiro Yamada reg = <0x54006a00 0x40>; 174c28adcb5SMasahiro Yamada interrupts = <0 37 4>; 175c28adcb5SMasahiro Yamada pinctrl-names = "default"; 176c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 177c28adcb5SMasahiro Yamada clocks = <&peri_clk 2>; 17876c48e1eSMasahiro Yamada resets = <&peri_rst 2>; 179c28adcb5SMasahiro Yamada }; 180c28adcb5SMasahiro Yamada 181c28adcb5SMasahiro Yamada serial3: serial@54006b00 { 182c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 183c28adcb5SMasahiro Yamada status = "disabled"; 184c28adcb5SMasahiro Yamada reg = <0x54006b00 0x40>; 185c28adcb5SMasahiro Yamada interrupts = <0 177 4>; 186c28adcb5SMasahiro Yamada pinctrl-names = "default"; 187c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 188c28adcb5SMasahiro Yamada clocks = <&peri_clk 3>; 18976c48e1eSMasahiro Yamada resets = <&peri_rst 3>; 190c28adcb5SMasahiro Yamada }; 191c28adcb5SMasahiro Yamada 192277b51e7SMasahiro Yamada gpio: gpio@55000000 { 193277b51e7SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 194277b51e7SMasahiro Yamada reg = <0x55000000 0x200>; 195277b51e7SMasahiro Yamada interrupt-parent = <&aidet>; 196277b51e7SMasahiro Yamada interrupt-controller; 197277b51e7SMasahiro Yamada #interrupt-cells = <2>; 198277b51e7SMasahiro Yamada gpio-controller; 199277b51e7SMasahiro Yamada #gpio-cells = <2>; 200277b51e7SMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 201277b51e7SMasahiro Yamada <&pinctrl 96 0 0>, 202277b51e7SMasahiro Yamada <&pinctrl 160 0 0>; 203277b51e7SMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 204277b51e7SMasahiro Yamada "gpio_range1", 205277b51e7SMasahiro Yamada "gpio_range2"; 206277b51e7SMasahiro Yamada ngpios = <286>; 207277b51e7SMasahiro Yamada socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 208277b51e7SMasahiro Yamada <21 217 3>; 209277b51e7SMasahiro Yamada }; 210277b51e7SMasahiro Yamada 211c28adcb5SMasahiro Yamada i2c0: i2c@58780000 { 212c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 213c28adcb5SMasahiro Yamada status = "disabled"; 214c28adcb5SMasahiro Yamada reg = <0x58780000 0x80>; 215c28adcb5SMasahiro Yamada #address-cells = <1>; 216c28adcb5SMasahiro Yamada #size-cells = <0>; 217c28adcb5SMasahiro Yamada interrupts = <0 41 4>; 218c28adcb5SMasahiro Yamada pinctrl-names = "default"; 219c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 220c28adcb5SMasahiro Yamada clocks = <&peri_clk 4>; 22176c48e1eSMasahiro Yamada resets = <&peri_rst 4>; 222c28adcb5SMasahiro Yamada clock-frequency = <100000>; 223c28adcb5SMasahiro Yamada }; 224c28adcb5SMasahiro Yamada 225c28adcb5SMasahiro Yamada i2c1: i2c@58781000 { 226c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 227c28adcb5SMasahiro Yamada status = "disabled"; 228c28adcb5SMasahiro Yamada reg = <0x58781000 0x80>; 229c28adcb5SMasahiro Yamada #address-cells = <1>; 230c28adcb5SMasahiro Yamada #size-cells = <0>; 231c28adcb5SMasahiro Yamada interrupts = <0 42 4>; 232c28adcb5SMasahiro Yamada pinctrl-names = "default"; 233c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 234c28adcb5SMasahiro Yamada clocks = <&peri_clk 5>; 23576c48e1eSMasahiro Yamada resets = <&peri_rst 5>; 236c28adcb5SMasahiro Yamada clock-frequency = <100000>; 237c28adcb5SMasahiro Yamada }; 238c28adcb5SMasahiro Yamada 239c28adcb5SMasahiro Yamada i2c2: i2c@58782000 { 240c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 241c28adcb5SMasahiro Yamada status = "disabled"; 242c28adcb5SMasahiro Yamada reg = <0x58782000 0x80>; 243c28adcb5SMasahiro Yamada #address-cells = <1>; 244c28adcb5SMasahiro Yamada #size-cells = <0>; 245c28adcb5SMasahiro Yamada interrupts = <0 43 4>; 246c28adcb5SMasahiro Yamada pinctrl-names = "default"; 247c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c2>; 248c28adcb5SMasahiro Yamada clocks = <&peri_clk 6>; 24976c48e1eSMasahiro Yamada resets = <&peri_rst 6>; 250c28adcb5SMasahiro Yamada clock-frequency = <100000>; 251c28adcb5SMasahiro Yamada }; 252c28adcb5SMasahiro Yamada 253c28adcb5SMasahiro Yamada i2c3: i2c@58783000 { 254c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 255c28adcb5SMasahiro Yamada status = "disabled"; 256c28adcb5SMasahiro Yamada reg = <0x58783000 0x80>; 257c28adcb5SMasahiro Yamada #address-cells = <1>; 258c28adcb5SMasahiro Yamada #size-cells = <0>; 259c28adcb5SMasahiro Yamada interrupts = <0 44 4>; 260c28adcb5SMasahiro Yamada pinctrl-names = "default"; 261c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 262c28adcb5SMasahiro Yamada clocks = <&peri_clk 7>; 26376c48e1eSMasahiro Yamada resets = <&peri_rst 7>; 264c28adcb5SMasahiro Yamada clock-frequency = <100000>; 265c28adcb5SMasahiro Yamada }; 266c28adcb5SMasahiro Yamada 267c28adcb5SMasahiro Yamada /* chip-internal connection for HDMI */ 268c28adcb5SMasahiro Yamada i2c6: i2c@58786000 { 269c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 270c28adcb5SMasahiro Yamada reg = <0x58786000 0x80>; 271c28adcb5SMasahiro Yamada #address-cells = <1>; 272c28adcb5SMasahiro Yamada #size-cells = <0>; 273c28adcb5SMasahiro Yamada interrupts = <0 26 4>; 274c28adcb5SMasahiro Yamada clocks = <&peri_clk 10>; 27576c48e1eSMasahiro Yamada resets = <&peri_rst 10>; 276c28adcb5SMasahiro Yamada clock-frequency = <400000>; 277c28adcb5SMasahiro Yamada }; 278c28adcb5SMasahiro Yamada 279c28adcb5SMasahiro Yamada system_bus: system-bus@58c00000 { 280c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 281c28adcb5SMasahiro Yamada status = "disabled"; 282c28adcb5SMasahiro Yamada reg = <0x58c00000 0x400>; 283c28adcb5SMasahiro Yamada #address-cells = <2>; 284c28adcb5SMasahiro Yamada #size-cells = <1>; 285c28adcb5SMasahiro Yamada pinctrl-names = "default"; 286c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 287c28adcb5SMasahiro Yamada }; 288c28adcb5SMasahiro Yamada 289c28adcb5SMasahiro Yamada smpctrl@59801000 { 290c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 291c28adcb5SMasahiro Yamada reg = <0x59801000 0x400>; 292c28adcb5SMasahiro Yamada }; 293c28adcb5SMasahiro Yamada 294c28adcb5SMasahiro Yamada sdctrl@59810000 { 295c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sdctrl", 296c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 297c28adcb5SMasahiro Yamada reg = <0x59810000 0x400>; 298c28adcb5SMasahiro Yamada 299c28adcb5SMasahiro Yamada sd_clk: clock { 300c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-clock"; 301c28adcb5SMasahiro Yamada #clock-cells = <1>; 302c28adcb5SMasahiro Yamada }; 303c28adcb5SMasahiro Yamada 304c28adcb5SMasahiro Yamada sd_rst: reset { 305c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-reset"; 306c28adcb5SMasahiro Yamada #reset-cells = <1>; 307c28adcb5SMasahiro Yamada }; 308c28adcb5SMasahiro Yamada }; 309c28adcb5SMasahiro Yamada 310c28adcb5SMasahiro Yamada perictrl@59820000 { 311c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-perictrl", 312c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 313c28adcb5SMasahiro Yamada reg = <0x59820000 0x200>; 314c28adcb5SMasahiro Yamada 315c28adcb5SMasahiro Yamada peri_clk: clock { 316c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-clock"; 317c28adcb5SMasahiro Yamada #clock-cells = <1>; 318c28adcb5SMasahiro Yamada }; 319c28adcb5SMasahiro Yamada 320c28adcb5SMasahiro Yamada peri_rst: reset { 321c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-reset"; 322c28adcb5SMasahiro Yamada #reset-cells = <1>; 323c28adcb5SMasahiro Yamada }; 324c28adcb5SMasahiro Yamada }; 325c28adcb5SMasahiro Yamada 326c28adcb5SMasahiro Yamada emmc: sdhc@5a000000 { 327c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 328c28adcb5SMasahiro Yamada reg = <0x5a000000 0x400>; 329c28adcb5SMasahiro Yamada interrupts = <0 78 4>; 330c28adcb5SMasahiro Yamada pinctrl-names = "default"; 331c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 332c28adcb5SMasahiro Yamada clocks = <&sys_clk 4>; 33376c48e1eSMasahiro Yamada resets = <&sys_rst 4>; 334c28adcb5SMasahiro Yamada bus-width = <8>; 335c28adcb5SMasahiro Yamada mmc-ddr-1_8v; 336c28adcb5SMasahiro Yamada mmc-hs200-1_8v; 337b6e5ec20SMasahiro Yamada mmc-pwrseq = <&emmc_pwrseq>; 338c28adcb5SMasahiro Yamada cdns,phy-input-delay-legacy = <4>; 339c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 340c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 341c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 342c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 343c28adcb5SMasahiro Yamada }; 344c28adcb5SMasahiro Yamada 345c28adcb5SMasahiro Yamada soc-glue@5f800000 { 346c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-soc-glue", 347c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 348c28adcb5SMasahiro Yamada reg = <0x5f800000 0x2000>; 349c28adcb5SMasahiro Yamada 350c28adcb5SMasahiro Yamada pinctrl: pinctrl { 351c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-pinctrl"; 352c28adcb5SMasahiro Yamada }; 353c28adcb5SMasahiro Yamada }; 354c28adcb5SMasahiro Yamada 355f05851e1SKeiji Hayashibara soc-glue@5f900000 { 356f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-pxs3-soc-glue-debug", 357f05851e1SKeiji Hayashibara "simple-mfd"; 358f05851e1SKeiji Hayashibara #address-cells = <1>; 359f05851e1SKeiji Hayashibara #size-cells = <1>; 360f05851e1SKeiji Hayashibara ranges = <0 0x5f900000 0x2000>; 361f05851e1SKeiji Hayashibara 362f05851e1SKeiji Hayashibara efuse@100 { 363f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 364f05851e1SKeiji Hayashibara reg = <0x100 0x28>; 365f05851e1SKeiji Hayashibara }; 366f05851e1SKeiji Hayashibara 367f05851e1SKeiji Hayashibara efuse@200 { 368f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 369f05851e1SKeiji Hayashibara reg = <0x200 0x68>; 370f05851e1SKeiji Hayashibara }; 371f05851e1SKeiji Hayashibara }; 372f05851e1SKeiji Hayashibara 373c28adcb5SMasahiro Yamada aidet: aidet@5fc20000 { 374c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-aidet"; 375c28adcb5SMasahiro Yamada reg = <0x5fc20000 0x200>; 376c28adcb5SMasahiro Yamada interrupt-controller; 377c28adcb5SMasahiro Yamada #interrupt-cells = <2>; 378c28adcb5SMasahiro Yamada }; 379c28adcb5SMasahiro Yamada 380c28adcb5SMasahiro Yamada gic: interrupt-controller@5fe00000 { 381c28adcb5SMasahiro Yamada compatible = "arm,gic-v3"; 382c28adcb5SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 383c28adcb5SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 384c28adcb5SMasahiro Yamada interrupt-controller; 385c28adcb5SMasahiro Yamada #interrupt-cells = <3>; 386c28adcb5SMasahiro Yamada interrupts = <1 9 4>; 387c28adcb5SMasahiro Yamada }; 388c28adcb5SMasahiro Yamada 389c28adcb5SMasahiro Yamada sysctrl@61840000 { 390c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sysctrl", 391c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 392c28adcb5SMasahiro Yamada reg = <0x61840000 0x10000>; 393c28adcb5SMasahiro Yamada 394c28adcb5SMasahiro Yamada sys_clk: clock { 395c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-clock"; 396c28adcb5SMasahiro Yamada #clock-cells = <1>; 397c28adcb5SMasahiro Yamada }; 398c28adcb5SMasahiro Yamada 399c28adcb5SMasahiro Yamada sys_rst: reset { 400c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-reset"; 401c28adcb5SMasahiro Yamada #reset-cells = <1>; 402c28adcb5SMasahiro Yamada }; 403c28adcb5SMasahiro Yamada 404c28adcb5SMasahiro Yamada watchdog { 405c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-wdt"; 406c28adcb5SMasahiro Yamada }; 407c28adcb5SMasahiro Yamada }; 408c28adcb5SMasahiro Yamada 409c28adcb5SMasahiro Yamada nand: nand@68000000 { 410c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 411c28adcb5SMasahiro Yamada status = "disabled"; 412c28adcb5SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 413c28adcb5SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 414c28adcb5SMasahiro Yamada interrupts = <0 65 4>; 415c28adcb5SMasahiro Yamada pinctrl-names = "default"; 416c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 417c28adcb5SMasahiro Yamada clocks = <&sys_clk 2>; 41876c48e1eSMasahiro Yamada resets = <&sys_rst 2>; 419c28adcb5SMasahiro Yamada }; 420c28adcb5SMasahiro Yamada }; 421c28adcb5SMasahiro Yamada}; 422c28adcb5SMasahiro Yamada 423c28adcb5SMasahiro Yamada#include "uniphier-pinctrl.dtsi" 424