105f7e3d1SMasahiro Yamada// SPDX-License-Identifier: GPL-2.0+ OR MIT 205f7e3d1SMasahiro Yamada// 305f7e3d1SMasahiro Yamada// Device Tree Source for UniPhier PXs3 SoC 405f7e3d1SMasahiro Yamada// 505f7e3d1SMasahiro Yamada// Copyright (C) 2017 Socionext Inc. 605f7e3d1SMasahiro Yamada// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7c28adcb5SMasahiro Yamada 8b6e5ec20SMasahiro Yamada#include <dt-bindings/gpio/gpio.h> 98311ca57SMasahiro Yamada#include <dt-bindings/gpio/uniphier-gpio.h> 104b7d3743SKunihiko Hayashi#include <dt-bindings/thermal/thermal.h> 11b6e5ec20SMasahiro Yamada 12c28adcb5SMasahiro Yamada/ { 13c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3"; 14c28adcb5SMasahiro Yamada #address-cells = <2>; 15c28adcb5SMasahiro Yamada #size-cells = <2>; 16c28adcb5SMasahiro Yamada interrupt-parent = <&gic>; 17c28adcb5SMasahiro Yamada 18c28adcb5SMasahiro Yamada cpus { 19c28adcb5SMasahiro Yamada #address-cells = <2>; 20c28adcb5SMasahiro Yamada #size-cells = <0>; 21c28adcb5SMasahiro Yamada 22c28adcb5SMasahiro Yamada cpu-map { 23c28adcb5SMasahiro Yamada cluster0 { 24c28adcb5SMasahiro Yamada core0 { 25c28adcb5SMasahiro Yamada cpu = <&cpu0>; 26c28adcb5SMasahiro Yamada }; 27c28adcb5SMasahiro Yamada core1 { 28c28adcb5SMasahiro Yamada cpu = <&cpu1>; 29c28adcb5SMasahiro Yamada }; 30c28adcb5SMasahiro Yamada core2 { 31c28adcb5SMasahiro Yamada cpu = <&cpu2>; 32c28adcb5SMasahiro Yamada }; 33c28adcb5SMasahiro Yamada core3 { 34c28adcb5SMasahiro Yamada cpu = <&cpu3>; 35c28adcb5SMasahiro Yamada }; 36c28adcb5SMasahiro Yamada }; 37c28adcb5SMasahiro Yamada }; 38c28adcb5SMasahiro Yamada 39c28adcb5SMasahiro Yamada cpu0: cpu@0 { 40c28adcb5SMasahiro Yamada device_type = "cpu"; 4131af04cdSRob Herring compatible = "arm,cortex-a53"; 42c28adcb5SMasahiro Yamada reg = <0 0x000>; 43c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 44c28adcb5SMasahiro Yamada enable-method = "psci"; 45c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 464b7d3743SKunihiko Hayashi #cooling-cells = <2>; 47c28adcb5SMasahiro Yamada }; 48c28adcb5SMasahiro Yamada 49c28adcb5SMasahiro Yamada cpu1: cpu@1 { 50c28adcb5SMasahiro Yamada device_type = "cpu"; 5131af04cdSRob Herring compatible = "arm,cortex-a53"; 52c28adcb5SMasahiro Yamada reg = <0 0x001>; 53c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 54c28adcb5SMasahiro Yamada enable-method = "psci"; 55c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 564b7d3743SKunihiko Hayashi #cooling-cells = <2>; 57c28adcb5SMasahiro Yamada }; 58c28adcb5SMasahiro Yamada 59c28adcb5SMasahiro Yamada cpu2: cpu@2 { 60c28adcb5SMasahiro Yamada device_type = "cpu"; 6131af04cdSRob Herring compatible = "arm,cortex-a53"; 62c28adcb5SMasahiro Yamada reg = <0 0x002>; 63c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 64c28adcb5SMasahiro Yamada enable-method = "psci"; 65c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 664b7d3743SKunihiko Hayashi #cooling-cells = <2>; 67c28adcb5SMasahiro Yamada }; 68c28adcb5SMasahiro Yamada 69c28adcb5SMasahiro Yamada cpu3: cpu@3 { 70c28adcb5SMasahiro Yamada device_type = "cpu"; 7131af04cdSRob Herring compatible = "arm,cortex-a53"; 72c28adcb5SMasahiro Yamada reg = <0 0x003>; 73c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 74c28adcb5SMasahiro Yamada enable-method = "psci"; 75c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 764b7d3743SKunihiko Hayashi #cooling-cells = <2>; 77c28adcb5SMasahiro Yamada }; 78c28adcb5SMasahiro Yamada }; 79c28adcb5SMasahiro Yamada 809cd7d03fSMasahiro Yamada cluster0_opp: opp-table { 81c28adcb5SMasahiro Yamada compatible = "operating-points-v2"; 82c28adcb5SMasahiro Yamada opp-shared; 83c28adcb5SMasahiro Yamada 84c28adcb5SMasahiro Yamada opp-250000000 { 85c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 86c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 87c28adcb5SMasahiro Yamada }; 88c28adcb5SMasahiro Yamada opp-325000000 { 89c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <325000000>; 90c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 91c28adcb5SMasahiro Yamada }; 92c28adcb5SMasahiro Yamada opp-500000000 { 93c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 94c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 95c28adcb5SMasahiro Yamada }; 96c28adcb5SMasahiro Yamada opp-650000000 { 97c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <650000000>; 98c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 99c28adcb5SMasahiro Yamada }; 100c28adcb5SMasahiro Yamada opp-666667000 { 101c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 102c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 103c28adcb5SMasahiro Yamada }; 104c28adcb5SMasahiro Yamada opp-866667000 { 105c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <866667000>; 106c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 107c28adcb5SMasahiro Yamada }; 108c28adcb5SMasahiro Yamada opp-1000000000 { 109c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 110c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 111c28adcb5SMasahiro Yamada }; 112c28adcb5SMasahiro Yamada opp-1300000000 { 113c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1300000000>; 114c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 115c28adcb5SMasahiro Yamada }; 116c28adcb5SMasahiro Yamada }; 117c28adcb5SMasahiro Yamada 118c28adcb5SMasahiro Yamada psci { 119c28adcb5SMasahiro Yamada compatible = "arm,psci-1.0"; 120c28adcb5SMasahiro Yamada method = "smc"; 121c28adcb5SMasahiro Yamada }; 122c28adcb5SMasahiro Yamada 123c28adcb5SMasahiro Yamada clocks { 124c28adcb5SMasahiro Yamada refclk: ref { 125c28adcb5SMasahiro Yamada compatible = "fixed-clock"; 126c28adcb5SMasahiro Yamada #clock-cells = <0>; 127c28adcb5SMasahiro Yamada clock-frequency = <25000000>; 128c28adcb5SMasahiro Yamada }; 129c28adcb5SMasahiro Yamada }; 130c28adcb5SMasahiro Yamada 131b6e5ec20SMasahiro Yamada emmc_pwrseq: emmc-pwrseq { 132b6e5ec20SMasahiro Yamada compatible = "mmc-pwrseq-emmc"; 1338311ca57SMasahiro Yamada reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 134b6e5ec20SMasahiro Yamada }; 135b6e5ec20SMasahiro Yamada 136c28adcb5SMasahiro Yamada timer { 137c28adcb5SMasahiro Yamada compatible = "arm,armv8-timer"; 138c28adcb5SMasahiro Yamada interrupts = <1 13 4>, 139c28adcb5SMasahiro Yamada <1 14 4>, 140c28adcb5SMasahiro Yamada <1 11 4>, 141c28adcb5SMasahiro Yamada <1 10 4>; 142c28adcb5SMasahiro Yamada }; 143c28adcb5SMasahiro Yamada 1444b7d3743SKunihiko Hayashi thermal-zones { 1454b7d3743SKunihiko Hayashi cpu-thermal { 1464b7d3743SKunihiko Hayashi polling-delay-passive = <250>; /* 250ms */ 1474b7d3743SKunihiko Hayashi polling-delay = <1000>; /* 1000ms */ 1484b7d3743SKunihiko Hayashi thermal-sensors = <&pvtctl>; 1494b7d3743SKunihiko Hayashi 1504b7d3743SKunihiko Hayashi trips { 1514b7d3743SKunihiko Hayashi cpu_crit: cpu-crit { 1524b7d3743SKunihiko Hayashi temperature = <110000>; /* 110C */ 1534b7d3743SKunihiko Hayashi hysteresis = <2000>; 1544b7d3743SKunihiko Hayashi type = "critical"; 1554b7d3743SKunihiko Hayashi }; 1564b7d3743SKunihiko Hayashi cpu_alert: cpu-alert { 1574b7d3743SKunihiko Hayashi temperature = <100000>; /* 100C */ 1584b7d3743SKunihiko Hayashi hysteresis = <2000>; 1594b7d3743SKunihiko Hayashi type = "passive"; 1604b7d3743SKunihiko Hayashi }; 1614b7d3743SKunihiko Hayashi }; 1624b7d3743SKunihiko Hayashi 1634b7d3743SKunihiko Hayashi cooling-maps { 1644b7d3743SKunihiko Hayashi map0 { 1654b7d3743SKunihiko Hayashi trip = <&cpu_alert>; 1664b7d3743SKunihiko Hayashi cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1674b7d3743SKunihiko Hayashi <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1684b7d3743SKunihiko Hayashi <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1694b7d3743SKunihiko Hayashi <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1704b7d3743SKunihiko Hayashi }; 1714b7d3743SKunihiko Hayashi }; 1724b7d3743SKunihiko Hayashi }; 1734b7d3743SKunihiko Hayashi }; 1744b7d3743SKunihiko Hayashi 175aa385712SMasahiro Yamada reserved-memory { 176aa385712SMasahiro Yamada #address-cells = <2>; 177aa385712SMasahiro Yamada #size-cells = <2>; 178aa385712SMasahiro Yamada ranges; 179aa385712SMasahiro Yamada 180aa385712SMasahiro Yamada secure-memory@81000000 { 181aa385712SMasahiro Yamada reg = <0x0 0x81000000 0x0 0x01000000>; 182aa385712SMasahiro Yamada no-map; 183aa385712SMasahiro Yamada }; 184aa385712SMasahiro Yamada }; 185aa385712SMasahiro Yamada 186c28adcb5SMasahiro Yamada soc@0 { 187c28adcb5SMasahiro Yamada compatible = "simple-bus"; 188c28adcb5SMasahiro Yamada #address-cells = <1>; 189c28adcb5SMasahiro Yamada #size-cells = <1>; 190c28adcb5SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 191c28adcb5SMasahiro Yamada 192925c5c32SKunihiko Hayashi spi0: spi@54006000 { 193925c5c32SKunihiko Hayashi compatible = "socionext,uniphier-scssi"; 194925c5c32SKunihiko Hayashi status = "disabled"; 195925c5c32SKunihiko Hayashi reg = <0x54006000 0x100>; 1961a13827bSMasahiro Yamada #address-cells = <1>; 1971a13827bSMasahiro Yamada #size-cells = <0>; 198925c5c32SKunihiko Hayashi interrupts = <0 39 4>; 199925c5c32SKunihiko Hayashi pinctrl-names = "default"; 200925c5c32SKunihiko Hayashi pinctrl-0 = <&pinctrl_spi0>; 201925c5c32SKunihiko Hayashi clocks = <&peri_clk 11>; 202925c5c32SKunihiko Hayashi resets = <&peri_rst 11>; 203925c5c32SKunihiko Hayashi }; 204925c5c32SKunihiko Hayashi 205925c5c32SKunihiko Hayashi spi1: spi@54006100 { 206925c5c32SKunihiko Hayashi compatible = "socionext,uniphier-scssi"; 207925c5c32SKunihiko Hayashi status = "disabled"; 208925c5c32SKunihiko Hayashi reg = <0x54006100 0x100>; 2091a13827bSMasahiro Yamada #address-cells = <1>; 2101a13827bSMasahiro Yamada #size-cells = <0>; 211925c5c32SKunihiko Hayashi interrupts = <0 216 4>; 212925c5c32SKunihiko Hayashi pinctrl-names = "default"; 213925c5c32SKunihiko Hayashi pinctrl-0 = <&pinctrl_spi1>; 214fdf9c17bSKunihiko Hayashi clocks = <&peri_clk 12>; 215fdf9c17bSKunihiko Hayashi resets = <&peri_rst 12>; 216925c5c32SKunihiko Hayashi }; 217925c5c32SKunihiko Hayashi 218c28adcb5SMasahiro Yamada serial0: serial@54006800 { 219c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 220c28adcb5SMasahiro Yamada status = "disabled"; 221c28adcb5SMasahiro Yamada reg = <0x54006800 0x40>; 222c28adcb5SMasahiro Yamada interrupts = <0 33 4>; 223c28adcb5SMasahiro Yamada pinctrl-names = "default"; 224c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 225c28adcb5SMasahiro Yamada clocks = <&peri_clk 0>; 22676c48e1eSMasahiro Yamada resets = <&peri_rst 0>; 227c28adcb5SMasahiro Yamada }; 228c28adcb5SMasahiro Yamada 229c28adcb5SMasahiro Yamada serial1: serial@54006900 { 230c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 231c28adcb5SMasahiro Yamada status = "disabled"; 232c28adcb5SMasahiro Yamada reg = <0x54006900 0x40>; 233c28adcb5SMasahiro Yamada interrupts = <0 35 4>; 234c28adcb5SMasahiro Yamada pinctrl-names = "default"; 235c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 236c28adcb5SMasahiro Yamada clocks = <&peri_clk 1>; 23776c48e1eSMasahiro Yamada resets = <&peri_rst 1>; 238c28adcb5SMasahiro Yamada }; 239c28adcb5SMasahiro Yamada 240c28adcb5SMasahiro Yamada serial2: serial@54006a00 { 241c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 242c28adcb5SMasahiro Yamada status = "disabled"; 243c28adcb5SMasahiro Yamada reg = <0x54006a00 0x40>; 244c28adcb5SMasahiro Yamada interrupts = <0 37 4>; 245c28adcb5SMasahiro Yamada pinctrl-names = "default"; 246c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 247c28adcb5SMasahiro Yamada clocks = <&peri_clk 2>; 24876c48e1eSMasahiro Yamada resets = <&peri_rst 2>; 249c28adcb5SMasahiro Yamada }; 250c28adcb5SMasahiro Yamada 251c28adcb5SMasahiro Yamada serial3: serial@54006b00 { 252c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 253c28adcb5SMasahiro Yamada status = "disabled"; 254c28adcb5SMasahiro Yamada reg = <0x54006b00 0x40>; 255c28adcb5SMasahiro Yamada interrupts = <0 177 4>; 256c28adcb5SMasahiro Yamada pinctrl-names = "default"; 257c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 258c28adcb5SMasahiro Yamada clocks = <&peri_clk 3>; 25976c48e1eSMasahiro Yamada resets = <&peri_rst 3>; 260c28adcb5SMasahiro Yamada }; 261c28adcb5SMasahiro Yamada 262277b51e7SMasahiro Yamada gpio: gpio@55000000 { 263277b51e7SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 264277b51e7SMasahiro Yamada reg = <0x55000000 0x200>; 265277b51e7SMasahiro Yamada interrupt-parent = <&aidet>; 266277b51e7SMasahiro Yamada interrupt-controller; 267277b51e7SMasahiro Yamada #interrupt-cells = <2>; 268277b51e7SMasahiro Yamada gpio-controller; 269277b51e7SMasahiro Yamada #gpio-cells = <2>; 270277b51e7SMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 271abb62c46SMasahiro Yamada <&pinctrl 104 0 0>, 272abb62c46SMasahiro Yamada <&pinctrl 168 0 0>; 273277b51e7SMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 274277b51e7SMasahiro Yamada "gpio_range1", 275277b51e7SMasahiro Yamada "gpio_range2"; 276277b51e7SMasahiro Yamada ngpios = <286>; 277277b51e7SMasahiro Yamada socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 278277b51e7SMasahiro Yamada <21 217 3>; 279277b51e7SMasahiro Yamada }; 280277b51e7SMasahiro Yamada 281c28adcb5SMasahiro Yamada i2c0: i2c@58780000 { 282c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 283c28adcb5SMasahiro Yamada status = "disabled"; 284c28adcb5SMasahiro Yamada reg = <0x58780000 0x80>; 285c28adcb5SMasahiro Yamada #address-cells = <1>; 286c28adcb5SMasahiro Yamada #size-cells = <0>; 287c28adcb5SMasahiro Yamada interrupts = <0 41 4>; 288c28adcb5SMasahiro Yamada pinctrl-names = "default"; 289c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 290c28adcb5SMasahiro Yamada clocks = <&peri_clk 4>; 29176c48e1eSMasahiro Yamada resets = <&peri_rst 4>; 292c28adcb5SMasahiro Yamada clock-frequency = <100000>; 293c28adcb5SMasahiro Yamada }; 294c28adcb5SMasahiro Yamada 295c28adcb5SMasahiro Yamada i2c1: i2c@58781000 { 296c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 297c28adcb5SMasahiro Yamada status = "disabled"; 298c28adcb5SMasahiro Yamada reg = <0x58781000 0x80>; 299c28adcb5SMasahiro Yamada #address-cells = <1>; 300c28adcb5SMasahiro Yamada #size-cells = <0>; 301c28adcb5SMasahiro Yamada interrupts = <0 42 4>; 302c28adcb5SMasahiro Yamada pinctrl-names = "default"; 303c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 304c28adcb5SMasahiro Yamada clocks = <&peri_clk 5>; 30576c48e1eSMasahiro Yamada resets = <&peri_rst 5>; 306c28adcb5SMasahiro Yamada clock-frequency = <100000>; 307c28adcb5SMasahiro Yamada }; 308c28adcb5SMasahiro Yamada 309c28adcb5SMasahiro Yamada i2c2: i2c@58782000 { 310c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 311c28adcb5SMasahiro Yamada status = "disabled"; 312c28adcb5SMasahiro Yamada reg = <0x58782000 0x80>; 313c28adcb5SMasahiro Yamada #address-cells = <1>; 314c28adcb5SMasahiro Yamada #size-cells = <0>; 315c28adcb5SMasahiro Yamada interrupts = <0 43 4>; 316c28adcb5SMasahiro Yamada pinctrl-names = "default"; 317c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c2>; 318c28adcb5SMasahiro Yamada clocks = <&peri_clk 6>; 31976c48e1eSMasahiro Yamada resets = <&peri_rst 6>; 320c28adcb5SMasahiro Yamada clock-frequency = <100000>; 321c28adcb5SMasahiro Yamada }; 322c28adcb5SMasahiro Yamada 323c28adcb5SMasahiro Yamada i2c3: i2c@58783000 { 324c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 325c28adcb5SMasahiro Yamada status = "disabled"; 326c28adcb5SMasahiro Yamada reg = <0x58783000 0x80>; 327c28adcb5SMasahiro Yamada #address-cells = <1>; 328c28adcb5SMasahiro Yamada #size-cells = <0>; 329c28adcb5SMasahiro Yamada interrupts = <0 44 4>; 330c28adcb5SMasahiro Yamada pinctrl-names = "default"; 331c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 332c28adcb5SMasahiro Yamada clocks = <&peri_clk 7>; 33376c48e1eSMasahiro Yamada resets = <&peri_rst 7>; 334c28adcb5SMasahiro Yamada clock-frequency = <100000>; 335c28adcb5SMasahiro Yamada }; 336c28adcb5SMasahiro Yamada 337c28adcb5SMasahiro Yamada /* chip-internal connection for HDMI */ 338c28adcb5SMasahiro Yamada i2c6: i2c@58786000 { 339c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 340c28adcb5SMasahiro Yamada reg = <0x58786000 0x80>; 341c28adcb5SMasahiro Yamada #address-cells = <1>; 342c28adcb5SMasahiro Yamada #size-cells = <0>; 343c28adcb5SMasahiro Yamada interrupts = <0 26 4>; 344c28adcb5SMasahiro Yamada clocks = <&peri_clk 10>; 34576c48e1eSMasahiro Yamada resets = <&peri_rst 10>; 346c28adcb5SMasahiro Yamada clock-frequency = <400000>; 347c28adcb5SMasahiro Yamada }; 348c28adcb5SMasahiro Yamada 349c28adcb5SMasahiro Yamada system_bus: system-bus@58c00000 { 350c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 351c28adcb5SMasahiro Yamada status = "disabled"; 352c28adcb5SMasahiro Yamada reg = <0x58c00000 0x400>; 353c28adcb5SMasahiro Yamada #address-cells = <2>; 354c28adcb5SMasahiro Yamada #size-cells = <1>; 355c28adcb5SMasahiro Yamada pinctrl-names = "default"; 356c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 357c28adcb5SMasahiro Yamada }; 358c28adcb5SMasahiro Yamada 359c28adcb5SMasahiro Yamada smpctrl@59801000 { 360c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 361c28adcb5SMasahiro Yamada reg = <0x59801000 0x400>; 362c28adcb5SMasahiro Yamada }; 363c28adcb5SMasahiro Yamada 364c28adcb5SMasahiro Yamada sdctrl@59810000 { 365c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sdctrl", 366c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 367c28adcb5SMasahiro Yamada reg = <0x59810000 0x400>; 368c28adcb5SMasahiro Yamada 369c28adcb5SMasahiro Yamada sd_clk: clock { 370c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-clock"; 371c28adcb5SMasahiro Yamada #clock-cells = <1>; 372c28adcb5SMasahiro Yamada }; 373c28adcb5SMasahiro Yamada 374c28adcb5SMasahiro Yamada sd_rst: reset { 375c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-reset"; 376c28adcb5SMasahiro Yamada #reset-cells = <1>; 377c28adcb5SMasahiro Yamada }; 378c28adcb5SMasahiro Yamada }; 379c28adcb5SMasahiro Yamada 380c28adcb5SMasahiro Yamada perictrl@59820000 { 381c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-perictrl", 382c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 383c28adcb5SMasahiro Yamada reg = <0x59820000 0x200>; 384c28adcb5SMasahiro Yamada 385c28adcb5SMasahiro Yamada peri_clk: clock { 386c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-clock"; 387c28adcb5SMasahiro Yamada #clock-cells = <1>; 388c28adcb5SMasahiro Yamada }; 389c28adcb5SMasahiro Yamada 390c28adcb5SMasahiro Yamada peri_rst: reset { 391c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-reset"; 392c28adcb5SMasahiro Yamada #reset-cells = <1>; 393c28adcb5SMasahiro Yamada }; 394c28adcb5SMasahiro Yamada }; 395c28adcb5SMasahiro Yamada 396bb3f4672SMasahiro Yamada emmc: mmc@5a000000 { 397c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 398c28adcb5SMasahiro Yamada reg = <0x5a000000 0x400>; 399c28adcb5SMasahiro Yamada interrupts = <0 78 4>; 400c28adcb5SMasahiro Yamada pinctrl-names = "default"; 401c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 402c28adcb5SMasahiro Yamada clocks = <&sys_clk 4>; 40376c48e1eSMasahiro Yamada resets = <&sys_rst 4>; 404c28adcb5SMasahiro Yamada bus-width = <8>; 405c28adcb5SMasahiro Yamada mmc-ddr-1_8v; 406c28adcb5SMasahiro Yamada mmc-hs200-1_8v; 407b6e5ec20SMasahiro Yamada mmc-pwrseq = <&emmc_pwrseq>; 408f4e5200fSMasahiro Yamada cdns,phy-input-delay-legacy = <9>; 409c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 410c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 411c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 412c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 413c28adcb5SMasahiro Yamada }; 414c28adcb5SMasahiro Yamada 415bb3f4672SMasahiro Yamada sd: mmc@5a400000 { 41684a9c4d5SMasahiro Yamada compatible = "socionext,uniphier-sd-v3.1.1"; 41784a9c4d5SMasahiro Yamada status = "disabled"; 41884a9c4d5SMasahiro Yamada reg = <0x5a400000 0x800>; 41984a9c4d5SMasahiro Yamada interrupts = <0 76 4>; 42084a9c4d5SMasahiro Yamada pinctrl-names = "default", "uhs"; 42184a9c4d5SMasahiro Yamada pinctrl-0 = <&pinctrl_sd>; 42284a9c4d5SMasahiro Yamada pinctrl-1 = <&pinctrl_sd_uhs>; 42384a9c4d5SMasahiro Yamada clocks = <&sd_clk 0>; 42484a9c4d5SMasahiro Yamada reset-names = "host"; 42584a9c4d5SMasahiro Yamada resets = <&sd_rst 0>; 42684a9c4d5SMasahiro Yamada bus-width = <4>; 42784a9c4d5SMasahiro Yamada cap-sd-highspeed; 42884a9c4d5SMasahiro Yamada sd-uhs-sdr12; 42984a9c4d5SMasahiro Yamada sd-uhs-sdr25; 43084a9c4d5SMasahiro Yamada sd-uhs-sdr50; 43184a9c4d5SMasahiro Yamada }; 43284a9c4d5SMasahiro Yamada 433b076ff8bSKunihiko Hayashi soc_glue: soc-glue@5f800000 { 434c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-soc-glue", 435c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 436c28adcb5SMasahiro Yamada reg = <0x5f800000 0x2000>; 437c28adcb5SMasahiro Yamada 438c28adcb5SMasahiro Yamada pinctrl: pinctrl { 439c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-pinctrl"; 440c28adcb5SMasahiro Yamada }; 441c28adcb5SMasahiro Yamada }; 442c28adcb5SMasahiro Yamada 443f05851e1SKeiji Hayashibara soc-glue@5f900000 { 444f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-pxs3-soc-glue-debug", 445f05851e1SKeiji Hayashibara "simple-mfd"; 446f05851e1SKeiji Hayashibara #address-cells = <1>; 447f05851e1SKeiji Hayashibara #size-cells = <1>; 448f05851e1SKeiji Hayashibara ranges = <0 0x5f900000 0x2000>; 449f05851e1SKeiji Hayashibara 450f05851e1SKeiji Hayashibara efuse@100 { 451f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 452f05851e1SKeiji Hayashibara reg = <0x100 0x28>; 453f05851e1SKeiji Hayashibara }; 454f05851e1SKeiji Hayashibara 455f05851e1SKeiji Hayashibara efuse@200 { 456f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 457f05851e1SKeiji Hayashibara reg = <0x200 0x68>; 458d7b9beb8SKunihiko Hayashi #address-cells = <1>; 459d7b9beb8SKunihiko Hayashi #size-cells = <1>; 460d7b9beb8SKunihiko Hayashi 461d7b9beb8SKunihiko Hayashi /* USB cells */ 462d7b9beb8SKunihiko Hayashi usb_rterm0: trim@54,4 { 463d7b9beb8SKunihiko Hayashi reg = <0x54 1>; 464d7b9beb8SKunihiko Hayashi bits = <4 2>; 465d7b9beb8SKunihiko Hayashi }; 466d7b9beb8SKunihiko Hayashi usb_rterm1: trim@55,4 { 467d7b9beb8SKunihiko Hayashi reg = <0x55 1>; 468d7b9beb8SKunihiko Hayashi bits = <4 2>; 469d7b9beb8SKunihiko Hayashi }; 470d7b9beb8SKunihiko Hayashi usb_rterm2: trim@58,4 { 471d7b9beb8SKunihiko Hayashi reg = <0x58 1>; 472d7b9beb8SKunihiko Hayashi bits = <4 2>; 473d7b9beb8SKunihiko Hayashi }; 474d7b9beb8SKunihiko Hayashi usb_rterm3: trim@59,4 { 475d7b9beb8SKunihiko Hayashi reg = <0x59 1>; 476d7b9beb8SKunihiko Hayashi bits = <4 2>; 477d7b9beb8SKunihiko Hayashi }; 478d7b9beb8SKunihiko Hayashi usb_sel_t0: trim@54,0 { 479d7b9beb8SKunihiko Hayashi reg = <0x54 1>; 480d7b9beb8SKunihiko Hayashi bits = <0 4>; 481d7b9beb8SKunihiko Hayashi }; 482d7b9beb8SKunihiko Hayashi usb_sel_t1: trim@55,0 { 483d7b9beb8SKunihiko Hayashi reg = <0x55 1>; 484d7b9beb8SKunihiko Hayashi bits = <0 4>; 485d7b9beb8SKunihiko Hayashi }; 486d7b9beb8SKunihiko Hayashi usb_sel_t2: trim@58,0 { 487d7b9beb8SKunihiko Hayashi reg = <0x58 1>; 488d7b9beb8SKunihiko Hayashi bits = <0 4>; 489d7b9beb8SKunihiko Hayashi }; 490d7b9beb8SKunihiko Hayashi usb_sel_t3: trim@59,0 { 491d7b9beb8SKunihiko Hayashi reg = <0x59 1>; 492d7b9beb8SKunihiko Hayashi bits = <0 4>; 493d7b9beb8SKunihiko Hayashi }; 494d7b9beb8SKunihiko Hayashi usb_hs_i0: trim@56,0 { 495d7b9beb8SKunihiko Hayashi reg = <0x56 1>; 496d7b9beb8SKunihiko Hayashi bits = <0 4>; 497d7b9beb8SKunihiko Hayashi }; 498d7b9beb8SKunihiko Hayashi usb_hs_i2: trim@5a,0 { 499d7b9beb8SKunihiko Hayashi reg = <0x5a 1>; 500d7b9beb8SKunihiko Hayashi bits = <0 4>; 501d7b9beb8SKunihiko Hayashi }; 502f05851e1SKeiji Hayashibara }; 503f05851e1SKeiji Hayashibara }; 504f05851e1SKeiji Hayashibara 505f03b998dSKunihiko Hayashi xdmac: dma-controller@5fc10000 { 506f03b998dSKunihiko Hayashi compatible = "socionext,uniphier-xdmac"; 507f03b998dSKunihiko Hayashi reg = <0x5fc10000 0x5300>; 508f03b998dSKunihiko Hayashi interrupts = <0 188 4>; 509f03b998dSKunihiko Hayashi dma-channels = <16>; 510f03b998dSKunihiko Hayashi #dma-cells = <2>; 511f03b998dSKunihiko Hayashi }; 512f03b998dSKunihiko Hayashi 5139ddc285bSMasahiro Yamada aidet: interrupt-controller@5fc20000 { 514c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-aidet"; 515c28adcb5SMasahiro Yamada reg = <0x5fc20000 0x200>; 516c28adcb5SMasahiro Yamada interrupt-controller; 517c28adcb5SMasahiro Yamada #interrupt-cells = <2>; 518c28adcb5SMasahiro Yamada }; 519c28adcb5SMasahiro Yamada 520c28adcb5SMasahiro Yamada gic: interrupt-controller@5fe00000 { 521c28adcb5SMasahiro Yamada compatible = "arm,gic-v3"; 522c28adcb5SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 523c28adcb5SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 524c28adcb5SMasahiro Yamada interrupt-controller; 525c28adcb5SMasahiro Yamada #interrupt-cells = <3>; 526c28adcb5SMasahiro Yamada interrupts = <1 9 4>; 527c28adcb5SMasahiro Yamada }; 528c28adcb5SMasahiro Yamada 529c28adcb5SMasahiro Yamada sysctrl@61840000 { 530c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sysctrl", 531c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 532c28adcb5SMasahiro Yamada reg = <0x61840000 0x10000>; 533c28adcb5SMasahiro Yamada 534c28adcb5SMasahiro Yamada sys_clk: clock { 535c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-clock"; 536c28adcb5SMasahiro Yamada #clock-cells = <1>; 537c28adcb5SMasahiro Yamada }; 538c28adcb5SMasahiro Yamada 539c28adcb5SMasahiro Yamada sys_rst: reset { 540c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-reset"; 541c28adcb5SMasahiro Yamada #reset-cells = <1>; 542c28adcb5SMasahiro Yamada }; 543c28adcb5SMasahiro Yamada 544c28adcb5SMasahiro Yamada watchdog { 545c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-wdt"; 546c28adcb5SMasahiro Yamada }; 5474b7d3743SKunihiko Hayashi 548*2dfb62d6SKunihiko Hayashi pvtctl: thermal-sensor { 5494b7d3743SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-thermal"; 5504b7d3743SKunihiko Hayashi interrupts = <0 3 4>; 5514b7d3743SKunihiko Hayashi #thermal-sensor-cells = <0>; 5524b7d3743SKunihiko Hayashi socionext,tmod-calibration = <0x0f22 0x68ee>; 5534b7d3743SKunihiko Hayashi }; 554c28adcb5SMasahiro Yamada }; 555c28adcb5SMasahiro Yamada 556aba054a1SKunihiko Hayashi eth0: ethernet@65000000 { 557aba054a1SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ave4"; 558aba054a1SKunihiko Hayashi status = "disabled"; 559aba054a1SKunihiko Hayashi reg = <0x65000000 0x8500>; 560aba054a1SKunihiko Hayashi interrupts = <0 66 4>; 561aba054a1SKunihiko Hayashi pinctrl-names = "default"; 562aba054a1SKunihiko Hayashi pinctrl-0 = <&pinctrl_ether_rgmii>; 563a34a464dSKunihiko Hayashi clock-names = "ether"; 564aba054a1SKunihiko Hayashi clocks = <&sys_clk 6>; 565a34a464dSKunihiko Hayashi reset-names = "ether"; 566aba054a1SKunihiko Hayashi resets = <&sys_rst 6>; 567dcabb06bSKunihiko Hayashi phy-mode = "rgmii-id"; 568aba054a1SKunihiko Hayashi local-mac-address = [00 00 00 00 00 00]; 569b076ff8bSKunihiko Hayashi socionext,syscon-phy-mode = <&soc_glue 0>; 570aba054a1SKunihiko Hayashi 571aba054a1SKunihiko Hayashi mdio0: mdio { 572aba054a1SKunihiko Hayashi #address-cells = <1>; 573aba054a1SKunihiko Hayashi #size-cells = <0>; 574aba054a1SKunihiko Hayashi }; 575aba054a1SKunihiko Hayashi }; 576aba054a1SKunihiko Hayashi 577aba054a1SKunihiko Hayashi eth1: ethernet@65200000 { 578aba054a1SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ave4"; 579aba054a1SKunihiko Hayashi status = "disabled"; 580aba054a1SKunihiko Hayashi reg = <0x65200000 0x8500>; 581aba054a1SKunihiko Hayashi interrupts = <0 67 4>; 582aba054a1SKunihiko Hayashi pinctrl-names = "default"; 583aba054a1SKunihiko Hayashi pinctrl-0 = <&pinctrl_ether1_rgmii>; 584a34a464dSKunihiko Hayashi clock-names = "ether"; 585aba054a1SKunihiko Hayashi clocks = <&sys_clk 7>; 586a34a464dSKunihiko Hayashi reset-names = "ether"; 587aba054a1SKunihiko Hayashi resets = <&sys_rst 7>; 588dcabb06bSKunihiko Hayashi phy-mode = "rgmii-id"; 589aba054a1SKunihiko Hayashi local-mac-address = [00 00 00 00 00 00]; 590b076ff8bSKunihiko Hayashi socionext,syscon-phy-mode = <&soc_glue 1>; 591aba054a1SKunihiko Hayashi 592aba054a1SKunihiko Hayashi mdio1: mdio { 593aba054a1SKunihiko Hayashi #address-cells = <1>; 594aba054a1SKunihiko Hayashi #size-cells = <0>; 595aba054a1SKunihiko Hayashi }; 596aba054a1SKunihiko Hayashi }; 597aba054a1SKunihiko Hayashi 598d7b9beb8SKunihiko Hayashi usb0: usb@65a00000 { 599d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 600d7b9beb8SKunihiko Hayashi status = "disabled"; 601d7b9beb8SKunihiko Hayashi reg = <0x65a00000 0xcd00>; 602fe17b91aSKunihiko Hayashi interrupt-names = "dwc_usb3"; 603fe17b91aSKunihiko Hayashi interrupts = <0 134 4>; 604d7b9beb8SKunihiko Hayashi pinctrl-names = "default"; 605d7b9beb8SKunihiko Hayashi pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 606d7b9beb8SKunihiko Hayashi clock-names = "ref", "bus_early", "suspend"; 607d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; 608d7b9beb8SKunihiko Hayashi resets = <&usb0_rst 15>; 609d7b9beb8SKunihiko Hayashi phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 610d7b9beb8SKunihiko Hayashi <&usb0_ssphy0>, <&usb0_ssphy1>; 611d7b9beb8SKunihiko Hayashi dr_mode = "host"; 612d7b9beb8SKunihiko Hayashi }; 613d7b9beb8SKunihiko Hayashi 614d7b9beb8SKunihiko Hayashi usb-glue@65b00000 { 615d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-dwc3-glue", 616d7b9beb8SKunihiko Hayashi "simple-mfd"; 617d7b9beb8SKunihiko Hayashi #address-cells = <1>; 618d7b9beb8SKunihiko Hayashi #size-cells = <1>; 619d7b9beb8SKunihiko Hayashi ranges = <0 0x65b00000 0x400>; 620d7b9beb8SKunihiko Hayashi 621d7b9beb8SKunihiko Hayashi usb0_rst: reset@0 { 622d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-reset"; 623d7b9beb8SKunihiko Hayashi reg = <0x0 0x4>; 624d7b9beb8SKunihiko Hayashi #reset-cells = <1>; 625d7b9beb8SKunihiko Hayashi clock-names = "link"; 626d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>; 627d7b9beb8SKunihiko Hayashi reset-names = "link"; 628d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>; 629d7b9beb8SKunihiko Hayashi }; 630d7b9beb8SKunihiko Hayashi 631d7b9beb8SKunihiko Hayashi usb0_vbus0: regulator@100 { 632d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-regulator"; 633d7b9beb8SKunihiko Hayashi reg = <0x100 0x10>; 634d7b9beb8SKunihiko Hayashi clock-names = "link"; 635d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>; 636d7b9beb8SKunihiko Hayashi reset-names = "link"; 637d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>; 638d7b9beb8SKunihiko Hayashi }; 639d7b9beb8SKunihiko Hayashi 640d7b9beb8SKunihiko Hayashi usb0_vbus1: regulator@110 { 641d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-regulator"; 642d7b9beb8SKunihiko Hayashi reg = <0x110 0x10>; 643d7b9beb8SKunihiko Hayashi clock-names = "link"; 644d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>; 645d7b9beb8SKunihiko Hayashi reset-names = "link"; 646d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>; 647d7b9beb8SKunihiko Hayashi }; 648d7b9beb8SKunihiko Hayashi 649d7b9beb8SKunihiko Hayashi usb0_hsphy0: hs-phy@200 { 650d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 651d7b9beb8SKunihiko Hayashi reg = <0x200 0x10>; 652d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 653d7b9beb8SKunihiko Hayashi clock-names = "link", "phy"; 654d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 16>; 655d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 656d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>, <&sys_rst 16>; 657d7b9beb8SKunihiko Hayashi vbus-supply = <&usb0_vbus0>; 658d7b9beb8SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 659d7b9beb8SKunihiko Hayashi nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 660d7b9beb8SKunihiko Hayashi <&usb_hs_i0>; 661d7b9beb8SKunihiko Hayashi }; 662d7b9beb8SKunihiko Hayashi 663d7b9beb8SKunihiko Hayashi usb0_hsphy1: hs-phy@210 { 664d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 665d7b9beb8SKunihiko Hayashi reg = <0x210 0x10>; 666d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 667d7b9beb8SKunihiko Hayashi clock-names = "link", "phy"; 668d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 16>; 669d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 670d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>, <&sys_rst 16>; 671d7b9beb8SKunihiko Hayashi vbus-supply = <&usb0_vbus1>; 672d7b9beb8SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 673d7b9beb8SKunihiko Hayashi nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 674d7b9beb8SKunihiko Hayashi <&usb_hs_i0>; 675d7b9beb8SKunihiko Hayashi }; 676d7b9beb8SKunihiko Hayashi 677d7b9beb8SKunihiko Hayashi usb0_ssphy0: ss-phy@300 { 678d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 679d7b9beb8SKunihiko Hayashi reg = <0x300 0x10>; 680d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 681d7b9beb8SKunihiko Hayashi clock-names = "link", "phy"; 682d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 17>; 683d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 684d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>, <&sys_rst 17>; 685d7b9beb8SKunihiko Hayashi vbus-supply = <&usb0_vbus0>; 686d7b9beb8SKunihiko Hayashi }; 687d7b9beb8SKunihiko Hayashi 688d7b9beb8SKunihiko Hayashi usb0_ssphy1: ss-phy@310 { 689d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 690d7b9beb8SKunihiko Hayashi reg = <0x310 0x10>; 691d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 692d7b9beb8SKunihiko Hayashi clock-names = "link", "phy"; 693d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 18>; 694d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 695d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>, <&sys_rst 18>; 696d7b9beb8SKunihiko Hayashi vbus-supply = <&usb0_vbus1>; 697d7b9beb8SKunihiko Hayashi }; 698d7b9beb8SKunihiko Hayashi }; 699d7b9beb8SKunihiko Hayashi 700d7b9beb8SKunihiko Hayashi usb1: usb@65c00000 { 701d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 702d7b9beb8SKunihiko Hayashi status = "disabled"; 703d7b9beb8SKunihiko Hayashi reg = <0x65c00000 0xcd00>; 704fe17b91aSKunihiko Hayashi interrupt-names = "dwc_usb3"; 705fe17b91aSKunihiko Hayashi interrupts = <0 137 4>; 706d7b9beb8SKunihiko Hayashi pinctrl-names = "default"; 707d7b9beb8SKunihiko Hayashi pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 708d7b9beb8SKunihiko Hayashi clock-names = "ref", "bus_early", "suspend"; 709d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; 710d7b9beb8SKunihiko Hayashi resets = <&usb1_rst 15>; 711d7b9beb8SKunihiko Hayashi phys = <&usb1_hsphy0>, <&usb1_hsphy1>, 712d7b9beb8SKunihiko Hayashi <&usb1_ssphy0>; 713d7b9beb8SKunihiko Hayashi dr_mode = "host"; 714d7b9beb8SKunihiko Hayashi }; 715d7b9beb8SKunihiko Hayashi 716d7b9beb8SKunihiko Hayashi usb-glue@65d00000 { 717d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-dwc3-glue", 718d7b9beb8SKunihiko Hayashi "simple-mfd"; 719d7b9beb8SKunihiko Hayashi #address-cells = <1>; 720d7b9beb8SKunihiko Hayashi #size-cells = <1>; 721d7b9beb8SKunihiko Hayashi ranges = <0 0x65d00000 0x400>; 722d7b9beb8SKunihiko Hayashi 723d7b9beb8SKunihiko Hayashi usb1_rst: reset@0 { 724d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-reset"; 725d7b9beb8SKunihiko Hayashi reg = <0x0 0x4>; 726d7b9beb8SKunihiko Hayashi #reset-cells = <1>; 727d7b9beb8SKunihiko Hayashi clock-names = "link"; 728d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>; 729d7b9beb8SKunihiko Hayashi reset-names = "link"; 730d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>; 731d7b9beb8SKunihiko Hayashi }; 732d7b9beb8SKunihiko Hayashi 733d7b9beb8SKunihiko Hayashi usb1_vbus0: regulator@100 { 734d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-regulator"; 735d7b9beb8SKunihiko Hayashi reg = <0x100 0x10>; 736d7b9beb8SKunihiko Hayashi clock-names = "link"; 737d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>; 738d7b9beb8SKunihiko Hayashi reset-names = "link"; 739d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>; 740d7b9beb8SKunihiko Hayashi }; 741d7b9beb8SKunihiko Hayashi 742d7b9beb8SKunihiko Hayashi usb1_vbus1: regulator@110 { 743d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-regulator"; 744d7b9beb8SKunihiko Hayashi reg = <0x110 0x10>; 745d7b9beb8SKunihiko Hayashi clock-names = "link"; 746d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>; 747d7b9beb8SKunihiko Hayashi reset-names = "link"; 748d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>; 749d7b9beb8SKunihiko Hayashi }; 750d7b9beb8SKunihiko Hayashi 751d7b9beb8SKunihiko Hayashi usb1_hsphy0: hs-phy@200 { 752d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 753d7b9beb8SKunihiko Hayashi reg = <0x200 0x10>; 754d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 755d7b9beb8SKunihiko Hayashi clock-names = "link", "phy", "phy-ext"; 756d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>, <&sys_clk 20>, 757d7b9beb8SKunihiko Hayashi <&sys_clk 14>; 758d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 759d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>, <&sys_rst 20>; 760d7b9beb8SKunihiko Hayashi vbus-supply = <&usb1_vbus0>; 761d7b9beb8SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 762d7b9beb8SKunihiko Hayashi nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 763d7b9beb8SKunihiko Hayashi <&usb_hs_i2>; 764d7b9beb8SKunihiko Hayashi }; 765d7b9beb8SKunihiko Hayashi 766d7b9beb8SKunihiko Hayashi usb1_hsphy1: hs-phy@210 { 767d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 768d7b9beb8SKunihiko Hayashi reg = <0x210 0x10>; 769d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 770d7b9beb8SKunihiko Hayashi clock-names = "link", "phy", "phy-ext"; 771d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>, <&sys_clk 20>, 772d7b9beb8SKunihiko Hayashi <&sys_clk 14>; 773d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 774d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>, <&sys_rst 20>; 775d7b9beb8SKunihiko Hayashi vbus-supply = <&usb1_vbus1>; 776d7b9beb8SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 777d7b9beb8SKunihiko Hayashi nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 778d7b9beb8SKunihiko Hayashi <&usb_hs_i2>; 779d7b9beb8SKunihiko Hayashi }; 780d7b9beb8SKunihiko Hayashi 781d7b9beb8SKunihiko Hayashi usb1_ssphy0: ss-phy@300 { 782d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 783d7b9beb8SKunihiko Hayashi reg = <0x300 0x10>; 784d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 785d7b9beb8SKunihiko Hayashi clock-names = "link", "phy", "phy-ext"; 786d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>, <&sys_clk 21>, 787d7b9beb8SKunihiko Hayashi <&sys_clk 14>; 788d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 789d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>, <&sys_rst 21>; 790d7b9beb8SKunihiko Hayashi vbus-supply = <&usb1_vbus0>; 791d7b9beb8SKunihiko Hayashi }; 792d7b9beb8SKunihiko Hayashi }; 793d7b9beb8SKunihiko Hayashi 79432dfc773SKunihiko Hayashi pcie: pcie@66000000 { 79532dfc773SKunihiko Hayashi compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; 79632dfc773SKunihiko Hayashi status = "disabled"; 79732dfc773SKunihiko Hayashi reg-names = "dbi", "link", "config"; 79832dfc773SKunihiko Hayashi reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 79932dfc773SKunihiko Hayashi <0x2fff0000 0x10000>; 80032dfc773SKunihiko Hayashi #address-cells = <3>; 80132dfc773SKunihiko Hayashi #size-cells = <2>; 80232dfc773SKunihiko Hayashi clocks = <&sys_clk 24>; 80332dfc773SKunihiko Hayashi resets = <&sys_rst 24>; 80432dfc773SKunihiko Hayashi num-lanes = <1>; 80532dfc773SKunihiko Hayashi num-viewport = <1>; 80632dfc773SKunihiko Hayashi bus-range = <0x0 0xff>; 80732dfc773SKunihiko Hayashi device_type = "pci"; 80832dfc773SKunihiko Hayashi ranges = 80932dfc773SKunihiko Hayashi /* downstream I/O */ 81032dfc773SKunihiko Hayashi <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 81132dfc773SKunihiko Hayashi /* non-prefetchable memory */ 81232dfc773SKunihiko Hayashi <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 81332dfc773SKunihiko Hayashi #interrupt-cells = <1>; 81432dfc773SKunihiko Hayashi interrupt-names = "dma", "msi"; 81532dfc773SKunihiko Hayashi interrupts = <0 224 4>, <0 225 4>; 81632dfc773SKunihiko Hayashi interrupt-map-mask = <0 0 0 7>; 81732dfc773SKunihiko Hayashi interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 81832dfc773SKunihiko Hayashi <0 0 0 2 &pcie_intc 1>, /* INTB */ 81932dfc773SKunihiko Hayashi <0 0 0 3 &pcie_intc 2>, /* INTC */ 82032dfc773SKunihiko Hayashi <0 0 0 4 &pcie_intc 3>; /* INTD */ 82132dfc773SKunihiko Hayashi phy-names = "pcie-phy"; 82232dfc773SKunihiko Hayashi phys = <&pcie_phy>; 82332dfc773SKunihiko Hayashi 82432dfc773SKunihiko Hayashi pcie_intc: legacy-interrupt-controller { 82532dfc773SKunihiko Hayashi interrupt-controller; 82632dfc773SKunihiko Hayashi #interrupt-cells = <1>; 82732dfc773SKunihiko Hayashi interrupt-parent = <&gic>; 82832dfc773SKunihiko Hayashi interrupts = <0 226 4>; 82932dfc773SKunihiko Hayashi }; 83032dfc773SKunihiko Hayashi }; 83132dfc773SKunihiko Hayashi 83232dfc773SKunihiko Hayashi pcie_phy: phy@66038000 { 83332dfc773SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-pcie-phy"; 83432dfc773SKunihiko Hayashi reg = <0x66038000 0x4000>; 83532dfc773SKunihiko Hayashi #phy-cells = <0>; 836e6bd81a2SKunihiko Hayashi clock-names = "link"; 83732dfc773SKunihiko Hayashi clocks = <&sys_clk 24>; 838e6bd81a2SKunihiko Hayashi reset-names = "link"; 83932dfc773SKunihiko Hayashi resets = <&sys_rst 24>; 84032dfc773SKunihiko Hayashi socionext,syscon = <&soc_glue>; 84132dfc773SKunihiko Hayashi }; 84232dfc773SKunihiko Hayashi 843fcb0e53cSMasahiro Yamada nand: nand-controller@68000000 { 844c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 845c28adcb5SMasahiro Yamada status = "disabled"; 846c28adcb5SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 847c28adcb5SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 84853c580c1SMasahiro Yamada #address-cells = <1>; 84953c580c1SMasahiro Yamada #size-cells = <0>; 850c28adcb5SMasahiro Yamada interrupts = <0 65 4>; 851c28adcb5SMasahiro Yamada pinctrl-names = "default"; 852c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 853bae120f8SMasahiro Yamada clock-names = "nand", "nand_x", "ecc"; 854bae120f8SMasahiro Yamada clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 855e98d5023SMasahiro Yamada reset-names = "nand", "reg"; 856e98d5023SMasahiro Yamada resets = <&sys_rst 2>, <&sys_rst 2>; 857c28adcb5SMasahiro Yamada }; 858c28adcb5SMasahiro Yamada }; 859c28adcb5SMasahiro Yamada}; 860c28adcb5SMasahiro Yamada 861c28adcb5SMasahiro Yamada#include "uniphier-pinctrl.dtsi" 862