105f7e3d1SMasahiro Yamada// SPDX-License-Identifier: GPL-2.0+ OR MIT 205f7e3d1SMasahiro Yamada// 305f7e3d1SMasahiro Yamada// Device Tree Source for UniPhier PXs3 SoC 405f7e3d1SMasahiro Yamada// 505f7e3d1SMasahiro Yamada// Copyright (C) 2017 Socionext Inc. 605f7e3d1SMasahiro Yamada// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7c28adcb5SMasahiro Yamada 8b6e5ec20SMasahiro Yamada#include <dt-bindings/gpio/gpio.h> 98311ca57SMasahiro Yamada#include <dt-bindings/gpio/uniphier-gpio.h> 105ba95e8eSKunihiko Hayashi#include <dt-bindings/interrupt-controller/arm-gic.h> 114b7d3743SKunihiko Hayashi#include <dt-bindings/thermal/thermal.h> 12b6e5ec20SMasahiro Yamada 13c28adcb5SMasahiro Yamada/ { 14c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3"; 15c28adcb5SMasahiro Yamada #address-cells = <2>; 16c28adcb5SMasahiro Yamada #size-cells = <2>; 17c28adcb5SMasahiro Yamada interrupt-parent = <&gic>; 18c28adcb5SMasahiro Yamada 19c28adcb5SMasahiro Yamada cpus { 20c28adcb5SMasahiro Yamada #address-cells = <2>; 21c28adcb5SMasahiro Yamada #size-cells = <0>; 22c28adcb5SMasahiro Yamada 23c28adcb5SMasahiro Yamada cpu-map { 24c28adcb5SMasahiro Yamada cluster0 { 25c28adcb5SMasahiro Yamada core0 { 26c28adcb5SMasahiro Yamada cpu = <&cpu0>; 27c28adcb5SMasahiro Yamada }; 28c28adcb5SMasahiro Yamada core1 { 29c28adcb5SMasahiro Yamada cpu = <&cpu1>; 30c28adcb5SMasahiro Yamada }; 31c28adcb5SMasahiro Yamada core2 { 32c28adcb5SMasahiro Yamada cpu = <&cpu2>; 33c28adcb5SMasahiro Yamada }; 34c28adcb5SMasahiro Yamada core3 { 35c28adcb5SMasahiro Yamada cpu = <&cpu3>; 36c28adcb5SMasahiro Yamada }; 37c28adcb5SMasahiro Yamada }; 38c28adcb5SMasahiro Yamada }; 39c28adcb5SMasahiro Yamada 40c28adcb5SMasahiro Yamada cpu0: cpu@0 { 41c28adcb5SMasahiro Yamada device_type = "cpu"; 4231af04cdSRob Herring compatible = "arm,cortex-a53"; 43c28adcb5SMasahiro Yamada reg = <0 0x000>; 44c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 45c28adcb5SMasahiro Yamada enable-method = "psci"; 465381a96cSKunihiko Hayashi next-level-cache = <&l2>; 47c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 484b7d3743SKunihiko Hayashi #cooling-cells = <2>; 49c28adcb5SMasahiro Yamada }; 50c28adcb5SMasahiro Yamada 51c28adcb5SMasahiro Yamada cpu1: cpu@1 { 52c28adcb5SMasahiro Yamada device_type = "cpu"; 5331af04cdSRob Herring compatible = "arm,cortex-a53"; 54c28adcb5SMasahiro Yamada reg = <0 0x001>; 55c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 56c28adcb5SMasahiro Yamada enable-method = "psci"; 575381a96cSKunihiko Hayashi next-level-cache = <&l2>; 58c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 594b7d3743SKunihiko Hayashi #cooling-cells = <2>; 60c28adcb5SMasahiro Yamada }; 61c28adcb5SMasahiro Yamada 62c28adcb5SMasahiro Yamada cpu2: cpu@2 { 63c28adcb5SMasahiro Yamada device_type = "cpu"; 6431af04cdSRob Herring compatible = "arm,cortex-a53"; 65c28adcb5SMasahiro Yamada reg = <0 0x002>; 66c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 67c28adcb5SMasahiro Yamada enable-method = "psci"; 685381a96cSKunihiko Hayashi next-level-cache = <&l2>; 69c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 704b7d3743SKunihiko Hayashi #cooling-cells = <2>; 71c28adcb5SMasahiro Yamada }; 72c28adcb5SMasahiro Yamada 73c28adcb5SMasahiro Yamada cpu3: cpu@3 { 74c28adcb5SMasahiro Yamada device_type = "cpu"; 7531af04cdSRob Herring compatible = "arm,cortex-a53"; 76c28adcb5SMasahiro Yamada reg = <0 0x003>; 77c28adcb5SMasahiro Yamada clocks = <&sys_clk 33>; 78c28adcb5SMasahiro Yamada enable-method = "psci"; 795381a96cSKunihiko Hayashi next-level-cache = <&l2>; 80c28adcb5SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 814b7d3743SKunihiko Hayashi #cooling-cells = <2>; 82c28adcb5SMasahiro Yamada }; 835381a96cSKunihiko Hayashi 845381a96cSKunihiko Hayashi l2: l2-cache { 855381a96cSKunihiko Hayashi compatible = "cache"; 865381a96cSKunihiko Hayashi }; 87c28adcb5SMasahiro Yamada }; 88c28adcb5SMasahiro Yamada 899cd7d03fSMasahiro Yamada cluster0_opp: opp-table { 90c28adcb5SMasahiro Yamada compatible = "operating-points-v2"; 91c28adcb5SMasahiro Yamada opp-shared; 92c28adcb5SMasahiro Yamada 93c28adcb5SMasahiro Yamada opp-250000000 { 94c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 95c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 96c28adcb5SMasahiro Yamada }; 97c28adcb5SMasahiro Yamada opp-325000000 { 98c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <325000000>; 99c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 100c28adcb5SMasahiro Yamada }; 101c28adcb5SMasahiro Yamada opp-500000000 { 102c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 103c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 104c28adcb5SMasahiro Yamada }; 105c28adcb5SMasahiro Yamada opp-650000000 { 106c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <650000000>; 107c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 108c28adcb5SMasahiro Yamada }; 109c28adcb5SMasahiro Yamada opp-666667000 { 110c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 111c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 112c28adcb5SMasahiro Yamada }; 113c28adcb5SMasahiro Yamada opp-866667000 { 114c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <866667000>; 115c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 116c28adcb5SMasahiro Yamada }; 117c28adcb5SMasahiro Yamada opp-1000000000 { 118c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 119c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 120c28adcb5SMasahiro Yamada }; 121c28adcb5SMasahiro Yamada opp-1300000000 { 122c28adcb5SMasahiro Yamada opp-hz = /bits/ 64 <1300000000>; 123c28adcb5SMasahiro Yamada clock-latency-ns = <300>; 124c28adcb5SMasahiro Yamada }; 125c28adcb5SMasahiro Yamada }; 126c28adcb5SMasahiro Yamada 127c28adcb5SMasahiro Yamada psci { 128c28adcb5SMasahiro Yamada compatible = "arm,psci-1.0"; 129c28adcb5SMasahiro Yamada method = "smc"; 130c28adcb5SMasahiro Yamada }; 131c28adcb5SMasahiro Yamada 132c28adcb5SMasahiro Yamada clocks { 133c28adcb5SMasahiro Yamada refclk: ref { 134c28adcb5SMasahiro Yamada compatible = "fixed-clock"; 135c28adcb5SMasahiro Yamada #clock-cells = <0>; 136c28adcb5SMasahiro Yamada clock-frequency = <25000000>; 137c28adcb5SMasahiro Yamada }; 138c28adcb5SMasahiro Yamada }; 139c28adcb5SMasahiro Yamada 140b6e5ec20SMasahiro Yamada emmc_pwrseq: emmc-pwrseq { 141b6e5ec20SMasahiro Yamada compatible = "mmc-pwrseq-emmc"; 1428311ca57SMasahiro Yamada reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 143b6e5ec20SMasahiro Yamada }; 144b6e5ec20SMasahiro Yamada 145c28adcb5SMasahiro Yamada timer { 146c28adcb5SMasahiro Yamada compatible = "arm,armv8-timer"; 1475ba95e8eSKunihiko Hayashi interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 1485ba95e8eSKunihiko Hayashi <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 1495ba95e8eSKunihiko Hayashi <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 1505ba95e8eSKunihiko Hayashi <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 151c28adcb5SMasahiro Yamada }; 152c28adcb5SMasahiro Yamada 1534b7d3743SKunihiko Hayashi thermal-zones { 1544b7d3743SKunihiko Hayashi cpu-thermal { 1554b7d3743SKunihiko Hayashi polling-delay-passive = <250>; /* 250ms */ 1564b7d3743SKunihiko Hayashi polling-delay = <1000>; /* 1000ms */ 1574b7d3743SKunihiko Hayashi thermal-sensors = <&pvtctl>; 1584b7d3743SKunihiko Hayashi 1594b7d3743SKunihiko Hayashi trips { 1604b7d3743SKunihiko Hayashi cpu_crit: cpu-crit { 1614b7d3743SKunihiko Hayashi temperature = <110000>; /* 110C */ 1624b7d3743SKunihiko Hayashi hysteresis = <2000>; 1634b7d3743SKunihiko Hayashi type = "critical"; 1644b7d3743SKunihiko Hayashi }; 1654b7d3743SKunihiko Hayashi cpu_alert: cpu-alert { 1664b7d3743SKunihiko Hayashi temperature = <100000>; /* 100C */ 1674b7d3743SKunihiko Hayashi hysteresis = <2000>; 1684b7d3743SKunihiko Hayashi type = "passive"; 1694b7d3743SKunihiko Hayashi }; 1704b7d3743SKunihiko Hayashi }; 1714b7d3743SKunihiko Hayashi 1724b7d3743SKunihiko Hayashi cooling-maps { 1734b7d3743SKunihiko Hayashi map0 { 1744b7d3743SKunihiko Hayashi trip = <&cpu_alert>; 1754b7d3743SKunihiko Hayashi cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1764b7d3743SKunihiko Hayashi <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1774b7d3743SKunihiko Hayashi <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1784b7d3743SKunihiko Hayashi <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1794b7d3743SKunihiko Hayashi }; 1804b7d3743SKunihiko Hayashi }; 1814b7d3743SKunihiko Hayashi }; 1824b7d3743SKunihiko Hayashi }; 1834b7d3743SKunihiko Hayashi 184aa385712SMasahiro Yamada reserved-memory { 185aa385712SMasahiro Yamada #address-cells = <2>; 186aa385712SMasahiro Yamada #size-cells = <2>; 187aa385712SMasahiro Yamada ranges; 188aa385712SMasahiro Yamada 189aa385712SMasahiro Yamada secure-memory@81000000 { 190aa385712SMasahiro Yamada reg = <0x0 0x81000000 0x0 0x01000000>; 191aa385712SMasahiro Yamada no-map; 192aa385712SMasahiro Yamada }; 193aa385712SMasahiro Yamada }; 194aa385712SMasahiro Yamada 195c28adcb5SMasahiro Yamada soc@0 { 196c28adcb5SMasahiro Yamada compatible = "simple-bus"; 197c28adcb5SMasahiro Yamada #address-cells = <1>; 198c28adcb5SMasahiro Yamada #size-cells = <1>; 199c28adcb5SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 200c28adcb5SMasahiro Yamada 201925c5c32SKunihiko Hayashi spi0: spi@54006000 { 202925c5c32SKunihiko Hayashi compatible = "socionext,uniphier-scssi"; 203925c5c32SKunihiko Hayashi status = "disabled"; 204925c5c32SKunihiko Hayashi reg = <0x54006000 0x100>; 2051a13827bSMasahiro Yamada #address-cells = <1>; 2061a13827bSMasahiro Yamada #size-cells = <0>; 2075ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 208925c5c32SKunihiko Hayashi pinctrl-names = "default"; 209925c5c32SKunihiko Hayashi pinctrl-0 = <&pinctrl_spi0>; 210925c5c32SKunihiko Hayashi clocks = <&peri_clk 11>; 211925c5c32SKunihiko Hayashi resets = <&peri_rst 11>; 212925c5c32SKunihiko Hayashi }; 213925c5c32SKunihiko Hayashi 214925c5c32SKunihiko Hayashi spi1: spi@54006100 { 215925c5c32SKunihiko Hayashi compatible = "socionext,uniphier-scssi"; 216925c5c32SKunihiko Hayashi status = "disabled"; 217925c5c32SKunihiko Hayashi reg = <0x54006100 0x100>; 2181a13827bSMasahiro Yamada #address-cells = <1>; 2191a13827bSMasahiro Yamada #size-cells = <0>; 2205ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 221925c5c32SKunihiko Hayashi pinctrl-names = "default"; 222925c5c32SKunihiko Hayashi pinctrl-0 = <&pinctrl_spi1>; 223fdf9c17bSKunihiko Hayashi clocks = <&peri_clk 12>; 224fdf9c17bSKunihiko Hayashi resets = <&peri_rst 12>; 225925c5c32SKunihiko Hayashi }; 226925c5c32SKunihiko Hayashi 227c28adcb5SMasahiro Yamada serial0: serial@54006800 { 228c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 229c28adcb5SMasahiro Yamada status = "disabled"; 230c28adcb5SMasahiro Yamada reg = <0x54006800 0x40>; 2315ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 232c28adcb5SMasahiro Yamada pinctrl-names = "default"; 233c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 234c28adcb5SMasahiro Yamada clocks = <&peri_clk 0>; 23576c48e1eSMasahiro Yamada resets = <&peri_rst 0>; 236c28adcb5SMasahiro Yamada }; 237c28adcb5SMasahiro Yamada 238c28adcb5SMasahiro Yamada serial1: serial@54006900 { 239c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 240c28adcb5SMasahiro Yamada status = "disabled"; 241c28adcb5SMasahiro Yamada reg = <0x54006900 0x40>; 2425ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 243c28adcb5SMasahiro Yamada pinctrl-names = "default"; 244c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 245c28adcb5SMasahiro Yamada clocks = <&peri_clk 1>; 24676c48e1eSMasahiro Yamada resets = <&peri_rst 1>; 247c28adcb5SMasahiro Yamada }; 248c28adcb5SMasahiro Yamada 249c28adcb5SMasahiro Yamada serial2: serial@54006a00 { 250c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 251c28adcb5SMasahiro Yamada status = "disabled"; 252c28adcb5SMasahiro Yamada reg = <0x54006a00 0x40>; 2535ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 254c28adcb5SMasahiro Yamada pinctrl-names = "default"; 255c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 256c28adcb5SMasahiro Yamada clocks = <&peri_clk 2>; 25776c48e1eSMasahiro Yamada resets = <&peri_rst 2>; 258c28adcb5SMasahiro Yamada }; 259c28adcb5SMasahiro Yamada 260c28adcb5SMasahiro Yamada serial3: serial@54006b00 { 261c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-uart"; 262c28adcb5SMasahiro Yamada status = "disabled"; 263c28adcb5SMasahiro Yamada reg = <0x54006b00 0x40>; 2645ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 265c28adcb5SMasahiro Yamada pinctrl-names = "default"; 266c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 267c28adcb5SMasahiro Yamada clocks = <&peri_clk 3>; 26876c48e1eSMasahiro Yamada resets = <&peri_rst 3>; 269c28adcb5SMasahiro Yamada }; 270c28adcb5SMasahiro Yamada 271277b51e7SMasahiro Yamada gpio: gpio@55000000 { 272277b51e7SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 273277b51e7SMasahiro Yamada reg = <0x55000000 0x200>; 274277b51e7SMasahiro Yamada interrupt-parent = <&aidet>; 275277b51e7SMasahiro Yamada interrupt-controller; 276277b51e7SMasahiro Yamada #interrupt-cells = <2>; 277277b51e7SMasahiro Yamada gpio-controller; 278277b51e7SMasahiro Yamada #gpio-cells = <2>; 279277b51e7SMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 280abb62c46SMasahiro Yamada <&pinctrl 104 0 0>, 281abb62c46SMasahiro Yamada <&pinctrl 168 0 0>; 282277b51e7SMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 283277b51e7SMasahiro Yamada "gpio_range1", 284277b51e7SMasahiro Yamada "gpio_range2"; 285277b51e7SMasahiro Yamada ngpios = <286>; 286277b51e7SMasahiro Yamada socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 287277b51e7SMasahiro Yamada <21 217 3>; 288277b51e7SMasahiro Yamada }; 289277b51e7SMasahiro Yamada 290c28adcb5SMasahiro Yamada i2c0: i2c@58780000 { 291c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 292c28adcb5SMasahiro Yamada status = "disabled"; 293c28adcb5SMasahiro Yamada reg = <0x58780000 0x80>; 294c28adcb5SMasahiro Yamada #address-cells = <1>; 295c28adcb5SMasahiro Yamada #size-cells = <0>; 2965ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 297c28adcb5SMasahiro Yamada pinctrl-names = "default"; 298c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 299c28adcb5SMasahiro Yamada clocks = <&peri_clk 4>; 30076c48e1eSMasahiro Yamada resets = <&peri_rst 4>; 301c28adcb5SMasahiro Yamada clock-frequency = <100000>; 302c28adcb5SMasahiro Yamada }; 303c28adcb5SMasahiro Yamada 304c28adcb5SMasahiro Yamada i2c1: i2c@58781000 { 305c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 306c28adcb5SMasahiro Yamada status = "disabled"; 307c28adcb5SMasahiro Yamada reg = <0x58781000 0x80>; 308c28adcb5SMasahiro Yamada #address-cells = <1>; 309c28adcb5SMasahiro Yamada #size-cells = <0>; 3105ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 311c28adcb5SMasahiro Yamada pinctrl-names = "default"; 312c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 313c28adcb5SMasahiro Yamada clocks = <&peri_clk 5>; 31476c48e1eSMasahiro Yamada resets = <&peri_rst 5>; 315c28adcb5SMasahiro Yamada clock-frequency = <100000>; 316c28adcb5SMasahiro Yamada }; 317c28adcb5SMasahiro Yamada 318c28adcb5SMasahiro Yamada i2c2: i2c@58782000 { 319c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 320c28adcb5SMasahiro Yamada status = "disabled"; 321c28adcb5SMasahiro Yamada reg = <0x58782000 0x80>; 322c28adcb5SMasahiro Yamada #address-cells = <1>; 323c28adcb5SMasahiro Yamada #size-cells = <0>; 3245ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 325c28adcb5SMasahiro Yamada pinctrl-names = "default"; 326c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c2>; 327c28adcb5SMasahiro Yamada clocks = <&peri_clk 6>; 32876c48e1eSMasahiro Yamada resets = <&peri_rst 6>; 329c28adcb5SMasahiro Yamada clock-frequency = <100000>; 330c28adcb5SMasahiro Yamada }; 331c28adcb5SMasahiro Yamada 332c28adcb5SMasahiro Yamada i2c3: i2c@58783000 { 333c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 334c28adcb5SMasahiro Yamada status = "disabled"; 335c28adcb5SMasahiro Yamada reg = <0x58783000 0x80>; 336c28adcb5SMasahiro Yamada #address-cells = <1>; 337c28adcb5SMasahiro Yamada #size-cells = <0>; 3385ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 339c28adcb5SMasahiro Yamada pinctrl-names = "default"; 340c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 341c28adcb5SMasahiro Yamada clocks = <&peri_clk 7>; 34276c48e1eSMasahiro Yamada resets = <&peri_rst 7>; 343c28adcb5SMasahiro Yamada clock-frequency = <100000>; 344c28adcb5SMasahiro Yamada }; 345c28adcb5SMasahiro Yamada 346c28adcb5SMasahiro Yamada /* chip-internal connection for HDMI */ 347c28adcb5SMasahiro Yamada i2c6: i2c@58786000 { 348c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 349c28adcb5SMasahiro Yamada reg = <0x58786000 0x80>; 350c28adcb5SMasahiro Yamada #address-cells = <1>; 351c28adcb5SMasahiro Yamada #size-cells = <0>; 3525ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 353c28adcb5SMasahiro Yamada clocks = <&peri_clk 10>; 35476c48e1eSMasahiro Yamada resets = <&peri_rst 10>; 355c28adcb5SMasahiro Yamada clock-frequency = <400000>; 356c28adcb5SMasahiro Yamada }; 357c28adcb5SMasahiro Yamada 358c28adcb5SMasahiro Yamada system_bus: system-bus@58c00000 { 359c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 360c28adcb5SMasahiro Yamada status = "disabled"; 361c28adcb5SMasahiro Yamada reg = <0x58c00000 0x400>; 362c28adcb5SMasahiro Yamada #address-cells = <2>; 363c28adcb5SMasahiro Yamada #size-cells = <1>; 364c28adcb5SMasahiro Yamada pinctrl-names = "default"; 365c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 366c28adcb5SMasahiro Yamada }; 367c28adcb5SMasahiro Yamada 368c28adcb5SMasahiro Yamada smpctrl@59801000 { 369c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 370c28adcb5SMasahiro Yamada reg = <0x59801000 0x400>; 371c28adcb5SMasahiro Yamada }; 372c28adcb5SMasahiro Yamada 373*a8d3f2d9SKunihiko Hayashi sdctrl: syscon@59810000 { 374c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sdctrl", 375c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 376c28adcb5SMasahiro Yamada reg = <0x59810000 0x400>; 377c28adcb5SMasahiro Yamada 3785ebfa90bSKunihiko Hayashi sd_clk: clock-controller { 379c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-clock"; 380c28adcb5SMasahiro Yamada #clock-cells = <1>; 381c28adcb5SMasahiro Yamada }; 382c28adcb5SMasahiro Yamada 3835ebfa90bSKunihiko Hayashi sd_rst: reset-controller { 384c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sd-reset"; 385c28adcb5SMasahiro Yamada #reset-cells = <1>; 386c28adcb5SMasahiro Yamada }; 387c28adcb5SMasahiro Yamada }; 388c28adcb5SMasahiro Yamada 3895ebfa90bSKunihiko Hayashi syscon@59820000 { 390c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-perictrl", 391c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 392c28adcb5SMasahiro Yamada reg = <0x59820000 0x200>; 393c28adcb5SMasahiro Yamada 3945ebfa90bSKunihiko Hayashi peri_clk: clock-controller { 395c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-clock"; 396c28adcb5SMasahiro Yamada #clock-cells = <1>; 397c28adcb5SMasahiro Yamada }; 398c28adcb5SMasahiro Yamada 3995ebfa90bSKunihiko Hayashi peri_rst: reset-controller { 400c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-peri-reset"; 401c28adcb5SMasahiro Yamada #reset-cells = <1>; 402c28adcb5SMasahiro Yamada }; 403c28adcb5SMasahiro Yamada }; 404c28adcb5SMasahiro Yamada 405bb3f4672SMasahiro Yamada emmc: mmc@5a000000 { 406c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 407c28adcb5SMasahiro Yamada reg = <0x5a000000 0x400>; 4085ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 409c28adcb5SMasahiro Yamada pinctrl-names = "default"; 410c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 411c28adcb5SMasahiro Yamada clocks = <&sys_clk 4>; 41276c48e1eSMasahiro Yamada resets = <&sys_rst 4>; 413c28adcb5SMasahiro Yamada bus-width = <8>; 414c28adcb5SMasahiro Yamada mmc-ddr-1_8v; 415c28adcb5SMasahiro Yamada mmc-hs200-1_8v; 416b6e5ec20SMasahiro Yamada mmc-pwrseq = <&emmc_pwrseq>; 417f4e5200fSMasahiro Yamada cdns,phy-input-delay-legacy = <9>; 418c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 419c28adcb5SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 420c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 421c28adcb5SMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 422c28adcb5SMasahiro Yamada }; 423c28adcb5SMasahiro Yamada 424bb3f4672SMasahiro Yamada sd: mmc@5a400000 { 42584a9c4d5SMasahiro Yamada compatible = "socionext,uniphier-sd-v3.1.1"; 42684a9c4d5SMasahiro Yamada status = "disabled"; 42784a9c4d5SMasahiro Yamada reg = <0x5a400000 0x800>; 4285ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 42984a9c4d5SMasahiro Yamada pinctrl-names = "default", "uhs"; 43084a9c4d5SMasahiro Yamada pinctrl-0 = <&pinctrl_sd>; 43184a9c4d5SMasahiro Yamada pinctrl-1 = <&pinctrl_sd_uhs>; 43284a9c4d5SMasahiro Yamada clocks = <&sd_clk 0>; 43384a9c4d5SMasahiro Yamada reset-names = "host"; 43484a9c4d5SMasahiro Yamada resets = <&sd_rst 0>; 43584a9c4d5SMasahiro Yamada bus-width = <4>; 43684a9c4d5SMasahiro Yamada cap-sd-highspeed; 43784a9c4d5SMasahiro Yamada sd-uhs-sdr12; 43884a9c4d5SMasahiro Yamada sd-uhs-sdr25; 43984a9c4d5SMasahiro Yamada sd-uhs-sdr50; 440*a8d3f2d9SKunihiko Hayashi socionext,syscon-uhs-mode = <&sdctrl 0>; 44184a9c4d5SMasahiro Yamada }; 44284a9c4d5SMasahiro Yamada 4435ebfa90bSKunihiko Hayashi soc_glue: syscon@5f800000 { 444c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-soc-glue", 445c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 446c28adcb5SMasahiro Yamada reg = <0x5f800000 0x2000>; 447c28adcb5SMasahiro Yamada 448c28adcb5SMasahiro Yamada pinctrl: pinctrl { 449c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-pinctrl"; 450c28adcb5SMasahiro Yamada }; 451c28adcb5SMasahiro Yamada }; 452c28adcb5SMasahiro Yamada 4535ebfa90bSKunihiko Hayashi syscon@5f900000 { 454f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-pxs3-soc-glue-debug", 455f4d624a1SKunihiko Hayashi "simple-mfd", "syscon"; 456f45d6207SKunihiko Hayashi reg = <0x5f900000 0x2000>; 457f05851e1SKeiji Hayashibara #address-cells = <1>; 458f05851e1SKeiji Hayashibara #size-cells = <1>; 459f05851e1SKeiji Hayashibara ranges = <0 0x5f900000 0x2000>; 460f05851e1SKeiji Hayashibara 461f05851e1SKeiji Hayashibara efuse@100 { 462f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 463f05851e1SKeiji Hayashibara reg = <0x100 0x28>; 464f05851e1SKeiji Hayashibara }; 465f05851e1SKeiji Hayashibara 466f05851e1SKeiji Hayashibara efuse@200 { 467f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 468f05851e1SKeiji Hayashibara reg = <0x200 0x68>; 469d7b9beb8SKunihiko Hayashi #address-cells = <1>; 470d7b9beb8SKunihiko Hayashi #size-cells = <1>; 471d7b9beb8SKunihiko Hayashi 472d7b9beb8SKunihiko Hayashi /* USB cells */ 473d7b9beb8SKunihiko Hayashi usb_rterm0: trim@54,4 { 474d7b9beb8SKunihiko Hayashi reg = <0x54 1>; 475d7b9beb8SKunihiko Hayashi bits = <4 2>; 476d7b9beb8SKunihiko Hayashi }; 477d7b9beb8SKunihiko Hayashi usb_rterm1: trim@55,4 { 478d7b9beb8SKunihiko Hayashi reg = <0x55 1>; 479d7b9beb8SKunihiko Hayashi bits = <4 2>; 480d7b9beb8SKunihiko Hayashi }; 481d7b9beb8SKunihiko Hayashi usb_rterm2: trim@58,4 { 482d7b9beb8SKunihiko Hayashi reg = <0x58 1>; 483d7b9beb8SKunihiko Hayashi bits = <4 2>; 484d7b9beb8SKunihiko Hayashi }; 485d7b9beb8SKunihiko Hayashi usb_rterm3: trim@59,4 { 486d7b9beb8SKunihiko Hayashi reg = <0x59 1>; 487d7b9beb8SKunihiko Hayashi bits = <4 2>; 488d7b9beb8SKunihiko Hayashi }; 489d7b9beb8SKunihiko Hayashi usb_sel_t0: trim@54,0 { 490d7b9beb8SKunihiko Hayashi reg = <0x54 1>; 491d7b9beb8SKunihiko Hayashi bits = <0 4>; 492d7b9beb8SKunihiko Hayashi }; 493d7b9beb8SKunihiko Hayashi usb_sel_t1: trim@55,0 { 494d7b9beb8SKunihiko Hayashi reg = <0x55 1>; 495d7b9beb8SKunihiko Hayashi bits = <0 4>; 496d7b9beb8SKunihiko Hayashi }; 497d7b9beb8SKunihiko Hayashi usb_sel_t2: trim@58,0 { 498d7b9beb8SKunihiko Hayashi reg = <0x58 1>; 499d7b9beb8SKunihiko Hayashi bits = <0 4>; 500d7b9beb8SKunihiko Hayashi }; 501d7b9beb8SKunihiko Hayashi usb_sel_t3: trim@59,0 { 502d7b9beb8SKunihiko Hayashi reg = <0x59 1>; 503d7b9beb8SKunihiko Hayashi bits = <0 4>; 504d7b9beb8SKunihiko Hayashi }; 505d7b9beb8SKunihiko Hayashi usb_hs_i0: trim@56,0 { 506d7b9beb8SKunihiko Hayashi reg = <0x56 1>; 507d7b9beb8SKunihiko Hayashi bits = <0 4>; 508d7b9beb8SKunihiko Hayashi }; 509d7b9beb8SKunihiko Hayashi usb_hs_i2: trim@5a,0 { 510d7b9beb8SKunihiko Hayashi reg = <0x5a 1>; 511d7b9beb8SKunihiko Hayashi bits = <0 4>; 512d7b9beb8SKunihiko Hayashi }; 513f05851e1SKeiji Hayashibara }; 514f05851e1SKeiji Hayashibara }; 515f05851e1SKeiji Hayashibara 516f03b998dSKunihiko Hayashi xdmac: dma-controller@5fc10000 { 517f03b998dSKunihiko Hayashi compatible = "socionext,uniphier-xdmac"; 518f03b998dSKunihiko Hayashi reg = <0x5fc10000 0x5300>; 5195ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 520f03b998dSKunihiko Hayashi dma-channels = <16>; 521f03b998dSKunihiko Hayashi #dma-cells = <2>; 522f03b998dSKunihiko Hayashi }; 523f03b998dSKunihiko Hayashi 5249ddc285bSMasahiro Yamada aidet: interrupt-controller@5fc20000 { 525c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-aidet"; 526c28adcb5SMasahiro Yamada reg = <0x5fc20000 0x200>; 527c28adcb5SMasahiro Yamada interrupt-controller; 528c28adcb5SMasahiro Yamada #interrupt-cells = <2>; 529c28adcb5SMasahiro Yamada }; 530c28adcb5SMasahiro Yamada 531c28adcb5SMasahiro Yamada gic: interrupt-controller@5fe00000 { 532c28adcb5SMasahiro Yamada compatible = "arm,gic-v3"; 533c28adcb5SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 534c28adcb5SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 535c28adcb5SMasahiro Yamada interrupt-controller; 536c28adcb5SMasahiro Yamada #interrupt-cells = <3>; 5375ba95e8eSKunihiko Hayashi interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 538c28adcb5SMasahiro Yamada }; 539c28adcb5SMasahiro Yamada 5405ebfa90bSKunihiko Hayashi syscon@61840000 { 541c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-sysctrl", 542c28adcb5SMasahiro Yamada "simple-mfd", "syscon"; 543c28adcb5SMasahiro Yamada reg = <0x61840000 0x10000>; 544c28adcb5SMasahiro Yamada 5455ebfa90bSKunihiko Hayashi sys_clk: clock-controller { 546c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-clock"; 547c28adcb5SMasahiro Yamada #clock-cells = <1>; 548c28adcb5SMasahiro Yamada }; 549c28adcb5SMasahiro Yamada 5505ebfa90bSKunihiko Hayashi sys_rst: reset-controller { 551c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-pxs3-reset"; 552c28adcb5SMasahiro Yamada #reset-cells = <1>; 553c28adcb5SMasahiro Yamada }; 554c28adcb5SMasahiro Yamada 555c28adcb5SMasahiro Yamada watchdog { 556c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-wdt"; 557c28adcb5SMasahiro Yamada }; 5584b7d3743SKunihiko Hayashi 5592dfb62d6SKunihiko Hayashi pvtctl: thermal-sensor { 5604b7d3743SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-thermal"; 5615ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 5624b7d3743SKunihiko Hayashi #thermal-sensor-cells = <0>; 5634b7d3743SKunihiko Hayashi socionext,tmod-calibration = <0x0f22 0x68ee>; 5644b7d3743SKunihiko Hayashi }; 565c28adcb5SMasahiro Yamada }; 566c28adcb5SMasahiro Yamada 567aba054a1SKunihiko Hayashi eth0: ethernet@65000000 { 568aba054a1SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ave4"; 569aba054a1SKunihiko Hayashi status = "disabled"; 570aba054a1SKunihiko Hayashi reg = <0x65000000 0x8500>; 5715ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 572aba054a1SKunihiko Hayashi pinctrl-names = "default"; 573aba054a1SKunihiko Hayashi pinctrl-0 = <&pinctrl_ether_rgmii>; 574a34a464dSKunihiko Hayashi clock-names = "ether"; 575aba054a1SKunihiko Hayashi clocks = <&sys_clk 6>; 576a34a464dSKunihiko Hayashi reset-names = "ether"; 577aba054a1SKunihiko Hayashi resets = <&sys_rst 6>; 578dcabb06bSKunihiko Hayashi phy-mode = "rgmii-id"; 579aba054a1SKunihiko Hayashi local-mac-address = [00 00 00 00 00 00]; 580b076ff8bSKunihiko Hayashi socionext,syscon-phy-mode = <&soc_glue 0>; 581aba054a1SKunihiko Hayashi 582aba054a1SKunihiko Hayashi mdio0: mdio { 583aba054a1SKunihiko Hayashi #address-cells = <1>; 584aba054a1SKunihiko Hayashi #size-cells = <0>; 585aba054a1SKunihiko Hayashi }; 586aba054a1SKunihiko Hayashi }; 587aba054a1SKunihiko Hayashi 588aba054a1SKunihiko Hayashi eth1: ethernet@65200000 { 589aba054a1SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ave4"; 590aba054a1SKunihiko Hayashi status = "disabled"; 591aba054a1SKunihiko Hayashi reg = <0x65200000 0x8500>; 5925ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 593aba054a1SKunihiko Hayashi pinctrl-names = "default"; 594aba054a1SKunihiko Hayashi pinctrl-0 = <&pinctrl_ether1_rgmii>; 595a34a464dSKunihiko Hayashi clock-names = "ether"; 596aba054a1SKunihiko Hayashi clocks = <&sys_clk 7>; 597a34a464dSKunihiko Hayashi reset-names = "ether"; 598aba054a1SKunihiko Hayashi resets = <&sys_rst 7>; 599dcabb06bSKunihiko Hayashi phy-mode = "rgmii-id"; 600aba054a1SKunihiko Hayashi local-mac-address = [00 00 00 00 00 00]; 601b076ff8bSKunihiko Hayashi socionext,syscon-phy-mode = <&soc_glue 1>; 602aba054a1SKunihiko Hayashi 603aba054a1SKunihiko Hayashi mdio1: mdio { 604aba054a1SKunihiko Hayashi #address-cells = <1>; 605aba054a1SKunihiko Hayashi #size-cells = <0>; 606aba054a1SKunihiko Hayashi }; 607aba054a1SKunihiko Hayashi }; 608aba054a1SKunihiko Hayashi 60923e001e7SKunihiko Hayashi ahci0: sata@65600000 { 61023e001e7SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ahci", 61123e001e7SKunihiko Hayashi "generic-ahci"; 61223e001e7SKunihiko Hayashi status = "disabled"; 61323e001e7SKunihiko Hayashi reg = <0x65600000 0x10000>; 61423e001e7SKunihiko Hayashi interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 61523e001e7SKunihiko Hayashi clocks = <&sys_clk 28>; 61623e001e7SKunihiko Hayashi resets = <&sys_rst 28>, <&ahci0_rst 0>; 61723e001e7SKunihiko Hayashi ports-implemented = <1>; 61823e001e7SKunihiko Hayashi phys = <&ahci0_phy>; 61923e001e7SKunihiko Hayashi }; 62023e001e7SKunihiko Hayashi 62123e001e7SKunihiko Hayashi sata-controller@65700000 { 62223e001e7SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ahci-glue", 62323e001e7SKunihiko Hayashi "simple-mfd"; 624f45d6207SKunihiko Hayashi reg = <0x65700000 0x100>; 62523e001e7SKunihiko Hayashi #address-cells = <1>; 62623e001e7SKunihiko Hayashi #size-cells = <1>; 62723e001e7SKunihiko Hayashi ranges = <0 0x65700000 0x100>; 62823e001e7SKunihiko Hayashi 62923e001e7SKunihiko Hayashi ahci0_rst: reset-controller@0 { 63023e001e7SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ahci-reset"; 63123e001e7SKunihiko Hayashi reg = <0x0 0x4>; 63223e001e7SKunihiko Hayashi clock-names = "link"; 63323e001e7SKunihiko Hayashi clocks = <&sys_clk 28>; 63423e001e7SKunihiko Hayashi reset-names = "link"; 63523e001e7SKunihiko Hayashi resets = <&sys_rst 28>; 63623e001e7SKunihiko Hayashi #reset-cells = <1>; 63723e001e7SKunihiko Hayashi }; 63823e001e7SKunihiko Hayashi 63923e001e7SKunihiko Hayashi ahci0_phy: sata-phy@10 { 64023e001e7SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ahci-phy"; 64123e001e7SKunihiko Hayashi reg = <0x10 0x10>; 64223e001e7SKunihiko Hayashi clock-names = "link", "phy"; 64323e001e7SKunihiko Hayashi clocks = <&sys_clk 28>, <&sys_clk 30>; 64423e001e7SKunihiko Hayashi reset-names = "link", "phy"; 64523e001e7SKunihiko Hayashi resets = <&sys_rst 28>, <&sys_rst 30>; 64623e001e7SKunihiko Hayashi #phy-cells = <0>; 64723e001e7SKunihiko Hayashi }; 64823e001e7SKunihiko Hayashi }; 64923e001e7SKunihiko Hayashi 65023e001e7SKunihiko Hayashi ahci1: sata@65800000 { 65123e001e7SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ahci", 65223e001e7SKunihiko Hayashi "generic-ahci"; 65323e001e7SKunihiko Hayashi status = "disabled"; 65423e001e7SKunihiko Hayashi reg = <0x65800000 0x10000>; 65523e001e7SKunihiko Hayashi interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 65623e001e7SKunihiko Hayashi clocks = <&sys_clk 29>; 65723e001e7SKunihiko Hayashi resets = <&sys_rst 29>, <&ahci1_rst 0>; 65823e001e7SKunihiko Hayashi ports-implemented = <1>; 65923e001e7SKunihiko Hayashi phys = <&ahci1_phy>; 66023e001e7SKunihiko Hayashi }; 66123e001e7SKunihiko Hayashi 66223e001e7SKunihiko Hayashi sata-controller@65900000 { 66323e001e7SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ahci-glue", 66423e001e7SKunihiko Hayashi "simple-mfd"; 665f45d6207SKunihiko Hayashi reg = <0x65900000 0x100>; 66623e001e7SKunihiko Hayashi #address-cells = <1>; 66723e001e7SKunihiko Hayashi #size-cells = <1>; 66823e001e7SKunihiko Hayashi ranges = <0 0x65900000 0x100>; 66923e001e7SKunihiko Hayashi 67023e001e7SKunihiko Hayashi ahci1_rst: reset-controller@0 { 67123e001e7SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ahci-reset"; 67223e001e7SKunihiko Hayashi reg = <0x0 0x4>; 67323e001e7SKunihiko Hayashi clock-names = "link"; 67423e001e7SKunihiko Hayashi clocks = <&sys_clk 29>; 67523e001e7SKunihiko Hayashi reset-names = "link"; 67623e001e7SKunihiko Hayashi resets = <&sys_rst 29>; 67723e001e7SKunihiko Hayashi #reset-cells = <1>; 67823e001e7SKunihiko Hayashi }; 67923e001e7SKunihiko Hayashi 68023e001e7SKunihiko Hayashi ahci1_phy: sata-phy@10 { 68123e001e7SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-ahci-phy"; 68223e001e7SKunihiko Hayashi reg = <0x10 0x10>; 68323e001e7SKunihiko Hayashi clock-names = "link", "phy"; 68423e001e7SKunihiko Hayashi clocks = <&sys_clk 29>, <&sys_clk 30>; 68523e001e7SKunihiko Hayashi reset-names = "link", "phy"; 68623e001e7SKunihiko Hayashi resets = <&sys_rst 29>, <&sys_rst 30>; 68723e001e7SKunihiko Hayashi #phy-cells = <0>; 68823e001e7SKunihiko Hayashi }; 68923e001e7SKunihiko Hayashi }; 69023e001e7SKunihiko Hayashi 691d7b9beb8SKunihiko Hayashi usb0: usb@65a00000 { 692d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 693d7b9beb8SKunihiko Hayashi status = "disabled"; 694d7b9beb8SKunihiko Hayashi reg = <0x65a00000 0xcd00>; 695fe17b91aSKunihiko Hayashi interrupt-names = "dwc_usb3"; 6965ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 697d7b9beb8SKunihiko Hayashi pinctrl-names = "default"; 698d7b9beb8SKunihiko Hayashi pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 699d7b9beb8SKunihiko Hayashi clock-names = "ref", "bus_early", "suspend"; 700d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; 701d7b9beb8SKunihiko Hayashi resets = <&usb0_rst 15>; 702d7b9beb8SKunihiko Hayashi phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 703d7b9beb8SKunihiko Hayashi <&usb0_ssphy0>, <&usb0_ssphy1>; 704d7b9beb8SKunihiko Hayashi dr_mode = "host"; 705d7b9beb8SKunihiko Hayashi }; 706d7b9beb8SKunihiko Hayashi 7074cc752a8SKunihiko Hayashi usb-controller@65b00000 { 708d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-dwc3-glue", 709d7b9beb8SKunihiko Hayashi "simple-mfd"; 710f45d6207SKunihiko Hayashi reg = <0x65b00000 0x400>; 711d7b9beb8SKunihiko Hayashi #address-cells = <1>; 712d7b9beb8SKunihiko Hayashi #size-cells = <1>; 713d7b9beb8SKunihiko Hayashi ranges = <0 0x65b00000 0x400>; 714d7b9beb8SKunihiko Hayashi 7155ebfa90bSKunihiko Hayashi usb0_rst: reset-controller@0 { 716d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-reset"; 717d7b9beb8SKunihiko Hayashi reg = <0x0 0x4>; 718d7b9beb8SKunihiko Hayashi #reset-cells = <1>; 719d7b9beb8SKunihiko Hayashi clock-names = "link"; 720d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>; 721d7b9beb8SKunihiko Hayashi reset-names = "link"; 722d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>; 723d7b9beb8SKunihiko Hayashi }; 724d7b9beb8SKunihiko Hayashi 725d7b9beb8SKunihiko Hayashi usb0_vbus0: regulator@100 { 726d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-regulator"; 727d7b9beb8SKunihiko Hayashi reg = <0x100 0x10>; 728d7b9beb8SKunihiko Hayashi clock-names = "link"; 729d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>; 730d7b9beb8SKunihiko Hayashi reset-names = "link"; 731d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>; 732d7b9beb8SKunihiko Hayashi }; 733d7b9beb8SKunihiko Hayashi 734d7b9beb8SKunihiko Hayashi usb0_vbus1: regulator@110 { 735d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-regulator"; 736d7b9beb8SKunihiko Hayashi reg = <0x110 0x10>; 737d7b9beb8SKunihiko Hayashi clock-names = "link"; 738d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>; 739d7b9beb8SKunihiko Hayashi reset-names = "link"; 740d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>; 741d7b9beb8SKunihiko Hayashi }; 742d7b9beb8SKunihiko Hayashi 7435ebfa90bSKunihiko Hayashi usb0_hsphy0: phy@200 { 744d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 745d7b9beb8SKunihiko Hayashi reg = <0x200 0x10>; 746d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 747d7b9beb8SKunihiko Hayashi clock-names = "link", "phy"; 748d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 16>; 749d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 750d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>, <&sys_rst 16>; 751d7b9beb8SKunihiko Hayashi vbus-supply = <&usb0_vbus0>; 752d7b9beb8SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 753d7b9beb8SKunihiko Hayashi nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 754d7b9beb8SKunihiko Hayashi <&usb_hs_i0>; 755d7b9beb8SKunihiko Hayashi }; 756d7b9beb8SKunihiko Hayashi 7575ebfa90bSKunihiko Hayashi usb0_hsphy1: phy@210 { 758d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 759d7b9beb8SKunihiko Hayashi reg = <0x210 0x10>; 760d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 761d7b9beb8SKunihiko Hayashi clock-names = "link", "phy"; 762d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 16>; 763d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 764d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>, <&sys_rst 16>; 765d7b9beb8SKunihiko Hayashi vbus-supply = <&usb0_vbus1>; 766d7b9beb8SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 767d7b9beb8SKunihiko Hayashi nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 768d7b9beb8SKunihiko Hayashi <&usb_hs_i0>; 769d7b9beb8SKunihiko Hayashi }; 770d7b9beb8SKunihiko Hayashi 7715ebfa90bSKunihiko Hayashi usb0_ssphy0: phy@300 { 772d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 773d7b9beb8SKunihiko Hayashi reg = <0x300 0x10>; 774d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 775d7b9beb8SKunihiko Hayashi clock-names = "link", "phy"; 776d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 17>; 777d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 778d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>, <&sys_rst 17>; 779d7b9beb8SKunihiko Hayashi vbus-supply = <&usb0_vbus0>; 780d7b9beb8SKunihiko Hayashi }; 781d7b9beb8SKunihiko Hayashi 7825ebfa90bSKunihiko Hayashi usb0_ssphy1: phy@310 { 783d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 784d7b9beb8SKunihiko Hayashi reg = <0x310 0x10>; 785d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 786d7b9beb8SKunihiko Hayashi clock-names = "link", "phy"; 787d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 12>, <&sys_clk 18>; 788d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 789d7b9beb8SKunihiko Hayashi resets = <&sys_rst 12>, <&sys_rst 18>; 790d7b9beb8SKunihiko Hayashi vbus-supply = <&usb0_vbus1>; 791d7b9beb8SKunihiko Hayashi }; 792d7b9beb8SKunihiko Hayashi }; 793d7b9beb8SKunihiko Hayashi 794d7b9beb8SKunihiko Hayashi usb1: usb@65c00000 { 795d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 796d7b9beb8SKunihiko Hayashi status = "disabled"; 797d7b9beb8SKunihiko Hayashi reg = <0x65c00000 0xcd00>; 798fe17b91aSKunihiko Hayashi interrupt-names = "dwc_usb3"; 7995ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 800d7b9beb8SKunihiko Hayashi pinctrl-names = "default"; 801d7b9beb8SKunihiko Hayashi pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 802d7b9beb8SKunihiko Hayashi clock-names = "ref", "bus_early", "suspend"; 803d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; 804d7b9beb8SKunihiko Hayashi resets = <&usb1_rst 15>; 805d7b9beb8SKunihiko Hayashi phys = <&usb1_hsphy0>, <&usb1_hsphy1>, 806d7b9beb8SKunihiko Hayashi <&usb1_ssphy0>; 807d7b9beb8SKunihiko Hayashi dr_mode = "host"; 808d7b9beb8SKunihiko Hayashi }; 809d7b9beb8SKunihiko Hayashi 8104cc752a8SKunihiko Hayashi usb-controller@65d00000 { 811d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-dwc3-glue", 812d7b9beb8SKunihiko Hayashi "simple-mfd"; 813f45d6207SKunihiko Hayashi reg = <0x65d00000 0x400>; 814d7b9beb8SKunihiko Hayashi #address-cells = <1>; 815d7b9beb8SKunihiko Hayashi #size-cells = <1>; 816d7b9beb8SKunihiko Hayashi ranges = <0 0x65d00000 0x400>; 817d7b9beb8SKunihiko Hayashi 8185ebfa90bSKunihiko Hayashi usb1_rst: reset-controller@0 { 819d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-reset"; 820d7b9beb8SKunihiko Hayashi reg = <0x0 0x4>; 821d7b9beb8SKunihiko Hayashi #reset-cells = <1>; 822d7b9beb8SKunihiko Hayashi clock-names = "link"; 823d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>; 824d7b9beb8SKunihiko Hayashi reset-names = "link"; 825d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>; 826d7b9beb8SKunihiko Hayashi }; 827d7b9beb8SKunihiko Hayashi 828d7b9beb8SKunihiko Hayashi usb1_vbus0: regulator@100 { 829d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-regulator"; 830d7b9beb8SKunihiko Hayashi reg = <0x100 0x10>; 831d7b9beb8SKunihiko Hayashi clock-names = "link"; 832d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>; 833d7b9beb8SKunihiko Hayashi reset-names = "link"; 834d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>; 835d7b9beb8SKunihiko Hayashi }; 836d7b9beb8SKunihiko Hayashi 837d7b9beb8SKunihiko Hayashi usb1_vbus1: regulator@110 { 838d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-regulator"; 839d7b9beb8SKunihiko Hayashi reg = <0x110 0x10>; 840d7b9beb8SKunihiko Hayashi clock-names = "link"; 841d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>; 842d7b9beb8SKunihiko Hayashi reset-names = "link"; 843d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>; 844d7b9beb8SKunihiko Hayashi }; 845d7b9beb8SKunihiko Hayashi 8465ebfa90bSKunihiko Hayashi usb1_hsphy0: phy@200 { 847d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 848d7b9beb8SKunihiko Hayashi reg = <0x200 0x10>; 849d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 850d7b9beb8SKunihiko Hayashi clock-names = "link", "phy", "phy-ext"; 851d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>, <&sys_clk 20>, 852d7b9beb8SKunihiko Hayashi <&sys_clk 14>; 853d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 854d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>, <&sys_rst 20>; 855d7b9beb8SKunihiko Hayashi vbus-supply = <&usb1_vbus0>; 856d7b9beb8SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 857d7b9beb8SKunihiko Hayashi nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 858d7b9beb8SKunihiko Hayashi <&usb_hs_i2>; 859d7b9beb8SKunihiko Hayashi }; 860d7b9beb8SKunihiko Hayashi 8615ebfa90bSKunihiko Hayashi usb1_hsphy1: phy@210 { 862d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 863d7b9beb8SKunihiko Hayashi reg = <0x210 0x10>; 864d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 865d7b9beb8SKunihiko Hayashi clock-names = "link", "phy", "phy-ext"; 866d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>, <&sys_clk 20>, 867d7b9beb8SKunihiko Hayashi <&sys_clk 14>; 868d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 869d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>, <&sys_rst 20>; 870d7b9beb8SKunihiko Hayashi vbus-supply = <&usb1_vbus1>; 871d7b9beb8SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 872d7b9beb8SKunihiko Hayashi nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 873d7b9beb8SKunihiko Hayashi <&usb_hs_i2>; 874d7b9beb8SKunihiko Hayashi }; 875d7b9beb8SKunihiko Hayashi 8765ebfa90bSKunihiko Hayashi usb1_ssphy0: phy@300 { 877d7b9beb8SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 878d7b9beb8SKunihiko Hayashi reg = <0x300 0x10>; 879d7b9beb8SKunihiko Hayashi #phy-cells = <0>; 880d7b9beb8SKunihiko Hayashi clock-names = "link", "phy", "phy-ext"; 881d7b9beb8SKunihiko Hayashi clocks = <&sys_clk 13>, <&sys_clk 21>, 882d7b9beb8SKunihiko Hayashi <&sys_clk 14>; 883d7b9beb8SKunihiko Hayashi reset-names = "link", "phy"; 884d7b9beb8SKunihiko Hayashi resets = <&sys_rst 13>, <&sys_rst 21>; 885d7b9beb8SKunihiko Hayashi vbus-supply = <&usb1_vbus0>; 886d7b9beb8SKunihiko Hayashi }; 887d7b9beb8SKunihiko Hayashi }; 888d7b9beb8SKunihiko Hayashi 88932dfc773SKunihiko Hayashi pcie: pcie@66000000 { 890d93ecbf5SKunihiko Hayashi compatible = "socionext,uniphier-pcie"; 89132dfc773SKunihiko Hayashi status = "disabled"; 89232dfc773SKunihiko Hayashi reg-names = "dbi", "link", "config"; 89332dfc773SKunihiko Hayashi reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 89432dfc773SKunihiko Hayashi <0x2fff0000 0x10000>; 89532dfc773SKunihiko Hayashi #address-cells = <3>; 89632dfc773SKunihiko Hayashi #size-cells = <2>; 89732dfc773SKunihiko Hayashi clocks = <&sys_clk 24>; 89832dfc773SKunihiko Hayashi resets = <&sys_rst 24>; 89932dfc773SKunihiko Hayashi num-lanes = <1>; 90032dfc773SKunihiko Hayashi num-viewport = <1>; 90132dfc773SKunihiko Hayashi bus-range = <0x0 0xff>; 90232dfc773SKunihiko Hayashi device_type = "pci"; 90332dfc773SKunihiko Hayashi ranges = 90432dfc773SKunihiko Hayashi /* downstream I/O */ 90532dfc773SKunihiko Hayashi <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 90632dfc773SKunihiko Hayashi /* non-prefetchable memory */ 90732dfc773SKunihiko Hayashi <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 90832dfc773SKunihiko Hayashi #interrupt-cells = <1>; 90932dfc773SKunihiko Hayashi interrupt-names = "dma", "msi"; 9105ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 9115ba95e8eSKunihiko Hayashi <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 91232dfc773SKunihiko Hayashi interrupt-map-mask = <0 0 0 7>; 91332dfc773SKunihiko Hayashi interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 91432dfc773SKunihiko Hayashi <0 0 0 2 &pcie_intc 1>, /* INTB */ 91532dfc773SKunihiko Hayashi <0 0 0 3 &pcie_intc 2>, /* INTC */ 91632dfc773SKunihiko Hayashi <0 0 0 4 &pcie_intc 3>; /* INTD */ 91732dfc773SKunihiko Hayashi phy-names = "pcie-phy"; 91832dfc773SKunihiko Hayashi phys = <&pcie_phy>; 91932dfc773SKunihiko Hayashi 92032dfc773SKunihiko Hayashi pcie_intc: legacy-interrupt-controller { 92132dfc773SKunihiko Hayashi interrupt-controller; 92232dfc773SKunihiko Hayashi #interrupt-cells = <1>; 92332dfc773SKunihiko Hayashi interrupt-parent = <&gic>; 9245ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 92532dfc773SKunihiko Hayashi }; 92632dfc773SKunihiko Hayashi }; 92732dfc773SKunihiko Hayashi 92832dfc773SKunihiko Hayashi pcie_phy: phy@66038000 { 92932dfc773SKunihiko Hayashi compatible = "socionext,uniphier-pxs3-pcie-phy"; 93032dfc773SKunihiko Hayashi reg = <0x66038000 0x4000>; 93132dfc773SKunihiko Hayashi #phy-cells = <0>; 932e6bd81a2SKunihiko Hayashi clock-names = "link"; 93332dfc773SKunihiko Hayashi clocks = <&sys_clk 24>; 934e6bd81a2SKunihiko Hayashi reset-names = "link"; 93532dfc773SKunihiko Hayashi resets = <&sys_rst 24>; 93632dfc773SKunihiko Hayashi socionext,syscon = <&soc_glue>; 93732dfc773SKunihiko Hayashi }; 93832dfc773SKunihiko Hayashi 939fcb0e53cSMasahiro Yamada nand: nand-controller@68000000 { 940c28adcb5SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 941c28adcb5SMasahiro Yamada status = "disabled"; 942c28adcb5SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 943c28adcb5SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 94453c580c1SMasahiro Yamada #address-cells = <1>; 94553c580c1SMasahiro Yamada #size-cells = <0>; 9465ba95e8eSKunihiko Hayashi interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 947c28adcb5SMasahiro Yamada pinctrl-names = "default"; 948c28adcb5SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 949bae120f8SMasahiro Yamada clock-names = "nand", "nand_x", "ecc"; 950bae120f8SMasahiro Yamada clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 951e98d5023SMasahiro Yamada reset-names = "nand", "reg"; 952e98d5023SMasahiro Yamada resets = <&sys_rst 2>, <&sys_rst 2>; 953c28adcb5SMasahiro Yamada }; 954c28adcb5SMasahiro Yamada }; 955c28adcb5SMasahiro Yamada}; 956c28adcb5SMasahiro Yamada 957c28adcb5SMasahiro Yamada#include "uniphier-pinctrl.dtsi" 958