1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD20 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "socionext,uniphier-ld20"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <2>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 }; 32 33 cluster1 { 34 core0 { 35 cpu = <&cpu2>; 36 }; 37 core1 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 }; 42 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a72"; 46 reg = <0 0x000>; 47 clocks = <&sys_clk 32>; 48 enable-method = "psci"; 49 next-level-cache = <&a72_l2>; 50 operating-points-v2 = <&cluster0_opp>; 51 #cooling-cells = <2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a72"; 57 reg = <0 0x001>; 58 clocks = <&sys_clk 32>; 59 enable-method = "psci"; 60 next-level-cache = <&a72_l2>; 61 operating-points-v2 = <&cluster0_opp>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu2: cpu@100 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0 0x100>; 69 clocks = <&sys_clk 33>; 70 enable-method = "psci"; 71 next-level-cache = <&a53_l2>; 72 operating-points-v2 = <&cluster1_opp>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu3: cpu@101 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0 0x101>; 80 clocks = <&sys_clk 33>; 81 enable-method = "psci"; 82 next-level-cache = <&a53_l2>; 83 operating-points-v2 = <&cluster1_opp>; 84 #cooling-cells = <2>; 85 }; 86 87 a72_l2: l2-cache0 { 88 compatible = "cache"; 89 }; 90 91 a53_l2: l2-cache1 { 92 compatible = "cache"; 93 }; 94 }; 95 96 cluster0_opp: opp-table-0 { 97 compatible = "operating-points-v2"; 98 opp-shared; 99 100 opp-250000000 { 101 opp-hz = /bits/ 64 <250000000>; 102 clock-latency-ns = <300>; 103 }; 104 opp-275000000 { 105 opp-hz = /bits/ 64 <275000000>; 106 clock-latency-ns = <300>; 107 }; 108 opp-500000000 { 109 opp-hz = /bits/ 64 <500000000>; 110 clock-latency-ns = <300>; 111 }; 112 opp-550000000 { 113 opp-hz = /bits/ 64 <550000000>; 114 clock-latency-ns = <300>; 115 }; 116 opp-666667000 { 117 opp-hz = /bits/ 64 <666667000>; 118 clock-latency-ns = <300>; 119 }; 120 opp-733334000 { 121 opp-hz = /bits/ 64 <733334000>; 122 clock-latency-ns = <300>; 123 }; 124 opp-1000000000 { 125 opp-hz = /bits/ 64 <1000000000>; 126 clock-latency-ns = <300>; 127 }; 128 opp-1100000000 { 129 opp-hz = /bits/ 64 <1100000000>; 130 clock-latency-ns = <300>; 131 }; 132 }; 133 134 cluster1_opp: opp-table-1 { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-250000000 { 139 opp-hz = /bits/ 64 <250000000>; 140 clock-latency-ns = <300>; 141 }; 142 opp-275000000 { 143 opp-hz = /bits/ 64 <275000000>; 144 clock-latency-ns = <300>; 145 }; 146 opp-500000000 { 147 opp-hz = /bits/ 64 <500000000>; 148 clock-latency-ns = <300>; 149 }; 150 opp-550000000 { 151 opp-hz = /bits/ 64 <550000000>; 152 clock-latency-ns = <300>; 153 }; 154 opp-666667000 { 155 opp-hz = /bits/ 64 <666667000>; 156 clock-latency-ns = <300>; 157 }; 158 opp-733334000 { 159 opp-hz = /bits/ 64 <733334000>; 160 clock-latency-ns = <300>; 161 }; 162 opp-1000000000 { 163 opp-hz = /bits/ 64 <1000000000>; 164 clock-latency-ns = <300>; 165 }; 166 opp-1100000000 { 167 opp-hz = /bits/ 64 <1100000000>; 168 clock-latency-ns = <300>; 169 }; 170 }; 171 172 psci { 173 compatible = "arm,psci-1.0"; 174 method = "smc"; 175 }; 176 177 clocks { 178 refclk: ref { 179 compatible = "fixed-clock"; 180 #clock-cells = <0>; 181 clock-frequency = <25000000>; 182 }; 183 }; 184 185 emmc_pwrseq: emmc-pwrseq { 186 compatible = "mmc-pwrseq-emmc"; 187 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 188 }; 189 190 timer { 191 compatible = "arm,armv8-timer"; 192 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 196 }; 197 198 thermal-zones { 199 cpu-thermal { 200 polling-delay-passive = <250>; /* 250ms */ 201 polling-delay = <1000>; /* 1000ms */ 202 thermal-sensors = <&pvtctl>; 203 204 trips { 205 cpu_crit: cpu-crit { 206 temperature = <110000>; /* 110C */ 207 hysteresis = <2000>; 208 type = "critical"; 209 }; 210 cpu_alert: cpu-alert { 211 temperature = <100000>; /* 100C */ 212 hysteresis = <2000>; 213 type = "passive"; 214 }; 215 }; 216 217 cooling-maps { 218 map0 { 219 trip = <&cpu_alert>; 220 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 221 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 222 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 223 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 224 }; 225 }; 226 }; 227 }; 228 229 reserved-memory { 230 #address-cells = <2>; 231 #size-cells = <2>; 232 ranges; 233 234 secure-memory@81000000 { 235 reg = <0x0 0x81000000 0x0 0x01000000>; 236 no-map; 237 }; 238 }; 239 240 soc@0 { 241 compatible = "simple-bus"; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 ranges = <0 0 0 0xffffffff>; 245 246 spi0: spi@54006000 { 247 compatible = "socionext,uniphier-scssi"; 248 status = "disabled"; 249 reg = <0x54006000 0x100>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_spi0>; 255 clocks = <&peri_clk 11>; 256 resets = <&peri_rst 11>; 257 }; 258 259 spi1: spi@54006100 { 260 compatible = "socionext,uniphier-scssi"; 261 status = "disabled"; 262 reg = <0x54006100 0x100>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_spi1>; 268 clocks = <&peri_clk 12>; 269 resets = <&peri_rst 12>; 270 }; 271 272 spi2: spi@54006200 { 273 compatible = "socionext,uniphier-scssi"; 274 status = "disabled"; 275 reg = <0x54006200 0x100>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_spi2>; 281 clocks = <&peri_clk 13>; 282 resets = <&peri_rst 13>; 283 }; 284 285 spi3: spi@54006300 { 286 compatible = "socionext,uniphier-scssi"; 287 status = "disabled"; 288 reg = <0x54006300 0x100>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_spi3>; 294 clocks = <&peri_clk 14>; 295 resets = <&peri_rst 14>; 296 }; 297 298 serial0: serial@54006800 { 299 compatible = "socionext,uniphier-uart"; 300 status = "disabled"; 301 reg = <0x54006800 0x40>; 302 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_uart0>; 305 clocks = <&peri_clk 0>; 306 resets = <&peri_rst 0>; 307 }; 308 309 serial1: serial@54006900 { 310 compatible = "socionext,uniphier-uart"; 311 status = "disabled"; 312 reg = <0x54006900 0x40>; 313 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_uart1>; 316 clocks = <&peri_clk 1>; 317 resets = <&peri_rst 1>; 318 }; 319 320 serial2: serial@54006a00 { 321 compatible = "socionext,uniphier-uart"; 322 status = "disabled"; 323 reg = <0x54006a00 0x40>; 324 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_uart2>; 327 clocks = <&peri_clk 2>; 328 resets = <&peri_rst 2>; 329 }; 330 331 serial3: serial@54006b00 { 332 compatible = "socionext,uniphier-uart"; 333 status = "disabled"; 334 reg = <0x54006b00 0x40>; 335 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_uart3>; 338 clocks = <&peri_clk 3>; 339 resets = <&peri_rst 3>; 340 }; 341 342 gpio: gpio@55000000 { 343 compatible = "socionext,uniphier-gpio"; 344 reg = <0x55000000 0x200>; 345 interrupt-parent = <&aidet>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 gpio-controller; 349 #gpio-cells = <2>; 350 gpio-ranges = <&pinctrl 0 0 0>, 351 <&pinctrl 96 0 0>, 352 <&pinctrl 160 0 0>; 353 gpio-ranges-group-names = "gpio_range0", 354 "gpio_range1", 355 "gpio_range2"; 356 ngpios = <205>; 357 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 358 <21 217 3>; 359 }; 360 361 audio@56000000 { 362 compatible = "socionext,uniphier-ld20-aio"; 363 reg = <0x56000000 0x80000>; 364 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pinctrl_aout1>, 367 <&pinctrl_aoutiec1>; 368 clock-names = "aio"; 369 clocks = <&sys_clk 40>; 370 reset-names = "aio"; 371 resets = <&sys_rst 40>; 372 #sound-dai-cells = <1>; 373 socionext,syscon = <&soc_glue>; 374 375 i2s_port0: port@0 { 376 i2s_hdmi: endpoint { 377 }; 378 }; 379 380 i2s_port1: port@1 { 381 i2s_pcmin2: endpoint { 382 }; 383 }; 384 385 i2s_port2: port@2 { 386 i2s_line: endpoint { 387 dai-format = "i2s"; 388 remote-endpoint = <&evea_line>; 389 }; 390 }; 391 392 i2s_port3: port@3 { 393 i2s_hpcmout1: endpoint { 394 }; 395 }; 396 397 i2s_port4: port@4 { 398 i2s_hp: endpoint { 399 dai-format = "i2s"; 400 remote-endpoint = <&evea_hp>; 401 }; 402 }; 403 404 spdif_port0: port@5 { 405 spdif_hiecout1: endpoint { 406 }; 407 }; 408 409 src_port0: port@6 { 410 i2s_epcmout2: endpoint { 411 }; 412 }; 413 414 src_port1: port@7 { 415 i2s_epcmout3: endpoint { 416 }; 417 }; 418 419 comp_spdif_port0: port@8 { 420 comp_spdif_hiecout1: endpoint { 421 }; 422 }; 423 }; 424 425 codec@57900000 { 426 compatible = "socionext,uniphier-evea"; 427 reg = <0x57900000 0x1000>; 428 clock-names = "evea", "exiv"; 429 clocks = <&sys_clk 41>, <&sys_clk 42>; 430 reset-names = "evea", "exiv", "adamv"; 431 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; 432 #sound-dai-cells = <1>; 433 434 port@0 { 435 evea_line: endpoint { 436 remote-endpoint = <&i2s_line>; 437 }; 438 }; 439 440 port@1 { 441 evea_hp: endpoint { 442 remote-endpoint = <&i2s_hp>; 443 }; 444 }; 445 }; 446 447 syscon@57920000 { 448 compatible = "socionext,uniphier-ld20-adamv", 449 "simple-mfd", "syscon"; 450 reg = <0x57920000 0x1000>; 451 452 adamv_rst: reset-controller { 453 compatible = "socionext,uniphier-ld20-adamv-reset"; 454 #reset-cells = <1>; 455 }; 456 }; 457 458 i2c0: i2c@58780000 { 459 compatible = "socionext,uniphier-fi2c"; 460 status = "disabled"; 461 reg = <0x58780000 0x80>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&pinctrl_i2c0>; 467 clocks = <&peri_clk 4>; 468 resets = <&peri_rst 4>; 469 clock-frequency = <100000>; 470 }; 471 472 i2c1: i2c@58781000 { 473 compatible = "socionext,uniphier-fi2c"; 474 status = "disabled"; 475 reg = <0x58781000 0x80>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pinctrl_i2c1>; 481 clocks = <&peri_clk 5>; 482 resets = <&peri_rst 5>; 483 clock-frequency = <100000>; 484 }; 485 486 i2c2: i2c@58782000 { 487 compatible = "socionext,uniphier-fi2c"; 488 reg = <0x58782000 0x80>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&peri_clk 6>; 493 resets = <&peri_rst 6>; 494 clock-frequency = <400000>; 495 }; 496 497 i2c3: i2c@58783000 { 498 compatible = "socionext,uniphier-fi2c"; 499 status = "disabled"; 500 reg = <0x58783000 0x80>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_i2c3>; 506 clocks = <&peri_clk 7>; 507 resets = <&peri_rst 7>; 508 clock-frequency = <100000>; 509 }; 510 511 i2c4: i2c@58784000 { 512 compatible = "socionext,uniphier-fi2c"; 513 status = "disabled"; 514 reg = <0x58784000 0x80>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_i2c4>; 520 clocks = <&peri_clk 8>; 521 resets = <&peri_rst 8>; 522 clock-frequency = <100000>; 523 }; 524 525 i2c5: i2c@58785000 { 526 compatible = "socionext,uniphier-fi2c"; 527 reg = <0x58785000 0x80>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&peri_clk 9>; 532 resets = <&peri_rst 9>; 533 clock-frequency = <400000>; 534 }; 535 536 system_bus: system-bus@58c00000 { 537 compatible = "socionext,uniphier-system-bus"; 538 status = "disabled"; 539 reg = <0x58c00000 0x400>; 540 #address-cells = <2>; 541 #size-cells = <1>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&pinctrl_system_bus>; 544 }; 545 546 smpctrl@59801000 { 547 compatible = "socionext,uniphier-smpctrl"; 548 reg = <0x59801000 0x400>; 549 }; 550 551 syscon@59810000 { 552 compatible = "socionext,uniphier-ld20-sdctrl", 553 "simple-mfd", "syscon"; 554 reg = <0x59810000 0x400>; 555 556 sd_clk: clock-controller { 557 compatible = "socionext,uniphier-ld20-sd-clock"; 558 #clock-cells = <1>; 559 }; 560 561 sd_rst: reset-controller { 562 compatible = "socionext,uniphier-ld20-sd-reset"; 563 #reset-cells = <1>; 564 }; 565 }; 566 567 syscon@59820000 { 568 compatible = "socionext,uniphier-ld20-perictrl", 569 "simple-mfd", "syscon"; 570 reg = <0x59820000 0x200>; 571 572 peri_clk: clock-controller { 573 compatible = "socionext,uniphier-ld20-peri-clock"; 574 #clock-cells = <1>; 575 }; 576 577 peri_rst: reset-controller { 578 compatible = "socionext,uniphier-ld20-peri-reset"; 579 #reset-cells = <1>; 580 }; 581 }; 582 583 emmc: mmc@5a000000 { 584 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 585 reg = <0x5a000000 0x400>; 586 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&pinctrl_emmc>; 589 clocks = <&sys_clk 4>; 590 resets = <&sys_rst 4>; 591 bus-width = <8>; 592 mmc-ddr-1_8v; 593 mmc-hs200-1_8v; 594 mmc-pwrseq = <&emmc_pwrseq>; 595 cdns,phy-input-delay-legacy = <9>; 596 cdns,phy-input-delay-mmc-highspeed = <2>; 597 cdns,phy-input-delay-mmc-ddr = <3>; 598 cdns,phy-dll-delay-sdclk = <21>; 599 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 600 }; 601 602 sd: mmc@5a400000 { 603 compatible = "socionext,uniphier-sd-v3.1.1"; 604 status = "disabled"; 605 reg = <0x5a400000 0x800>; 606 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_sd>; 609 clocks = <&sd_clk 0>; 610 reset-names = "host"; 611 resets = <&sd_rst 0>; 612 bus-width = <4>; 613 cap-sd-highspeed; 614 }; 615 616 soc_glue: syscon@5f800000 { 617 compatible = "socionext,uniphier-ld20-soc-glue", 618 "simple-mfd", "syscon"; 619 reg = <0x5f800000 0x2000>; 620 621 pinctrl: pinctrl { 622 compatible = "socionext,uniphier-ld20-pinctrl"; 623 }; 624 }; 625 626 syscon@5f900000 { 627 compatible = "socionext,uniphier-ld20-soc-glue-debug", 628 "simple-mfd", "syscon"; 629 reg = <0x5f900000 0x2000>; 630 #address-cells = <1>; 631 #size-cells = <1>; 632 ranges = <0 0x5f900000 0x2000>; 633 634 efuse@100 { 635 compatible = "socionext,uniphier-efuse"; 636 reg = <0x100 0x28>; 637 }; 638 639 efuse@200 { 640 compatible = "socionext,uniphier-efuse"; 641 reg = <0x200 0x68>; 642 #address-cells = <1>; 643 #size-cells = <1>; 644 645 /* USB cells */ 646 usb_rterm0: trim@54,4 { 647 reg = <0x54 1>; 648 bits = <4 2>; 649 }; 650 usb_rterm1: trim@55,4 { 651 reg = <0x55 1>; 652 bits = <4 2>; 653 }; 654 usb_rterm2: trim@58,4 { 655 reg = <0x58 1>; 656 bits = <4 2>; 657 }; 658 usb_rterm3: trim@59,4 { 659 reg = <0x59 1>; 660 bits = <4 2>; 661 }; 662 usb_sel_t0: trim@54,0 { 663 reg = <0x54 1>; 664 bits = <0 4>; 665 }; 666 usb_sel_t1: trim@55,0 { 667 reg = <0x55 1>; 668 bits = <0 4>; 669 }; 670 usb_sel_t2: trim@58,0 { 671 reg = <0x58 1>; 672 bits = <0 4>; 673 }; 674 usb_sel_t3: trim@59,0 { 675 reg = <0x59 1>; 676 bits = <0 4>; 677 }; 678 usb_hs_i0: trim@56,0 { 679 reg = <0x56 1>; 680 bits = <0 4>; 681 }; 682 usb_hs_i2: trim@5a,0 { 683 reg = <0x5a 1>; 684 bits = <0 4>; 685 }; 686 }; 687 }; 688 689 xdmac: dma-controller@5fc10000 { 690 compatible = "socionext,uniphier-xdmac"; 691 reg = <0x5fc10000 0x5300>; 692 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 693 dma-channels = <16>; 694 #dma-cells = <2>; 695 }; 696 697 aidet: interrupt-controller@5fc20000 { 698 compatible = "socionext,uniphier-ld20-aidet"; 699 reg = <0x5fc20000 0x200>; 700 interrupt-controller; 701 #interrupt-cells = <2>; 702 }; 703 704 gic: interrupt-controller@5fe00000 { 705 compatible = "arm,gic-v3"; 706 reg = <0x5fe00000 0x10000>, /* GICD */ 707 <0x5fe80000 0x80000>; /* GICR */ 708 interrupt-controller; 709 #interrupt-cells = <3>; 710 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 711 }; 712 713 syscon@61840000 { 714 compatible = "socionext,uniphier-ld20-sysctrl", 715 "simple-mfd", "syscon"; 716 reg = <0x61840000 0x10000>; 717 718 sys_clk: clock-controller { 719 compatible = "socionext,uniphier-ld20-clock"; 720 #clock-cells = <1>; 721 }; 722 723 sys_rst: reset-controller { 724 compatible = "socionext,uniphier-ld20-reset"; 725 #reset-cells = <1>; 726 }; 727 728 watchdog { 729 compatible = "socionext,uniphier-wdt"; 730 }; 731 732 pvtctl: thermal-sensor { 733 compatible = "socionext,uniphier-ld20-thermal"; 734 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 735 #thermal-sensor-cells = <0>; 736 socionext,tmod-calibration = <0x0f22 0x68ee>; 737 }; 738 }; 739 740 eth: ethernet@65000000 { 741 compatible = "socionext,uniphier-ld20-ave4"; 742 status = "disabled"; 743 reg = <0x65000000 0x8500>; 744 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&pinctrl_ether_rgmii>; 747 clock-names = "ether"; 748 clocks = <&sys_clk 6>; 749 reset-names = "ether"; 750 resets = <&sys_rst 6>; 751 phy-mode = "rgmii-id"; 752 local-mac-address = [00 00 00 00 00 00]; 753 socionext,syscon-phy-mode = <&soc_glue 0>; 754 755 mdio: mdio { 756 #address-cells = <1>; 757 #size-cells = <0>; 758 }; 759 }; 760 761 usb: usb@65a00000 { 762 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 763 status = "disabled"; 764 reg = <0x65a00000 0xcd00>; 765 interrupt-names = "host"; 766 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 767 pinctrl-names = "default"; 768 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, 769 <&pinctrl_usb2>, <&pinctrl_usb3>; 770 clock-names = "ref", "bus_early", "suspend"; 771 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; 772 resets = <&usb_rst 15>; 773 phys = <&usb_hsphy0>, <&usb_hsphy1>, 774 <&usb_hsphy2>, <&usb_hsphy3>, 775 <&usb_ssphy0>, <&usb_ssphy1>; 776 dr_mode = "host"; 777 }; 778 779 usb-controller@65b00000 { 780 compatible = "socionext,uniphier-ld20-dwc3-glue", 781 "simple-mfd"; 782 reg = <0x65b00000 0x400>; 783 #address-cells = <1>; 784 #size-cells = <1>; 785 ranges = <0 0x65b00000 0x400>; 786 787 usb_rst: reset-controller@0 { 788 compatible = "socionext,uniphier-ld20-usb3-reset"; 789 reg = <0x0 0x4>; 790 #reset-cells = <1>; 791 clock-names = "link"; 792 clocks = <&sys_clk 14>; 793 reset-names = "link"; 794 resets = <&sys_rst 14>; 795 }; 796 797 usb_vbus0: regulator@100 { 798 compatible = "socionext,uniphier-ld20-usb3-regulator"; 799 reg = <0x100 0x10>; 800 clock-names = "link"; 801 clocks = <&sys_clk 14>; 802 reset-names = "link"; 803 resets = <&sys_rst 14>; 804 }; 805 806 usb_vbus1: regulator@110 { 807 compatible = "socionext,uniphier-ld20-usb3-regulator"; 808 reg = <0x110 0x10>; 809 clock-names = "link"; 810 clocks = <&sys_clk 14>; 811 reset-names = "link"; 812 resets = <&sys_rst 14>; 813 }; 814 815 usb_vbus2: regulator@120 { 816 compatible = "socionext,uniphier-ld20-usb3-regulator"; 817 reg = <0x120 0x10>; 818 clock-names = "link"; 819 clocks = <&sys_clk 14>; 820 reset-names = "link"; 821 resets = <&sys_rst 14>; 822 }; 823 824 usb_vbus3: regulator@130 { 825 compatible = "socionext,uniphier-ld20-usb3-regulator"; 826 reg = <0x130 0x10>; 827 clock-names = "link"; 828 clocks = <&sys_clk 14>; 829 reset-names = "link"; 830 resets = <&sys_rst 14>; 831 }; 832 833 usb_hsphy0: phy@200 { 834 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 835 reg = <0x200 0x10>; 836 #phy-cells = <0>; 837 clock-names = "link", "phy"; 838 clocks = <&sys_clk 14>, <&sys_clk 16>; 839 reset-names = "link", "phy"; 840 resets = <&sys_rst 14>, <&sys_rst 16>; 841 vbus-supply = <&usb_vbus0>; 842 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 843 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 844 <&usb_hs_i0>; 845 }; 846 847 usb_hsphy1: phy@210 { 848 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 849 reg = <0x210 0x10>; 850 #phy-cells = <0>; 851 clock-names = "link", "phy"; 852 clocks = <&sys_clk 14>, <&sys_clk 16>; 853 reset-names = "link", "phy"; 854 resets = <&sys_rst 14>, <&sys_rst 16>; 855 vbus-supply = <&usb_vbus1>; 856 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 857 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 858 <&usb_hs_i0>; 859 }; 860 861 usb_hsphy2: phy@220 { 862 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 863 reg = <0x220 0x10>; 864 #phy-cells = <0>; 865 clock-names = "link", "phy"; 866 clocks = <&sys_clk 14>, <&sys_clk 17>; 867 reset-names = "link", "phy"; 868 resets = <&sys_rst 14>, <&sys_rst 17>; 869 vbus-supply = <&usb_vbus2>; 870 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 871 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 872 <&usb_hs_i2>; 873 }; 874 875 usb_hsphy3: phy@230 { 876 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 877 reg = <0x230 0x10>; 878 #phy-cells = <0>; 879 clock-names = "link", "phy"; 880 clocks = <&sys_clk 14>, <&sys_clk 17>; 881 reset-names = "link", "phy"; 882 resets = <&sys_rst 14>, <&sys_rst 17>; 883 vbus-supply = <&usb_vbus3>; 884 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 885 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 886 <&usb_hs_i2>; 887 }; 888 889 usb_ssphy0: phy@300 { 890 compatible = "socionext,uniphier-ld20-usb3-ssphy"; 891 reg = <0x300 0x10>; 892 #phy-cells = <0>; 893 clock-names = "link", "phy"; 894 clocks = <&sys_clk 14>, <&sys_clk 18>; 895 reset-names = "link", "phy"; 896 resets = <&sys_rst 14>, <&sys_rst 18>; 897 vbus-supply = <&usb_vbus0>; 898 }; 899 900 usb_ssphy1: phy@310 { 901 compatible = "socionext,uniphier-ld20-usb3-ssphy"; 902 reg = <0x310 0x10>; 903 #phy-cells = <0>; 904 clock-names = "link", "phy"; 905 clocks = <&sys_clk 14>, <&sys_clk 19>; 906 reset-names = "link", "phy"; 907 resets = <&sys_rst 14>, <&sys_rst 19>; 908 vbus-supply = <&usb_vbus1>; 909 }; 910 }; 911 912 pcie: pcie@66000000 { 913 compatible = "socionext,uniphier-pcie"; 914 status = "disabled"; 915 reg-names = "dbi", "link", "config"; 916 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 917 <0x2fff0000 0x10000>; 918 #address-cells = <3>; 919 #size-cells = <2>; 920 clocks = <&sys_clk 24>; 921 resets = <&sys_rst 24>; 922 num-lanes = <1>; 923 num-viewport = <1>; 924 bus-range = <0x0 0xff>; 925 device_type = "pci"; 926 ranges = 927 /* downstream I/O */ 928 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 929 /* non-prefetchable memory */ 930 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 931 #interrupt-cells = <1>; 932 interrupt-names = "dma", "msi"; 933 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 935 interrupt-map-mask = <0 0 0 7>; 936 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 937 <0 0 0 2 &pcie_intc 1>, /* INTB */ 938 <0 0 0 3 &pcie_intc 2>, /* INTC */ 939 <0 0 0 4 &pcie_intc 3>; /* INTD */ 940 phy-names = "pcie-phy"; 941 phys = <&pcie_phy>; 942 943 pcie_intc: legacy-interrupt-controller { 944 interrupt-controller; 945 #interrupt-cells = <1>; 946 interrupt-parent = <&gic>; 947 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 948 }; 949 }; 950 951 pcie_phy: phy@66038000 { 952 compatible = "socionext,uniphier-ld20-pcie-phy"; 953 reg = <0x66038000 0x4000>; 954 #phy-cells = <0>; 955 clock-names = "link"; 956 clocks = <&sys_clk 24>; 957 reset-names = "link"; 958 resets = <&sys_rst 24>; 959 socionext,syscon = <&soc_glue>; 960 }; 961 962 nand: nand-controller@68000000 { 963 compatible = "socionext,uniphier-denali-nand-v5b"; 964 status = "disabled"; 965 reg-names = "nand_data", "denali_reg"; 966 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 970 pinctrl-names = "default"; 971 pinctrl-0 = <&pinctrl_nand>; 972 clock-names = "nand", "nand_x", "ecc"; 973 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 974 reset-names = "nand", "reg"; 975 resets = <&sys_rst 2>, <&sys_rst 2>; 976 }; 977 }; 978}; 979 980#include "uniphier-pinctrl.dtsi" 981 982&pinctrl_aout1 { 983 drive-strength = <4>; /* default: 3.5mA */ 984 985 ao1dacck { 986 pins = "AO1DACCK"; 987 drive-strength = <5>; /* 5mA */ 988 }; 989}; 990 991&pinctrl_aoutiec1 { 992 drive-strength = <4>; /* default: 3.5mA */ 993 994 ao1arc { 995 pins = "AO1ARC"; 996 drive-strength = <11>; /* 11mA */ 997 }; 998}; 999