1/*
2 * Device Tree Source for UniPhier LD20 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/gpio/uniphier-gpio.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/memreserve/ 0x80000000 0x02000000;
15
16/ {
17	compatible = "socionext,uniphier-ld20";
18	#address-cells = <2>;
19	#size-cells = <2>;
20	interrupt-parent = <&gic>;
21
22	cpus {
23		#address-cells = <2>;
24		#size-cells = <0>;
25
26		cpu-map {
27			cluster0 {
28				core0 {
29					cpu = <&cpu0>;
30				};
31				core1 {
32					cpu = <&cpu1>;
33				};
34			};
35
36			cluster1 {
37				core0 {
38					cpu = <&cpu2>;
39				};
40				core1 {
41					cpu = <&cpu3>;
42				};
43			};
44		};
45
46		cpu0: cpu@0 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a72", "arm,armv8";
49			reg = <0 0x000>;
50			clocks = <&sys_clk 32>;
51			enable-method = "psci";
52			operating-points-v2 = <&cluster0_opp>;
53			#cooling-cells = <2>;
54		};
55
56		cpu1: cpu@1 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a72", "arm,armv8";
59			reg = <0 0x001>;
60			clocks = <&sys_clk 32>;
61			enable-method = "psci";
62			operating-points-v2 = <&cluster0_opp>;
63		};
64
65		cpu2: cpu@100 {
66			device_type = "cpu";
67			compatible = "arm,cortex-a53", "arm,armv8";
68			reg = <0 0x100>;
69			clocks = <&sys_clk 33>;
70			enable-method = "psci";
71			operating-points-v2 = <&cluster1_opp>;
72			#cooling-cells = <2>;
73		};
74
75		cpu3: cpu@101 {
76			device_type = "cpu";
77			compatible = "arm,cortex-a53", "arm,armv8";
78			reg = <0 0x101>;
79			clocks = <&sys_clk 33>;
80			enable-method = "psci";
81			operating-points-v2 = <&cluster1_opp>;
82		};
83	};
84
85	cluster0_opp: opp-table0 {
86		compatible = "operating-points-v2";
87		opp-shared;
88
89		opp-250000000 {
90			opp-hz = /bits/ 64 <250000000>;
91			clock-latency-ns = <300>;
92		};
93		opp-275000000 {
94			opp-hz = /bits/ 64 <275000000>;
95			clock-latency-ns = <300>;
96		};
97		opp-500000000 {
98			opp-hz = /bits/ 64 <500000000>;
99			clock-latency-ns = <300>;
100		};
101		opp-550000000 {
102			opp-hz = /bits/ 64 <550000000>;
103			clock-latency-ns = <300>;
104		};
105		opp-666667000 {
106			opp-hz = /bits/ 64 <666667000>;
107			clock-latency-ns = <300>;
108		};
109		opp-733334000 {
110			opp-hz = /bits/ 64 <733334000>;
111			clock-latency-ns = <300>;
112		};
113		opp-1000000000 {
114			opp-hz = /bits/ 64 <1000000000>;
115			clock-latency-ns = <300>;
116		};
117		opp-1100000000 {
118			opp-hz = /bits/ 64 <1100000000>;
119			clock-latency-ns = <300>;
120		};
121	};
122
123	cluster1_opp: opp-table1 {
124		compatible = "operating-points-v2";
125		opp-shared;
126
127		opp-250000000 {
128			opp-hz = /bits/ 64 <250000000>;
129			clock-latency-ns = <300>;
130		};
131		opp-275000000 {
132			opp-hz = /bits/ 64 <275000000>;
133			clock-latency-ns = <300>;
134		};
135		opp-500000000 {
136			opp-hz = /bits/ 64 <500000000>;
137			clock-latency-ns = <300>;
138		};
139		opp-550000000 {
140			opp-hz = /bits/ 64 <550000000>;
141			clock-latency-ns = <300>;
142		};
143		opp-666667000 {
144			opp-hz = /bits/ 64 <666667000>;
145			clock-latency-ns = <300>;
146		};
147		opp-733334000 {
148			opp-hz = /bits/ 64 <733334000>;
149			clock-latency-ns = <300>;
150		};
151		opp-1000000000 {
152			opp-hz = /bits/ 64 <1000000000>;
153			clock-latency-ns = <300>;
154		};
155		opp-1100000000 {
156			opp-hz = /bits/ 64 <1100000000>;
157			clock-latency-ns = <300>;
158		};
159	};
160
161	psci {
162		compatible = "arm,psci-1.0";
163		method = "smc";
164	};
165
166	clocks {
167		refclk: ref {
168			compatible = "fixed-clock";
169			#clock-cells = <0>;
170			clock-frequency = <25000000>;
171		};
172	};
173
174	emmc_pwrseq: emmc-pwrseq {
175		compatible = "mmc-pwrseq-emmc";
176		reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
177	};
178
179	timer {
180		compatible = "arm,armv8-timer";
181		interrupts = <1 13 4>,
182			     <1 14 4>,
183			     <1 11 4>,
184			     <1 10 4>;
185	};
186
187	thermal-zones {
188		cpu-thermal {
189			polling-delay-passive = <250>;	/* 250ms */
190			polling-delay = <1000>;		/* 1000ms */
191			thermal-sensors = <&pvtctl>;
192
193			trips {
194				cpu_crit: cpu-crit {
195					temperature = <110000>;	/* 110C */
196					hysteresis = <2000>;
197					type = "critical";
198				};
199				cpu_alert: cpu-alert {
200					temperature = <100000>;	/* 100C */
201					hysteresis = <2000>;
202					type = "passive";
203				};
204			};
205
206			cooling-maps {
207				map0 {
208					trip = <&cpu_alert>;
209					cooling-device = <&cpu0
210					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211				};
212				map1 {
213					trip = <&cpu_alert>;
214					cooling-device = <&cpu2
215					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216				};
217			};
218		};
219	};
220
221	soc@0 {
222		compatible = "simple-bus";
223		#address-cells = <1>;
224		#size-cells = <1>;
225		ranges = <0 0 0 0xffffffff>;
226
227		serial0: serial@54006800 {
228			compatible = "socionext,uniphier-uart";
229			status = "disabled";
230			reg = <0x54006800 0x40>;
231			interrupts = <0 33 4>;
232			pinctrl-names = "default";
233			pinctrl-0 = <&pinctrl_uart0>;
234			clocks = <&peri_clk 0>;
235			resets = <&peri_rst 0>;
236		};
237
238		serial1: serial@54006900 {
239			compatible = "socionext,uniphier-uart";
240			status = "disabled";
241			reg = <0x54006900 0x40>;
242			interrupts = <0 35 4>;
243			pinctrl-names = "default";
244			pinctrl-0 = <&pinctrl_uart1>;
245			clocks = <&peri_clk 1>;
246			resets = <&peri_rst 1>;
247		};
248
249		serial2: serial@54006a00 {
250			compatible = "socionext,uniphier-uart";
251			status = "disabled";
252			reg = <0x54006a00 0x40>;
253			interrupts = <0 37 4>;
254			pinctrl-names = "default";
255			pinctrl-0 = <&pinctrl_uart2>;
256			clocks = <&peri_clk 2>;
257			resets = <&peri_rst 2>;
258		};
259
260		serial3: serial@54006b00 {
261			compatible = "socionext,uniphier-uart";
262			status = "disabled";
263			reg = <0x54006b00 0x40>;
264			interrupts = <0 177 4>;
265			pinctrl-names = "default";
266			pinctrl-0 = <&pinctrl_uart3>;
267			clocks = <&peri_clk 3>;
268			resets = <&peri_rst 3>;
269		};
270
271		gpio: gpio@55000000 {
272			compatible = "socionext,uniphier-gpio";
273			reg = <0x55000000 0x200>;
274			interrupt-parent = <&aidet>;
275			interrupt-controller;
276			#interrupt-cells = <2>;
277			gpio-controller;
278			#gpio-cells = <2>;
279			gpio-ranges = <&pinctrl 0 0 0>,
280				      <&pinctrl 96 0 0>,
281				      <&pinctrl 160 0 0>;
282			gpio-ranges-group-names = "gpio_range0",
283						  "gpio_range1",
284						  "gpio_range2";
285			ngpios = <205>;
286			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
287						     <21 217 3>;
288		};
289
290		audio@56000000 {
291			compatible = "socionext,uniphier-ld20-aio";
292			reg = <0x56000000 0x80000>;
293			interrupts = <0 144 4>;
294			pinctrl-names = "default";
295			pinctrl-0 = <&pinctrl_aout1>,
296				    <&pinctrl_aoutiec1>;
297			clock-names = "aio";
298			clocks = <&sys_clk 40>;
299			reset-names = "aio";
300			resets = <&sys_rst 40>;
301			#sound-dai-cells = <1>;
302
303			i2s_port0: port@0 {
304				i2s_hdmi: endpoint {
305				};
306			};
307
308			i2s_port1: port@1 {
309				i2s_pcmin2: endpoint {
310				};
311			};
312
313			i2s_port2: port@2 {
314				i2s_line: endpoint {
315					dai-format = "i2s";
316					remote-endpoint = <&evea_line>;
317				};
318			};
319
320			i2s_port3: port@3 {
321				i2s_hpcmout1: endpoint {
322				};
323			};
324
325			i2s_port4: port@4 {
326				i2s_hp: endpoint {
327					dai-format = "i2s";
328					remote-endpoint = <&evea_hp>;
329				};
330			};
331
332			spdif_port0: port@5 {
333				spdif_hiecout1: endpoint {
334				};
335			};
336
337			src_port0: port@6 {
338				i2s_epcmout2: endpoint {
339				};
340			};
341
342			src_port1: port@7 {
343				i2s_epcmout3: endpoint {
344				};
345			};
346
347			comp_spdif_port0: port@8 {
348				comp_spdif_hiecout1: endpoint {
349				};
350			};
351		};
352
353		codec@57900000 {
354			compatible = "socionext,uniphier-evea";
355			reg = <0x57900000 0x1000>;
356			clock-names = "evea", "exiv";
357			clocks = <&sys_clk 41>, <&sys_clk 42>;
358			reset-names = "evea", "exiv", "adamv";
359			resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
360			#sound-dai-cells = <1>;
361
362			port@0 {
363				evea_line: endpoint {
364					remote-endpoint = <&i2s_line>;
365				};
366			};
367
368			port@1 {
369				evea_hp: endpoint {
370					remote-endpoint = <&i2s_hp>;
371				};
372			};
373		};
374
375		adamv@57920000 {
376			compatible = "socionext,uniphier-ld20-adamv",
377				     "simple-mfd", "syscon";
378			reg = <0x57920000 0x1000>;
379
380			adamv_rst: reset {
381				compatible = "socionext,uniphier-ld20-adamv-reset";
382				#reset-cells = <1>;
383			};
384		};
385
386		i2c0: i2c@58780000 {
387			compatible = "socionext,uniphier-fi2c";
388			status = "disabled";
389			reg = <0x58780000 0x80>;
390			#address-cells = <1>;
391			#size-cells = <0>;
392			interrupts = <0 41 4>;
393			pinctrl-names = "default";
394			pinctrl-0 = <&pinctrl_i2c0>;
395			clocks = <&peri_clk 4>;
396			resets = <&peri_rst 4>;
397			clock-frequency = <100000>;
398		};
399
400		i2c1: i2c@58781000 {
401			compatible = "socionext,uniphier-fi2c";
402			status = "disabled";
403			reg = <0x58781000 0x80>;
404			#address-cells = <1>;
405			#size-cells = <0>;
406			interrupts = <0 42 4>;
407			pinctrl-names = "default";
408			pinctrl-0 = <&pinctrl_i2c1>;
409			clocks = <&peri_clk 5>;
410			resets = <&peri_rst 5>;
411			clock-frequency = <100000>;
412		};
413
414		i2c2: i2c@58782000 {
415			compatible = "socionext,uniphier-fi2c";
416			reg = <0x58782000 0x80>;
417			#address-cells = <1>;
418			#size-cells = <0>;
419			interrupts = <0 43 4>;
420			clocks = <&peri_clk 6>;
421			resets = <&peri_rst 6>;
422			clock-frequency = <400000>;
423		};
424
425		i2c3: i2c@58783000 {
426			compatible = "socionext,uniphier-fi2c";
427			status = "disabled";
428			reg = <0x58783000 0x80>;
429			#address-cells = <1>;
430			#size-cells = <0>;
431			interrupts = <0 44 4>;
432			pinctrl-names = "default";
433			pinctrl-0 = <&pinctrl_i2c3>;
434			clocks = <&peri_clk 7>;
435			resets = <&peri_rst 7>;
436			clock-frequency = <100000>;
437		};
438
439		i2c4: i2c@58784000 {
440			compatible = "socionext,uniphier-fi2c";
441			status = "disabled";
442			reg = <0x58784000 0x80>;
443			#address-cells = <1>;
444			#size-cells = <0>;
445			interrupts = <0 45 4>;
446			pinctrl-names = "default";
447			pinctrl-0 = <&pinctrl_i2c4>;
448			clocks = <&peri_clk 8>;
449			resets = <&peri_rst 8>;
450			clock-frequency = <100000>;
451		};
452
453		i2c5: i2c@58785000 {
454			compatible = "socionext,uniphier-fi2c";
455			reg = <0x58785000 0x80>;
456			#address-cells = <1>;
457			#size-cells = <0>;
458			interrupts = <0 25 4>;
459			clocks = <&peri_clk 9>;
460			resets = <&peri_rst 9>;
461			clock-frequency = <400000>;
462		};
463
464		system_bus: system-bus@58c00000 {
465			compatible = "socionext,uniphier-system-bus";
466			status = "disabled";
467			reg = <0x58c00000 0x400>;
468			#address-cells = <2>;
469			#size-cells = <1>;
470			pinctrl-names = "default";
471			pinctrl-0 = <&pinctrl_system_bus>;
472		};
473
474		smpctrl@59801000 {
475			compatible = "socionext,uniphier-smpctrl";
476			reg = <0x59801000 0x400>;
477		};
478
479		sdctrl@59810000 {
480			compatible = "socionext,uniphier-ld20-sdctrl",
481				     "simple-mfd", "syscon";
482			reg = <0x59810000 0x400>;
483
484			sd_clk: clock {
485				compatible = "socionext,uniphier-ld20-sd-clock";
486				#clock-cells = <1>;
487			};
488
489			sd_rst: reset {
490				compatible = "socionext,uniphier-ld20-sd-reset";
491				#reset-cells = <1>;
492			};
493		};
494
495		perictrl@59820000 {
496			compatible = "socionext,uniphier-ld20-perictrl",
497				     "simple-mfd", "syscon";
498			reg = <0x59820000 0x200>;
499
500			peri_clk: clock {
501				compatible = "socionext,uniphier-ld20-peri-clock";
502				#clock-cells = <1>;
503			};
504
505			peri_rst: reset {
506				compatible = "socionext,uniphier-ld20-peri-reset";
507				#reset-cells = <1>;
508			};
509		};
510
511		emmc: sdhc@5a000000 {
512			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
513			reg = <0x5a000000 0x400>;
514			interrupts = <0 78 4>;
515			pinctrl-names = "default";
516			pinctrl-0 = <&pinctrl_emmc>;
517			clocks = <&sys_clk 4>;
518			resets = <&sys_rst 4>;
519			bus-width = <8>;
520			mmc-ddr-1_8v;
521			mmc-hs200-1_8v;
522			mmc-pwrseq = <&emmc_pwrseq>;
523			cdns,phy-input-delay-legacy = <4>;
524			cdns,phy-input-delay-mmc-highspeed = <2>;
525			cdns,phy-input-delay-mmc-ddr = <3>;
526			cdns,phy-dll-delay-sdclk = <21>;
527			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
528		};
529
530		soc-glue@5f800000 {
531			compatible = "socionext,uniphier-ld20-soc-glue",
532				     "simple-mfd", "syscon";
533			reg = <0x5f800000 0x2000>;
534
535			pinctrl: pinctrl {
536				compatible = "socionext,uniphier-ld20-pinctrl";
537			};
538		};
539
540		soc-glue@5f900000 {
541			compatible = "socionext,uniphier-ld20-soc-glue-debug",
542				     "simple-mfd";
543			#address-cells = <1>;
544			#size-cells = <1>;
545			ranges = <0 0x5f900000 0x2000>;
546
547			efuse@100 {
548				compatible = "socionext,uniphier-efuse";
549				reg = <0x100 0x28>;
550			};
551
552			efuse@200 {
553				compatible = "socionext,uniphier-efuse";
554				reg = <0x200 0x68>;
555			};
556		};
557
558		aidet: aidet@5fc20000 {
559			compatible = "socionext,uniphier-ld20-aidet";
560			reg = <0x5fc20000 0x200>;
561			interrupt-controller;
562			#interrupt-cells = <2>;
563		};
564
565		gic: interrupt-controller@5fe00000 {
566			compatible = "arm,gic-v3";
567			reg = <0x5fe00000 0x10000>,	/* GICD */
568			      <0x5fe80000 0x80000>;	/* GICR */
569			interrupt-controller;
570			#interrupt-cells = <3>;
571			interrupts = <1 9 4>;
572		};
573
574		sysctrl@61840000 {
575			compatible = "socionext,uniphier-ld20-sysctrl",
576				     "simple-mfd", "syscon";
577			reg = <0x61840000 0x10000>;
578
579			sys_clk: clock {
580				compatible = "socionext,uniphier-ld20-clock";
581				#clock-cells = <1>;
582			};
583
584			sys_rst: reset {
585				compatible = "socionext,uniphier-ld20-reset";
586				#reset-cells = <1>;
587			};
588
589			watchdog {
590				compatible = "socionext,uniphier-wdt";
591			};
592
593			pvtctl: pvtctl {
594				compatible = "socionext,uniphier-ld20-thermal";
595				interrupts = <0 3 4>;
596				#thermal-sensor-cells = <0>;
597				socionext,tmod-calibration = <0x0f22 0x68ee>;
598			};
599		};
600
601		eth: ethernet@65000000 {
602			compatible = "socionext,uniphier-ld20-ave4";
603			status = "disabled";
604			reg = <0x65000000 0x8500>;
605			interrupts = <0 66 4>;
606			pinctrl-names = "default";
607			pinctrl-0 = <&pinctrl_ether_rgmii>;
608			clocks = <&sys_clk 6>;
609			resets = <&sys_rst 6>;
610			phy-mode = "rgmii";
611			local-mac-address = [00 00 00 00 00 00];
612
613			mdio: mdio {
614				#address-cells = <1>;
615				#size-cells = <0>;
616			};
617		};
618
619		nand: nand@68000000 {
620			compatible = "socionext,uniphier-denali-nand-v5b";
621			status = "disabled";
622			reg-names = "nand_data", "denali_reg";
623			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
624			interrupts = <0 65 4>;
625			pinctrl-names = "default";
626			pinctrl-0 = <&pinctrl_nand>;
627			clocks = <&sys_clk 2>;
628			resets = <&sys_rst 2>;
629		};
630	};
631};
632
633#include "uniphier-pinctrl.dtsi"
634
635&pinctrl_aout1 {
636	drive-strength = <4>;	/* default: 3.5mA */
637
638	ao1dacck {
639		pins = "AO1DACCK";
640		drive-strength = <5>;	/* 5mA */
641	};
642};
643
644&pinctrl_aoutiec1 {
645	drive-strength = <4>;	/* default: 3.5mA */
646
647	ao1arc {
648		pins = "AO1ARC";
649		drive-strength = <11>;	/* 11mA */
650	};
651};
652