1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier LD20 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/gpio/uniphier-gpio.h>
10#include <dt-bindings/thermal/thermal.h>
11
12/memreserve/ 0x80000000 0x02000000;
13
14/ {
15	compatible = "socionext,uniphier-ld20";
16	#address-cells = <2>;
17	#size-cells = <2>;
18	interrupt-parent = <&gic>;
19
20	cpus {
21		#address-cells = <2>;
22		#size-cells = <0>;
23
24		cpu-map {
25			cluster0 {
26				core0 {
27					cpu = <&cpu0>;
28				};
29				core1 {
30					cpu = <&cpu1>;
31				};
32			};
33
34			cluster1 {
35				core0 {
36					cpu = <&cpu2>;
37				};
38				core1 {
39					cpu = <&cpu3>;
40				};
41			};
42		};
43
44		cpu0: cpu@0 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a72", "arm,armv8";
47			reg = <0 0x000>;
48			clocks = <&sys_clk 32>;
49			enable-method = "psci";
50			operating-points-v2 = <&cluster0_opp>;
51			#cooling-cells = <2>;
52		};
53
54		cpu1: cpu@1 {
55			device_type = "cpu";
56			compatible = "arm,cortex-a72", "arm,armv8";
57			reg = <0 0x001>;
58			clocks = <&sys_clk 32>;
59			enable-method = "psci";
60			operating-points-v2 = <&cluster0_opp>;
61			#cooling-cells = <2>;
62		};
63
64		cpu2: cpu@100 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53", "arm,armv8";
67			reg = <0 0x100>;
68			clocks = <&sys_clk 33>;
69			enable-method = "psci";
70			operating-points-v2 = <&cluster1_opp>;
71			#cooling-cells = <2>;
72		};
73
74		cpu3: cpu@101 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53", "arm,armv8";
77			reg = <0 0x101>;
78			clocks = <&sys_clk 33>;
79			enable-method = "psci";
80			operating-points-v2 = <&cluster1_opp>;
81			#cooling-cells = <2>;
82		};
83	};
84
85	cluster0_opp: opp-table0 {
86		compatible = "operating-points-v2";
87		opp-shared;
88
89		opp-250000000 {
90			opp-hz = /bits/ 64 <250000000>;
91			clock-latency-ns = <300>;
92		};
93		opp-275000000 {
94			opp-hz = /bits/ 64 <275000000>;
95			clock-latency-ns = <300>;
96		};
97		opp-500000000 {
98			opp-hz = /bits/ 64 <500000000>;
99			clock-latency-ns = <300>;
100		};
101		opp-550000000 {
102			opp-hz = /bits/ 64 <550000000>;
103			clock-latency-ns = <300>;
104		};
105		opp-666667000 {
106			opp-hz = /bits/ 64 <666667000>;
107			clock-latency-ns = <300>;
108		};
109		opp-733334000 {
110			opp-hz = /bits/ 64 <733334000>;
111			clock-latency-ns = <300>;
112		};
113		opp-1000000000 {
114			opp-hz = /bits/ 64 <1000000000>;
115			clock-latency-ns = <300>;
116		};
117		opp-1100000000 {
118			opp-hz = /bits/ 64 <1100000000>;
119			clock-latency-ns = <300>;
120		};
121	};
122
123	cluster1_opp: opp-table1 {
124		compatible = "operating-points-v2";
125		opp-shared;
126
127		opp-250000000 {
128			opp-hz = /bits/ 64 <250000000>;
129			clock-latency-ns = <300>;
130		};
131		opp-275000000 {
132			opp-hz = /bits/ 64 <275000000>;
133			clock-latency-ns = <300>;
134		};
135		opp-500000000 {
136			opp-hz = /bits/ 64 <500000000>;
137			clock-latency-ns = <300>;
138		};
139		opp-550000000 {
140			opp-hz = /bits/ 64 <550000000>;
141			clock-latency-ns = <300>;
142		};
143		opp-666667000 {
144			opp-hz = /bits/ 64 <666667000>;
145			clock-latency-ns = <300>;
146		};
147		opp-733334000 {
148			opp-hz = /bits/ 64 <733334000>;
149			clock-latency-ns = <300>;
150		};
151		opp-1000000000 {
152			opp-hz = /bits/ 64 <1000000000>;
153			clock-latency-ns = <300>;
154		};
155		opp-1100000000 {
156			opp-hz = /bits/ 64 <1100000000>;
157			clock-latency-ns = <300>;
158		};
159	};
160
161	psci {
162		compatible = "arm,psci-1.0";
163		method = "smc";
164	};
165
166	clocks {
167		refclk: ref {
168			compatible = "fixed-clock";
169			#clock-cells = <0>;
170			clock-frequency = <25000000>;
171		};
172	};
173
174	emmc_pwrseq: emmc-pwrseq {
175		compatible = "mmc-pwrseq-emmc";
176		reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
177	};
178
179	timer {
180		compatible = "arm,armv8-timer";
181		interrupts = <1 13 4>,
182			     <1 14 4>,
183			     <1 11 4>,
184			     <1 10 4>;
185	};
186
187	thermal-zones {
188		cpu-thermal {
189			polling-delay-passive = <250>;	/* 250ms */
190			polling-delay = <1000>;		/* 1000ms */
191			thermal-sensors = <&pvtctl>;
192
193			trips {
194				cpu_crit: cpu-crit {
195					temperature = <110000>;	/* 110C */
196					hysteresis = <2000>;
197					type = "critical";
198				};
199				cpu_alert: cpu-alert {
200					temperature = <100000>;	/* 100C */
201					hysteresis = <2000>;
202					type = "passive";
203				};
204			};
205
206			cooling-maps {
207				map0 {
208					trip = <&cpu_alert>;
209					cooling-device = <&cpu0
210					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211				};
212				map1 {
213					trip = <&cpu_alert>;
214					cooling-device = <&cpu2
215					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216				};
217			};
218		};
219	};
220
221	soc@0 {
222		compatible = "simple-bus";
223		#address-cells = <1>;
224		#size-cells = <1>;
225		ranges = <0 0 0 0xffffffff>;
226
227		serial0: serial@54006800 {
228			compatible = "socionext,uniphier-uart";
229			status = "disabled";
230			reg = <0x54006800 0x40>;
231			interrupts = <0 33 4>;
232			pinctrl-names = "default";
233			pinctrl-0 = <&pinctrl_uart0>;
234			clocks = <&peri_clk 0>;
235			resets = <&peri_rst 0>;
236		};
237
238		serial1: serial@54006900 {
239			compatible = "socionext,uniphier-uart";
240			status = "disabled";
241			reg = <0x54006900 0x40>;
242			interrupts = <0 35 4>;
243			pinctrl-names = "default";
244			pinctrl-0 = <&pinctrl_uart1>;
245			clocks = <&peri_clk 1>;
246			resets = <&peri_rst 1>;
247		};
248
249		serial2: serial@54006a00 {
250			compatible = "socionext,uniphier-uart";
251			status = "disabled";
252			reg = <0x54006a00 0x40>;
253			interrupts = <0 37 4>;
254			pinctrl-names = "default";
255			pinctrl-0 = <&pinctrl_uart2>;
256			clocks = <&peri_clk 2>;
257			resets = <&peri_rst 2>;
258		};
259
260		serial3: serial@54006b00 {
261			compatible = "socionext,uniphier-uart";
262			status = "disabled";
263			reg = <0x54006b00 0x40>;
264			interrupts = <0 177 4>;
265			pinctrl-names = "default";
266			pinctrl-0 = <&pinctrl_uart3>;
267			clocks = <&peri_clk 3>;
268			resets = <&peri_rst 3>;
269		};
270
271		gpio: gpio@55000000 {
272			compatible = "socionext,uniphier-gpio";
273			reg = <0x55000000 0x200>;
274			interrupt-parent = <&aidet>;
275			interrupt-controller;
276			#interrupt-cells = <2>;
277			gpio-controller;
278			#gpio-cells = <2>;
279			gpio-ranges = <&pinctrl 0 0 0>,
280				      <&pinctrl 96 0 0>,
281				      <&pinctrl 160 0 0>;
282			gpio-ranges-group-names = "gpio_range0",
283						  "gpio_range1",
284						  "gpio_range2";
285			ngpios = <205>;
286			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
287						     <21 217 3>;
288		};
289
290		audio@56000000 {
291			compatible = "socionext,uniphier-ld20-aio";
292			reg = <0x56000000 0x80000>;
293			interrupts = <0 144 4>;
294			pinctrl-names = "default";
295			pinctrl-0 = <&pinctrl_aout1>,
296				    <&pinctrl_aoutiec1>;
297			clock-names = "aio";
298			clocks = <&sys_clk 40>;
299			reset-names = "aio";
300			resets = <&sys_rst 40>;
301			#sound-dai-cells = <1>;
302			socionext,syscon = <&soc_glue>;
303
304			i2s_port0: port@0 {
305				i2s_hdmi: endpoint {
306				};
307			};
308
309			i2s_port1: port@1 {
310				i2s_pcmin2: endpoint {
311				};
312			};
313
314			i2s_port2: port@2 {
315				i2s_line: endpoint {
316					dai-format = "i2s";
317					remote-endpoint = <&evea_line>;
318				};
319			};
320
321			i2s_port3: port@3 {
322				i2s_hpcmout1: endpoint {
323				};
324			};
325
326			i2s_port4: port@4 {
327				i2s_hp: endpoint {
328					dai-format = "i2s";
329					remote-endpoint = <&evea_hp>;
330				};
331			};
332
333			spdif_port0: port@5 {
334				spdif_hiecout1: endpoint {
335				};
336			};
337
338			src_port0: port@6 {
339				i2s_epcmout2: endpoint {
340				};
341			};
342
343			src_port1: port@7 {
344				i2s_epcmout3: endpoint {
345				};
346			};
347
348			comp_spdif_port0: port@8 {
349				comp_spdif_hiecout1: endpoint {
350				};
351			};
352		};
353
354		codec@57900000 {
355			compatible = "socionext,uniphier-evea";
356			reg = <0x57900000 0x1000>;
357			clock-names = "evea", "exiv";
358			clocks = <&sys_clk 41>, <&sys_clk 42>;
359			reset-names = "evea", "exiv", "adamv";
360			resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
361			#sound-dai-cells = <1>;
362
363			port@0 {
364				evea_line: endpoint {
365					remote-endpoint = <&i2s_line>;
366				};
367			};
368
369			port@1 {
370				evea_hp: endpoint {
371					remote-endpoint = <&i2s_hp>;
372				};
373			};
374		};
375
376		adamv@57920000 {
377			compatible = "socionext,uniphier-ld20-adamv",
378				     "simple-mfd", "syscon";
379			reg = <0x57920000 0x1000>;
380
381			adamv_rst: reset {
382				compatible = "socionext,uniphier-ld20-adamv-reset";
383				#reset-cells = <1>;
384			};
385		};
386
387		i2c0: i2c@58780000 {
388			compatible = "socionext,uniphier-fi2c";
389			status = "disabled";
390			reg = <0x58780000 0x80>;
391			#address-cells = <1>;
392			#size-cells = <0>;
393			interrupts = <0 41 4>;
394			pinctrl-names = "default";
395			pinctrl-0 = <&pinctrl_i2c0>;
396			clocks = <&peri_clk 4>;
397			resets = <&peri_rst 4>;
398			clock-frequency = <100000>;
399		};
400
401		i2c1: i2c@58781000 {
402			compatible = "socionext,uniphier-fi2c";
403			status = "disabled";
404			reg = <0x58781000 0x80>;
405			#address-cells = <1>;
406			#size-cells = <0>;
407			interrupts = <0 42 4>;
408			pinctrl-names = "default";
409			pinctrl-0 = <&pinctrl_i2c1>;
410			clocks = <&peri_clk 5>;
411			resets = <&peri_rst 5>;
412			clock-frequency = <100000>;
413		};
414
415		i2c2: i2c@58782000 {
416			compatible = "socionext,uniphier-fi2c";
417			reg = <0x58782000 0x80>;
418			#address-cells = <1>;
419			#size-cells = <0>;
420			interrupts = <0 43 4>;
421			clocks = <&peri_clk 6>;
422			resets = <&peri_rst 6>;
423			clock-frequency = <400000>;
424		};
425
426		i2c3: i2c@58783000 {
427			compatible = "socionext,uniphier-fi2c";
428			status = "disabled";
429			reg = <0x58783000 0x80>;
430			#address-cells = <1>;
431			#size-cells = <0>;
432			interrupts = <0 44 4>;
433			pinctrl-names = "default";
434			pinctrl-0 = <&pinctrl_i2c3>;
435			clocks = <&peri_clk 7>;
436			resets = <&peri_rst 7>;
437			clock-frequency = <100000>;
438		};
439
440		i2c4: i2c@58784000 {
441			compatible = "socionext,uniphier-fi2c";
442			status = "disabled";
443			reg = <0x58784000 0x80>;
444			#address-cells = <1>;
445			#size-cells = <0>;
446			interrupts = <0 45 4>;
447			pinctrl-names = "default";
448			pinctrl-0 = <&pinctrl_i2c4>;
449			clocks = <&peri_clk 8>;
450			resets = <&peri_rst 8>;
451			clock-frequency = <100000>;
452		};
453
454		i2c5: i2c@58785000 {
455			compatible = "socionext,uniphier-fi2c";
456			reg = <0x58785000 0x80>;
457			#address-cells = <1>;
458			#size-cells = <0>;
459			interrupts = <0 25 4>;
460			clocks = <&peri_clk 9>;
461			resets = <&peri_rst 9>;
462			clock-frequency = <400000>;
463		};
464
465		system_bus: system-bus@58c00000 {
466			compatible = "socionext,uniphier-system-bus";
467			status = "disabled";
468			reg = <0x58c00000 0x400>;
469			#address-cells = <2>;
470			#size-cells = <1>;
471			pinctrl-names = "default";
472			pinctrl-0 = <&pinctrl_system_bus>;
473		};
474
475		smpctrl@59801000 {
476			compatible = "socionext,uniphier-smpctrl";
477			reg = <0x59801000 0x400>;
478		};
479
480		sdctrl@59810000 {
481			compatible = "socionext,uniphier-ld20-sdctrl",
482				     "simple-mfd", "syscon";
483			reg = <0x59810000 0x400>;
484
485			sd_clk: clock {
486				compatible = "socionext,uniphier-ld20-sd-clock";
487				#clock-cells = <1>;
488			};
489
490			sd_rst: reset {
491				compatible = "socionext,uniphier-ld20-sd-reset";
492				#reset-cells = <1>;
493			};
494		};
495
496		perictrl@59820000 {
497			compatible = "socionext,uniphier-ld20-perictrl",
498				     "simple-mfd", "syscon";
499			reg = <0x59820000 0x200>;
500
501			peri_clk: clock {
502				compatible = "socionext,uniphier-ld20-peri-clock";
503				#clock-cells = <1>;
504			};
505
506			peri_rst: reset {
507				compatible = "socionext,uniphier-ld20-peri-reset";
508				#reset-cells = <1>;
509			};
510		};
511
512		emmc: sdhc@5a000000 {
513			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
514			reg = <0x5a000000 0x400>;
515			interrupts = <0 78 4>;
516			pinctrl-names = "default";
517			pinctrl-0 = <&pinctrl_emmc>;
518			clocks = <&sys_clk 4>;
519			resets = <&sys_rst 4>;
520			bus-width = <8>;
521			mmc-ddr-1_8v;
522			mmc-hs200-1_8v;
523			mmc-pwrseq = <&emmc_pwrseq>;
524			cdns,phy-input-delay-legacy = <9>;
525			cdns,phy-input-delay-mmc-highspeed = <2>;
526			cdns,phy-input-delay-mmc-ddr = <3>;
527			cdns,phy-dll-delay-sdclk = <21>;
528			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
529		};
530
531		soc_glue: soc-glue@5f800000 {
532			compatible = "socionext,uniphier-ld20-soc-glue",
533				     "simple-mfd", "syscon";
534			reg = <0x5f800000 0x2000>;
535
536			pinctrl: pinctrl {
537				compatible = "socionext,uniphier-ld20-pinctrl";
538			};
539		};
540
541		soc-glue@5f900000 {
542			compatible = "socionext,uniphier-ld20-soc-glue-debug",
543				     "simple-mfd";
544			#address-cells = <1>;
545			#size-cells = <1>;
546			ranges = <0 0x5f900000 0x2000>;
547
548			efuse@100 {
549				compatible = "socionext,uniphier-efuse";
550				reg = <0x100 0x28>;
551			};
552
553			efuse@200 {
554				compatible = "socionext,uniphier-efuse";
555				reg = <0x200 0x68>;
556			};
557		};
558
559		aidet: aidet@5fc20000 {
560			compatible = "socionext,uniphier-ld20-aidet";
561			reg = <0x5fc20000 0x200>;
562			interrupt-controller;
563			#interrupt-cells = <2>;
564		};
565
566		gic: interrupt-controller@5fe00000 {
567			compatible = "arm,gic-v3";
568			reg = <0x5fe00000 0x10000>,	/* GICD */
569			      <0x5fe80000 0x80000>;	/* GICR */
570			interrupt-controller;
571			#interrupt-cells = <3>;
572			interrupts = <1 9 4>;
573		};
574
575		sysctrl@61840000 {
576			compatible = "socionext,uniphier-ld20-sysctrl",
577				     "simple-mfd", "syscon";
578			reg = <0x61840000 0x10000>;
579
580			sys_clk: clock {
581				compatible = "socionext,uniphier-ld20-clock";
582				#clock-cells = <1>;
583			};
584
585			sys_rst: reset {
586				compatible = "socionext,uniphier-ld20-reset";
587				#reset-cells = <1>;
588			};
589
590			watchdog {
591				compatible = "socionext,uniphier-wdt";
592			};
593
594			pvtctl: pvtctl {
595				compatible = "socionext,uniphier-ld20-thermal";
596				interrupts = <0 3 4>;
597				#thermal-sensor-cells = <0>;
598				socionext,tmod-calibration = <0x0f22 0x68ee>;
599			};
600		};
601
602		eth: ethernet@65000000 {
603			compatible = "socionext,uniphier-ld20-ave4";
604			status = "disabled";
605			reg = <0x65000000 0x8500>;
606			interrupts = <0 66 4>;
607			pinctrl-names = "default";
608			pinctrl-0 = <&pinctrl_ether_rgmii>;
609			clock-names = "ether";
610			clocks = <&sys_clk 6>;
611			reset-names = "ether";
612			resets = <&sys_rst 6>;
613			phy-mode = "rgmii";
614			local-mac-address = [00 00 00 00 00 00];
615			socionext,syscon-phy-mode = <&soc_glue 0>;
616
617			mdio: mdio {
618				#address-cells = <1>;
619				#size-cells = <0>;
620			};
621		};
622
623		nand: nand@68000000 {
624			compatible = "socionext,uniphier-denali-nand-v5b";
625			status = "disabled";
626			reg-names = "nand_data", "denali_reg";
627			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
628			interrupts = <0 65 4>;
629			pinctrl-names = "default";
630			pinctrl-0 = <&pinctrl_nand>;
631			clock-names = "nand", "nand_x", "ecc";
632			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
633			resets = <&sys_rst 2>;
634		};
635	};
636};
637
638#include "uniphier-pinctrl.dtsi"
639
640&pinctrl_aout1 {
641	drive-strength = <4>;	/* default: 3.5mA */
642
643	ao1dacck {
644		pins = "AO1DACCK";
645		drive-strength = <5>;	/* 5mA */
646	};
647};
648
649&pinctrl_aoutiec1 {
650	drive-strength = <4>;	/* default: 3.5mA */
651
652	ao1arc {
653		pins = "AO1ARC";
654		drive-strength = <11>;	/* 11mA */
655	};
656};
657