1/*
2 * Device Tree Source for UniPhier LD20 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/thermal/thermal.h>
12
13/memreserve/ 0x80000000 0x02000000;
14
15/ {
16	compatible = "socionext,uniphier-ld20";
17	#address-cells = <2>;
18	#size-cells = <2>;
19	interrupt-parent = <&gic>;
20
21	cpus {
22		#address-cells = <2>;
23		#size-cells = <0>;
24
25		cpu-map {
26			cluster0 {
27				core0 {
28					cpu = <&cpu0>;
29				};
30				core1 {
31					cpu = <&cpu1>;
32				};
33			};
34
35			cluster1 {
36				core0 {
37					cpu = <&cpu2>;
38				};
39				core1 {
40					cpu = <&cpu3>;
41				};
42			};
43		};
44
45		cpu0: cpu@0 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a72", "arm,armv8";
48			reg = <0 0x000>;
49			clocks = <&sys_clk 32>;
50			enable-method = "psci";
51			operating-points-v2 = <&cluster0_opp>;
52			#cooling-cells = <2>;
53		};
54
55		cpu1: cpu@1 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a72", "arm,armv8";
58			reg = <0 0x001>;
59			clocks = <&sys_clk 32>;
60			enable-method = "psci";
61			operating-points-v2 = <&cluster0_opp>;
62		};
63
64		cpu2: cpu@100 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53", "arm,armv8";
67			reg = <0 0x100>;
68			clocks = <&sys_clk 33>;
69			enable-method = "psci";
70			operating-points-v2 = <&cluster1_opp>;
71			#cooling-cells = <2>;
72		};
73
74		cpu3: cpu@101 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53", "arm,armv8";
77			reg = <0 0x101>;
78			clocks = <&sys_clk 33>;
79			enable-method = "psci";
80			operating-points-v2 = <&cluster1_opp>;
81		};
82	};
83
84	cluster0_opp: opp-table0 {
85		compatible = "operating-points-v2";
86		opp-shared;
87
88		opp-250000000 {
89			opp-hz = /bits/ 64 <250000000>;
90			clock-latency-ns = <300>;
91		};
92		opp-275000000 {
93			opp-hz = /bits/ 64 <275000000>;
94			clock-latency-ns = <300>;
95		};
96		opp-500000000 {
97			opp-hz = /bits/ 64 <500000000>;
98			clock-latency-ns = <300>;
99		};
100		opp-550000000 {
101			opp-hz = /bits/ 64 <550000000>;
102			clock-latency-ns = <300>;
103		};
104		opp-666667000 {
105			opp-hz = /bits/ 64 <666667000>;
106			clock-latency-ns = <300>;
107		};
108		opp-733334000 {
109			opp-hz = /bits/ 64 <733334000>;
110			clock-latency-ns = <300>;
111		};
112		opp-1000000000 {
113			opp-hz = /bits/ 64 <1000000000>;
114			clock-latency-ns = <300>;
115		};
116		opp-1100000000 {
117			opp-hz = /bits/ 64 <1100000000>;
118			clock-latency-ns = <300>;
119		};
120	};
121
122	cluster1_opp: opp-table1 {
123		compatible = "operating-points-v2";
124		opp-shared;
125
126		opp-250000000 {
127			opp-hz = /bits/ 64 <250000000>;
128			clock-latency-ns = <300>;
129		};
130		opp-275000000 {
131			opp-hz = /bits/ 64 <275000000>;
132			clock-latency-ns = <300>;
133		};
134		opp-500000000 {
135			opp-hz = /bits/ 64 <500000000>;
136			clock-latency-ns = <300>;
137		};
138		opp-550000000 {
139			opp-hz = /bits/ 64 <550000000>;
140			clock-latency-ns = <300>;
141		};
142		opp-666667000 {
143			opp-hz = /bits/ 64 <666667000>;
144			clock-latency-ns = <300>;
145		};
146		opp-733334000 {
147			opp-hz = /bits/ 64 <733334000>;
148			clock-latency-ns = <300>;
149		};
150		opp-1000000000 {
151			opp-hz = /bits/ 64 <1000000000>;
152			clock-latency-ns = <300>;
153		};
154		opp-1100000000 {
155			opp-hz = /bits/ 64 <1100000000>;
156			clock-latency-ns = <300>;
157		};
158	};
159
160	psci {
161		compatible = "arm,psci-1.0";
162		method = "smc";
163	};
164
165	clocks {
166		refclk: ref {
167			compatible = "fixed-clock";
168			#clock-cells = <0>;
169			clock-frequency = <25000000>;
170		};
171	};
172
173	emmc_pwrseq: emmc-pwrseq {
174		compatible = "mmc-pwrseq-emmc";
175		reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
176	};
177
178	timer {
179		compatible = "arm,armv8-timer";
180		interrupts = <1 13 4>,
181			     <1 14 4>,
182			     <1 11 4>,
183			     <1 10 4>;
184	};
185
186	thermal-zones {
187		cpu-thermal {
188			polling-delay-passive = <250>;	/* 250ms */
189			polling-delay = <1000>;		/* 1000ms */
190			thermal-sensors = <&pvtctl>;
191
192			trips {
193				cpu_crit: cpu-crit {
194					temperature = <110000>;	/* 110C */
195					hysteresis = <2000>;
196					type = "critical";
197				};
198				cpu_alert: cpu-alert {
199					temperature = <100000>;	/* 100C */
200					hysteresis = <2000>;
201					type = "passive";
202				};
203			};
204
205			cooling-maps {
206				map0 {
207					trip = <&cpu_alert>;
208					cooling-device = <&cpu0
209					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210				};
211				map1 {
212					trip = <&cpu_alert>;
213					cooling-device = <&cpu2
214					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
215				};
216			};
217		};
218	};
219
220	soc@0 {
221		compatible = "simple-bus";
222		#address-cells = <1>;
223		#size-cells = <1>;
224		ranges = <0 0 0 0xffffffff>;
225
226		serial0: serial@54006800 {
227			compatible = "socionext,uniphier-uart";
228			status = "disabled";
229			reg = <0x54006800 0x40>;
230			interrupts = <0 33 4>;
231			pinctrl-names = "default";
232			pinctrl-0 = <&pinctrl_uart0>;
233			clocks = <&peri_clk 0>;
234		};
235
236		serial1: serial@54006900 {
237			compatible = "socionext,uniphier-uart";
238			status = "disabled";
239			reg = <0x54006900 0x40>;
240			interrupts = <0 35 4>;
241			pinctrl-names = "default";
242			pinctrl-0 = <&pinctrl_uart1>;
243			clocks = <&peri_clk 1>;
244		};
245
246		serial2: serial@54006a00 {
247			compatible = "socionext,uniphier-uart";
248			status = "disabled";
249			reg = <0x54006a00 0x40>;
250			interrupts = <0 37 4>;
251			pinctrl-names = "default";
252			pinctrl-0 = <&pinctrl_uart2>;
253			clocks = <&peri_clk 2>;
254		};
255
256		serial3: serial@54006b00 {
257			compatible = "socionext,uniphier-uart";
258			status = "disabled";
259			reg = <0x54006b00 0x40>;
260			interrupts = <0 177 4>;
261			pinctrl-names = "default";
262			pinctrl-0 = <&pinctrl_uart3>;
263			clocks = <&peri_clk 3>;
264		};
265
266		gpio: gpio@55000000 {
267			compatible = "socionext,uniphier-gpio";
268			reg = <0x55000000 0x200>;
269			interrupt-parent = <&aidet>;
270			interrupt-controller;
271			#interrupt-cells = <2>;
272			gpio-controller;
273			#gpio-cells = <2>;
274			gpio-ranges = <&pinctrl 0 0 0>,
275				      <&pinctrl 96 0 0>,
276				      <&pinctrl 160 0 0>;
277			gpio-ranges-group-names = "gpio_range0",
278						  "gpio_range1",
279						  "gpio_range2";
280			ngpios = <205>;
281			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
282						     <21 217 3>;
283		};
284
285		adamv@57920000 {
286			compatible = "socionext,uniphier-ld20-adamv",
287				     "simple-mfd", "syscon";
288			reg = <0x57920000 0x1000>;
289
290			adamv_rst: reset {
291				compatible = "socionext,uniphier-ld20-adamv-reset";
292				#reset-cells = <1>;
293			};
294		};
295
296		i2c0: i2c@58780000 {
297			compatible = "socionext,uniphier-fi2c";
298			status = "disabled";
299			reg = <0x58780000 0x80>;
300			#address-cells = <1>;
301			#size-cells = <0>;
302			interrupts = <0 41 4>;
303			pinctrl-names = "default";
304			pinctrl-0 = <&pinctrl_i2c0>;
305			clocks = <&peri_clk 4>;
306			clock-frequency = <100000>;
307		};
308
309		i2c1: i2c@58781000 {
310			compatible = "socionext,uniphier-fi2c";
311			status = "disabled";
312			reg = <0x58781000 0x80>;
313			#address-cells = <1>;
314			#size-cells = <0>;
315			interrupts = <0 42 4>;
316			pinctrl-names = "default";
317			pinctrl-0 = <&pinctrl_i2c1>;
318			clocks = <&peri_clk 5>;
319			clock-frequency = <100000>;
320		};
321
322		i2c2: i2c@58782000 {
323			compatible = "socionext,uniphier-fi2c";
324			reg = <0x58782000 0x80>;
325			#address-cells = <1>;
326			#size-cells = <0>;
327			interrupts = <0 43 4>;
328			clocks = <&peri_clk 6>;
329			clock-frequency = <400000>;
330		};
331
332		i2c3: i2c@58783000 {
333			compatible = "socionext,uniphier-fi2c";
334			status = "disabled";
335			reg = <0x58783000 0x80>;
336			#address-cells = <1>;
337			#size-cells = <0>;
338			interrupts = <0 44 4>;
339			pinctrl-names = "default";
340			pinctrl-0 = <&pinctrl_i2c3>;
341			clocks = <&peri_clk 7>;
342			clock-frequency = <100000>;
343		};
344
345		i2c4: i2c@58784000 {
346			compatible = "socionext,uniphier-fi2c";
347			status = "disabled";
348			reg = <0x58784000 0x80>;
349			#address-cells = <1>;
350			#size-cells = <0>;
351			interrupts = <0 45 4>;
352			pinctrl-names = "default";
353			pinctrl-0 = <&pinctrl_i2c4>;
354			clocks = <&peri_clk 8>;
355			clock-frequency = <100000>;
356		};
357
358		i2c5: i2c@58785000 {
359			compatible = "socionext,uniphier-fi2c";
360			reg = <0x58785000 0x80>;
361			#address-cells = <1>;
362			#size-cells = <0>;
363			interrupts = <0 25 4>;
364			clocks = <&peri_clk 9>;
365			clock-frequency = <400000>;
366		};
367
368		system_bus: system-bus@58c00000 {
369			compatible = "socionext,uniphier-system-bus";
370			status = "disabled";
371			reg = <0x58c00000 0x400>;
372			#address-cells = <2>;
373			#size-cells = <1>;
374			pinctrl-names = "default";
375			pinctrl-0 = <&pinctrl_system_bus>;
376		};
377
378		smpctrl@59801000 {
379			compatible = "socionext,uniphier-smpctrl";
380			reg = <0x59801000 0x400>;
381		};
382
383		sdctrl@59810000 {
384			compatible = "socionext,uniphier-ld20-sdctrl",
385				     "simple-mfd", "syscon";
386			reg = <0x59810000 0x400>;
387
388			sd_clk: clock {
389				compatible = "socionext,uniphier-ld20-sd-clock";
390				#clock-cells = <1>;
391			};
392
393			sd_rst: reset {
394				compatible = "socionext,uniphier-ld20-sd-reset";
395				#reset-cells = <1>;
396			};
397		};
398
399		perictrl@59820000 {
400			compatible = "socionext,uniphier-ld20-perictrl",
401				     "simple-mfd", "syscon";
402			reg = <0x59820000 0x200>;
403
404			peri_clk: clock {
405				compatible = "socionext,uniphier-ld20-peri-clock";
406				#clock-cells = <1>;
407			};
408
409			peri_rst: reset {
410				compatible = "socionext,uniphier-ld20-peri-reset";
411				#reset-cells = <1>;
412			};
413		};
414
415		emmc: sdhc@5a000000 {
416			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
417			reg = <0x5a000000 0x400>;
418			interrupts = <0 78 4>;
419			pinctrl-names = "default";
420			pinctrl-0 = <&pinctrl_emmc>;
421			clocks = <&sys_clk 4>;
422			bus-width = <8>;
423			mmc-ddr-1_8v;
424			mmc-hs200-1_8v;
425			mmc-pwrseq = <&emmc_pwrseq>;
426			cdns,phy-input-delay-legacy = <4>;
427			cdns,phy-input-delay-mmc-highspeed = <2>;
428			cdns,phy-input-delay-mmc-ddr = <3>;
429			cdns,phy-dll-delay-sdclk = <21>;
430			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
431		};
432
433		soc-glue@5f800000 {
434			compatible = "socionext,uniphier-ld20-soc-glue",
435				     "simple-mfd", "syscon";
436			reg = <0x5f800000 0x2000>;
437
438			pinctrl: pinctrl {
439				compatible = "socionext,uniphier-ld20-pinctrl";
440			};
441		};
442
443		soc-glue@5f900000 {
444			compatible = "socionext,uniphier-ld20-soc-glue-debug",
445				     "simple-mfd";
446			#address-cells = <1>;
447			#size-cells = <1>;
448			ranges = <0 0x5f900000 0x2000>;
449
450			efuse@100 {
451				compatible = "socionext,uniphier-efuse";
452				reg = <0x100 0x28>;
453			};
454
455			efuse@200 {
456				compatible = "socionext,uniphier-efuse";
457				reg = <0x200 0x68>;
458			};
459		};
460
461		aidet: aidet@5fc20000 {
462			compatible = "socionext,uniphier-ld20-aidet";
463			reg = <0x5fc20000 0x200>;
464			interrupt-controller;
465			#interrupt-cells = <2>;
466		};
467
468		gic: interrupt-controller@5fe00000 {
469			compatible = "arm,gic-v3";
470			reg = <0x5fe00000 0x10000>,	/* GICD */
471			      <0x5fe80000 0x80000>;	/* GICR */
472			interrupt-controller;
473			#interrupt-cells = <3>;
474			interrupts = <1 9 4>;
475		};
476
477		sysctrl@61840000 {
478			compatible = "socionext,uniphier-ld20-sysctrl",
479				     "simple-mfd", "syscon";
480			reg = <0x61840000 0x10000>;
481
482			sys_clk: clock {
483				compatible = "socionext,uniphier-ld20-clock";
484				#clock-cells = <1>;
485			};
486
487			sys_rst: reset {
488				compatible = "socionext,uniphier-ld20-reset";
489				#reset-cells = <1>;
490			};
491
492			watchdog {
493				compatible = "socionext,uniphier-wdt";
494			};
495
496			pvtctl: pvtctl {
497				compatible = "socionext,uniphier-ld20-thermal";
498				interrupts = <0 3 4>;
499				#thermal-sensor-cells = <0>;
500				socionext,tmod-calibration = <0x0f22 0x68ee>;
501			};
502		};
503
504		nand: nand@68000000 {
505			compatible = "socionext,uniphier-denali-nand-v5b";
506			status = "disabled";
507			reg-names = "nand_data", "denali_reg";
508			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
509			interrupts = <0 65 4>;
510			pinctrl-names = "default";
511			pinctrl-0 = <&pinctrl_nand>;
512			clocks = <&sys_clk 2>;
513		};
514	};
515};
516
517#include "uniphier-pinctrl.dtsi"
518