1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ 47 48/ { 49 compatible = "socionext,uniphier-ld20"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 68 cluster1 { 69 core0 { 70 cpu = <&cpu2>; 71 }; 72 core1 { 73 cpu = <&cpu3>; 74 }; 75 }; 76 }; 77 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72", "arm,armv8"; 81 reg = <0 0x000>; 82 enable-method = "spin-table"; 83 cpu-release-addr = <0 0x80000000>; 84 }; 85 86 cpu1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a72", "arm,armv8"; 89 reg = <0 0x001>; 90 enable-method = "spin-table"; 91 cpu-release-addr = <0 0x80000000>; 92 }; 93 94 cpu2: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53", "arm,armv8"; 97 reg = <0 0x100>; 98 enable-method = "spin-table"; 99 cpu-release-addr = <0 0x80000000>; 100 }; 101 102 cpu3: cpu@101 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53", "arm,armv8"; 105 reg = <0 0x101>; 106 enable-method = "spin-table"; 107 cpu-release-addr = <0 0x80000000>; 108 }; 109 }; 110 111 clocks { 112 refclk: ref { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <25000000>; 116 }; 117 118 uart_clk: uart_clk { 119 #clock-cells = <0>; 120 compatible = "fixed-clock"; 121 clock-frequency = <58820000>; 122 }; 123 124 i2c_clk: i2c_clk { 125 #clock-cells = <0>; 126 compatible = "fixed-clock"; 127 clock-frequency = <50000000>; 128 }; 129 }; 130 131 timer { 132 compatible = "arm,armv8-timer"; 133 interrupts = <1 13 0xf01>, 134 <1 14 0xf01>, 135 <1 11 0xf01>, 136 <1 10 0xf01>; 137 }; 138 139 soc { 140 compatible = "simple-bus"; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0 0 0 0xffffffff>; 144 145 serial0: serial@54006800 { 146 compatible = "socionext,uniphier-uart"; 147 status = "disabled"; 148 reg = <0x54006800 0x40>; 149 interrupts = <0 33 4>; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_uart0>; 152 clocks = <&uart_clk>; 153 }; 154 155 serial1: serial@54006900 { 156 compatible = "socionext,uniphier-uart"; 157 status = "disabled"; 158 reg = <0x54006900 0x40>; 159 interrupts = <0 35 4>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_uart1>; 162 clocks = <&uart_clk>; 163 }; 164 165 serial2: serial@54006a00 { 166 compatible = "socionext,uniphier-uart"; 167 status = "disabled"; 168 reg = <0x54006a00 0x40>; 169 interrupts = <0 37 4>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_uart2>; 172 clocks = <&uart_clk>; 173 }; 174 175 serial3: serial@54006b00 { 176 compatible = "socionext,uniphier-uart"; 177 status = "disabled"; 178 reg = <0x54006b00 0x40>; 179 interrupts = <0 177 4>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_uart3>; 182 clocks = <&uart_clk>; 183 }; 184 185 i2c0: i2c@58780000 { 186 compatible = "socionext,uniphier-fi2c"; 187 status = "disabled"; 188 reg = <0x58780000 0x80>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 interrupts = <0 41 4>; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_i2c0>; 194 clocks = <&i2c_clk>; 195 clock-frequency = <100000>; 196 }; 197 198 i2c1: i2c@58781000 { 199 compatible = "socionext,uniphier-fi2c"; 200 status = "disabled"; 201 reg = <0x58781000 0x80>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 interrupts = <0 42 4>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_i2c1>; 207 clocks = <&i2c_clk>; 208 clock-frequency = <100000>; 209 }; 210 211 i2c2: i2c@58782000 { 212 compatible = "socionext,uniphier-fi2c"; 213 reg = <0x58782000 0x80>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 interrupts = <0 43 4>; 217 clocks = <&i2c_clk>; 218 clock-frequency = <400000>; 219 }; 220 221 i2c3: i2c@58783000 { 222 compatible = "socionext,uniphier-fi2c"; 223 status = "disabled"; 224 reg = <0x58783000 0x80>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <0 44 4>; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_i2c3>; 230 clocks = <&i2c_clk>; 231 clock-frequency = <100000>; 232 }; 233 234 i2c4: i2c@58784000 { 235 compatible = "socionext,uniphier-fi2c"; 236 status = "disabled"; 237 reg = <0x58784000 0x80>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 interrupts = <0 45 4>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_i2c4>; 243 clocks = <&i2c_clk>; 244 clock-frequency = <100000>; 245 }; 246 247 i2c5: i2c@58785000 { 248 compatible = "socionext,uniphier-fi2c"; 249 reg = <0x58785000 0x80>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 interrupts = <0 25 4>; 253 clocks = <&i2c_clk>; 254 clock-frequency = <400000>; 255 }; 256 257 system_bus: system-bus@58c00000 { 258 compatible = "socionext,uniphier-system-bus"; 259 status = "disabled"; 260 reg = <0x58c00000 0x400>; 261 #address-cells = <2>; 262 #size-cells = <1>; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_system_bus>; 265 }; 266 267 smpctrl@59800000 { 268 compatible = "socionext,uniphier-smpctrl"; 269 reg = <0x59801000 0x400>; 270 }; 271 272 soc-glue@5f800000 { 273 compatible = "simple-mfd", "syscon"; 274 reg = <0x5f800000 0x2000>; 275 276 pinctrl: pinctrl { 277 compatible = "socionext,uniphier-ld20-pinctrl"; 278 }; 279 }; 280 281 gic: interrupt-controller@5fe00000 { 282 compatible = "arm,gic-v3"; 283 reg = <0x5fe00000 0x10000>, /* GICD */ 284 <0x5fe80000 0x80000>; /* GICR */ 285 interrupt-controller; 286 #interrupt-cells = <3>; 287 interrupts = <1 9 4>; 288 }; 289 }; 290}; 291 292/include/ "uniphier-pinctrl.dtsi" 293