1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD20 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "socionext,uniphier-ld20"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <2>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 }; 32 33 cluster1 { 34 core0 { 35 cpu = <&cpu2>; 36 }; 37 core1 { 38 cpu = <&cpu3>; 39 }; 40 }; 41 }; 42 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a72"; 46 reg = <0 0x000>; 47 clocks = <&sys_clk 32>; 48 enable-method = "psci"; 49 operating-points-v2 = <&cluster0_opp>; 50 #cooling-cells = <2>; 51 }; 52 53 cpu1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a72"; 56 reg = <0 0x001>; 57 clocks = <&sys_clk 32>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cluster0_opp>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu2: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0 0x100>; 67 clocks = <&sys_clk 33>; 68 enable-method = "psci"; 69 operating-points-v2 = <&cluster1_opp>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu3: cpu@101 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0 0x101>; 77 clocks = <&sys_clk 33>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cluster1_opp>; 80 #cooling-cells = <2>; 81 }; 82 }; 83 84 cluster0_opp: opp-table-0 { 85 compatible = "operating-points-v2"; 86 opp-shared; 87 88 opp-250000000 { 89 opp-hz = /bits/ 64 <250000000>; 90 clock-latency-ns = <300>; 91 }; 92 opp-275000000 { 93 opp-hz = /bits/ 64 <275000000>; 94 clock-latency-ns = <300>; 95 }; 96 opp-500000000 { 97 opp-hz = /bits/ 64 <500000000>; 98 clock-latency-ns = <300>; 99 }; 100 opp-550000000 { 101 opp-hz = /bits/ 64 <550000000>; 102 clock-latency-ns = <300>; 103 }; 104 opp-666667000 { 105 opp-hz = /bits/ 64 <666667000>; 106 clock-latency-ns = <300>; 107 }; 108 opp-733334000 { 109 opp-hz = /bits/ 64 <733334000>; 110 clock-latency-ns = <300>; 111 }; 112 opp-1000000000 { 113 opp-hz = /bits/ 64 <1000000000>; 114 clock-latency-ns = <300>; 115 }; 116 opp-1100000000 { 117 opp-hz = /bits/ 64 <1100000000>; 118 clock-latency-ns = <300>; 119 }; 120 }; 121 122 cluster1_opp: opp-table-1 { 123 compatible = "operating-points-v2"; 124 opp-shared; 125 126 opp-250000000 { 127 opp-hz = /bits/ 64 <250000000>; 128 clock-latency-ns = <300>; 129 }; 130 opp-275000000 { 131 opp-hz = /bits/ 64 <275000000>; 132 clock-latency-ns = <300>; 133 }; 134 opp-500000000 { 135 opp-hz = /bits/ 64 <500000000>; 136 clock-latency-ns = <300>; 137 }; 138 opp-550000000 { 139 opp-hz = /bits/ 64 <550000000>; 140 clock-latency-ns = <300>; 141 }; 142 opp-666667000 { 143 opp-hz = /bits/ 64 <666667000>; 144 clock-latency-ns = <300>; 145 }; 146 opp-733334000 { 147 opp-hz = /bits/ 64 <733334000>; 148 clock-latency-ns = <300>; 149 }; 150 opp-1000000000 { 151 opp-hz = /bits/ 64 <1000000000>; 152 clock-latency-ns = <300>; 153 }; 154 opp-1100000000 { 155 opp-hz = /bits/ 64 <1100000000>; 156 clock-latency-ns = <300>; 157 }; 158 }; 159 160 psci { 161 compatible = "arm,psci-1.0"; 162 method = "smc"; 163 }; 164 165 clocks { 166 refclk: ref { 167 compatible = "fixed-clock"; 168 #clock-cells = <0>; 169 clock-frequency = <25000000>; 170 }; 171 }; 172 173 emmc_pwrseq: emmc-pwrseq { 174 compatible = "mmc-pwrseq-emmc"; 175 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 176 }; 177 178 timer { 179 compatible = "arm,armv8-timer"; 180 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 184 }; 185 186 thermal-zones { 187 cpu-thermal { 188 polling-delay-passive = <250>; /* 250ms */ 189 polling-delay = <1000>; /* 1000ms */ 190 thermal-sensors = <&pvtctl>; 191 192 trips { 193 cpu_crit: cpu-crit { 194 temperature = <110000>; /* 110C */ 195 hysteresis = <2000>; 196 type = "critical"; 197 }; 198 cpu_alert: cpu-alert { 199 temperature = <100000>; /* 100C */ 200 hysteresis = <2000>; 201 type = "passive"; 202 }; 203 }; 204 205 cooling-maps { 206 map0 { 207 trip = <&cpu_alert>; 208 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 }; 214 }; 215 }; 216 217 reserved-memory { 218 #address-cells = <2>; 219 #size-cells = <2>; 220 ranges; 221 222 secure-memory@81000000 { 223 reg = <0x0 0x81000000 0x0 0x01000000>; 224 no-map; 225 }; 226 }; 227 228 soc@0 { 229 compatible = "simple-bus"; 230 #address-cells = <1>; 231 #size-cells = <1>; 232 ranges = <0 0 0 0xffffffff>; 233 234 spi0: spi@54006000 { 235 compatible = "socionext,uniphier-scssi"; 236 status = "disabled"; 237 reg = <0x54006000 0x100>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_spi0>; 243 clocks = <&peri_clk 11>; 244 resets = <&peri_rst 11>; 245 }; 246 247 spi1: spi@54006100 { 248 compatible = "socionext,uniphier-scssi"; 249 status = "disabled"; 250 reg = <0x54006100 0x100>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_spi1>; 256 clocks = <&peri_clk 12>; 257 resets = <&peri_rst 12>; 258 }; 259 260 spi2: spi@54006200 { 261 compatible = "socionext,uniphier-scssi"; 262 status = "disabled"; 263 reg = <0x54006200 0x100>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_spi2>; 269 clocks = <&peri_clk 13>; 270 resets = <&peri_rst 13>; 271 }; 272 273 spi3: spi@54006300 { 274 compatible = "socionext,uniphier-scssi"; 275 status = "disabled"; 276 reg = <0x54006300 0x100>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_spi3>; 282 clocks = <&peri_clk 14>; 283 resets = <&peri_rst 14>; 284 }; 285 286 serial0: serial@54006800 { 287 compatible = "socionext,uniphier-uart"; 288 status = "disabled"; 289 reg = <0x54006800 0x40>; 290 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_uart0>; 293 clocks = <&peri_clk 0>; 294 resets = <&peri_rst 0>; 295 }; 296 297 serial1: serial@54006900 { 298 compatible = "socionext,uniphier-uart"; 299 status = "disabled"; 300 reg = <0x54006900 0x40>; 301 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_uart1>; 304 clocks = <&peri_clk 1>; 305 resets = <&peri_rst 1>; 306 }; 307 308 serial2: serial@54006a00 { 309 compatible = "socionext,uniphier-uart"; 310 status = "disabled"; 311 reg = <0x54006a00 0x40>; 312 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_uart2>; 315 clocks = <&peri_clk 2>; 316 resets = <&peri_rst 2>; 317 }; 318 319 serial3: serial@54006b00 { 320 compatible = "socionext,uniphier-uart"; 321 status = "disabled"; 322 reg = <0x54006b00 0x40>; 323 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_uart3>; 326 clocks = <&peri_clk 3>; 327 resets = <&peri_rst 3>; 328 }; 329 330 gpio: gpio@55000000 { 331 compatible = "socionext,uniphier-gpio"; 332 reg = <0x55000000 0x200>; 333 interrupt-parent = <&aidet>; 334 interrupt-controller; 335 #interrupt-cells = <2>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 gpio-ranges = <&pinctrl 0 0 0>, 339 <&pinctrl 96 0 0>, 340 <&pinctrl 160 0 0>; 341 gpio-ranges-group-names = "gpio_range0", 342 "gpio_range1", 343 "gpio_range2"; 344 ngpios = <205>; 345 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 346 <21 217 3>; 347 }; 348 349 audio@56000000 { 350 compatible = "socionext,uniphier-ld20-aio"; 351 reg = <0x56000000 0x80000>; 352 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_aout1>, 355 <&pinctrl_aoutiec1>; 356 clock-names = "aio"; 357 clocks = <&sys_clk 40>; 358 reset-names = "aio"; 359 resets = <&sys_rst 40>; 360 #sound-dai-cells = <1>; 361 socionext,syscon = <&soc_glue>; 362 363 i2s_port0: port@0 { 364 i2s_hdmi: endpoint { 365 }; 366 }; 367 368 i2s_port1: port@1 { 369 i2s_pcmin2: endpoint { 370 }; 371 }; 372 373 i2s_port2: port@2 { 374 i2s_line: endpoint { 375 dai-format = "i2s"; 376 remote-endpoint = <&evea_line>; 377 }; 378 }; 379 380 i2s_port3: port@3 { 381 i2s_hpcmout1: endpoint { 382 }; 383 }; 384 385 i2s_port4: port@4 { 386 i2s_hp: endpoint { 387 dai-format = "i2s"; 388 remote-endpoint = <&evea_hp>; 389 }; 390 }; 391 392 spdif_port0: port@5 { 393 spdif_hiecout1: endpoint { 394 }; 395 }; 396 397 src_port0: port@6 { 398 i2s_epcmout2: endpoint { 399 }; 400 }; 401 402 src_port1: port@7 { 403 i2s_epcmout3: endpoint { 404 }; 405 }; 406 407 comp_spdif_port0: port@8 { 408 comp_spdif_hiecout1: endpoint { 409 }; 410 }; 411 }; 412 413 codec@57900000 { 414 compatible = "socionext,uniphier-evea"; 415 reg = <0x57900000 0x1000>; 416 clock-names = "evea", "exiv"; 417 clocks = <&sys_clk 41>, <&sys_clk 42>; 418 reset-names = "evea", "exiv", "adamv"; 419 resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>; 420 #sound-dai-cells = <1>; 421 422 port@0 { 423 evea_line: endpoint { 424 remote-endpoint = <&i2s_line>; 425 }; 426 }; 427 428 port@1 { 429 evea_hp: endpoint { 430 remote-endpoint = <&i2s_hp>; 431 }; 432 }; 433 }; 434 435 adamv@57920000 { 436 compatible = "socionext,uniphier-ld20-adamv", 437 "simple-mfd", "syscon"; 438 reg = <0x57920000 0x1000>; 439 440 adamv_rst: reset { 441 compatible = "socionext,uniphier-ld20-adamv-reset"; 442 #reset-cells = <1>; 443 }; 444 }; 445 446 i2c0: i2c@58780000 { 447 compatible = "socionext,uniphier-fi2c"; 448 status = "disabled"; 449 reg = <0x58780000 0x80>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_i2c0>; 455 clocks = <&peri_clk 4>; 456 resets = <&peri_rst 4>; 457 clock-frequency = <100000>; 458 }; 459 460 i2c1: i2c@58781000 { 461 compatible = "socionext,uniphier-fi2c"; 462 status = "disabled"; 463 reg = <0x58781000 0x80>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_i2c1>; 469 clocks = <&peri_clk 5>; 470 resets = <&peri_rst 5>; 471 clock-frequency = <100000>; 472 }; 473 474 i2c2: i2c@58782000 { 475 compatible = "socionext,uniphier-fi2c"; 476 reg = <0x58782000 0x80>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&peri_clk 6>; 481 resets = <&peri_rst 6>; 482 clock-frequency = <400000>; 483 }; 484 485 i2c3: i2c@58783000 { 486 compatible = "socionext,uniphier-fi2c"; 487 status = "disabled"; 488 reg = <0x58783000 0x80>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pinctrl_i2c3>; 494 clocks = <&peri_clk 7>; 495 resets = <&peri_rst 7>; 496 clock-frequency = <100000>; 497 }; 498 499 i2c4: i2c@58784000 { 500 compatible = "socionext,uniphier-fi2c"; 501 status = "disabled"; 502 reg = <0x58784000 0x80>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&pinctrl_i2c4>; 508 clocks = <&peri_clk 8>; 509 resets = <&peri_rst 8>; 510 clock-frequency = <100000>; 511 }; 512 513 i2c5: i2c@58785000 { 514 compatible = "socionext,uniphier-fi2c"; 515 reg = <0x58785000 0x80>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&peri_clk 9>; 520 resets = <&peri_rst 9>; 521 clock-frequency = <400000>; 522 }; 523 524 system_bus: system-bus@58c00000 { 525 compatible = "socionext,uniphier-system-bus"; 526 status = "disabled"; 527 reg = <0x58c00000 0x400>; 528 #address-cells = <2>; 529 #size-cells = <1>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&pinctrl_system_bus>; 532 }; 533 534 smpctrl@59801000 { 535 compatible = "socionext,uniphier-smpctrl"; 536 reg = <0x59801000 0x400>; 537 }; 538 539 sdctrl@59810000 { 540 compatible = "socionext,uniphier-ld20-sdctrl", 541 "simple-mfd", "syscon"; 542 reg = <0x59810000 0x400>; 543 544 sd_clk: clock { 545 compatible = "socionext,uniphier-ld20-sd-clock"; 546 #clock-cells = <1>; 547 }; 548 549 sd_rst: reset { 550 compatible = "socionext,uniphier-ld20-sd-reset"; 551 #reset-cells = <1>; 552 }; 553 }; 554 555 perictrl@59820000 { 556 compatible = "socionext,uniphier-ld20-perictrl", 557 "simple-mfd", "syscon"; 558 reg = <0x59820000 0x200>; 559 560 peri_clk: clock { 561 compatible = "socionext,uniphier-ld20-peri-clock"; 562 #clock-cells = <1>; 563 }; 564 565 peri_rst: reset { 566 compatible = "socionext,uniphier-ld20-peri-reset"; 567 #reset-cells = <1>; 568 }; 569 }; 570 571 emmc: mmc@5a000000 { 572 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 573 reg = <0x5a000000 0x400>; 574 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&pinctrl_emmc>; 577 clocks = <&sys_clk 4>; 578 resets = <&sys_rst 4>; 579 bus-width = <8>; 580 mmc-ddr-1_8v; 581 mmc-hs200-1_8v; 582 mmc-pwrseq = <&emmc_pwrseq>; 583 cdns,phy-input-delay-legacy = <9>; 584 cdns,phy-input-delay-mmc-highspeed = <2>; 585 cdns,phy-input-delay-mmc-ddr = <3>; 586 cdns,phy-dll-delay-sdclk = <21>; 587 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 588 }; 589 590 sd: mmc@5a400000 { 591 compatible = "socionext,uniphier-sd-v3.1.1"; 592 status = "disabled"; 593 reg = <0x5a400000 0x800>; 594 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&pinctrl_sd>; 597 clocks = <&sd_clk 0>; 598 reset-names = "host"; 599 resets = <&sd_rst 0>; 600 bus-width = <4>; 601 cap-sd-highspeed; 602 }; 603 604 soc_glue: soc-glue@5f800000 { 605 compatible = "socionext,uniphier-ld20-soc-glue", 606 "simple-mfd", "syscon"; 607 reg = <0x5f800000 0x2000>; 608 609 pinctrl: pinctrl { 610 compatible = "socionext,uniphier-ld20-pinctrl"; 611 }; 612 }; 613 614 soc-glue@5f900000 { 615 compatible = "socionext,uniphier-ld20-soc-glue-debug", 616 "simple-mfd"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges = <0 0x5f900000 0x2000>; 620 621 efuse@100 { 622 compatible = "socionext,uniphier-efuse"; 623 reg = <0x100 0x28>; 624 }; 625 626 efuse@200 { 627 compatible = "socionext,uniphier-efuse"; 628 reg = <0x200 0x68>; 629 #address-cells = <1>; 630 #size-cells = <1>; 631 632 /* USB cells */ 633 usb_rterm0: trim@54,4 { 634 reg = <0x54 1>; 635 bits = <4 2>; 636 }; 637 usb_rterm1: trim@55,4 { 638 reg = <0x55 1>; 639 bits = <4 2>; 640 }; 641 usb_rterm2: trim@58,4 { 642 reg = <0x58 1>; 643 bits = <4 2>; 644 }; 645 usb_rterm3: trim@59,4 { 646 reg = <0x59 1>; 647 bits = <4 2>; 648 }; 649 usb_sel_t0: trim@54,0 { 650 reg = <0x54 1>; 651 bits = <0 4>; 652 }; 653 usb_sel_t1: trim@55,0 { 654 reg = <0x55 1>; 655 bits = <0 4>; 656 }; 657 usb_sel_t2: trim@58,0 { 658 reg = <0x58 1>; 659 bits = <0 4>; 660 }; 661 usb_sel_t3: trim@59,0 { 662 reg = <0x59 1>; 663 bits = <0 4>; 664 }; 665 usb_hs_i0: trim@56,0 { 666 reg = <0x56 1>; 667 bits = <0 4>; 668 }; 669 usb_hs_i2: trim@5a,0 { 670 reg = <0x5a 1>; 671 bits = <0 4>; 672 }; 673 }; 674 }; 675 676 xdmac: dma-controller@5fc10000 { 677 compatible = "socionext,uniphier-xdmac"; 678 reg = <0x5fc10000 0x5300>; 679 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 680 dma-channels = <16>; 681 #dma-cells = <2>; 682 }; 683 684 aidet: interrupt-controller@5fc20000 { 685 compatible = "socionext,uniphier-ld20-aidet"; 686 reg = <0x5fc20000 0x200>; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 }; 690 691 gic: interrupt-controller@5fe00000 { 692 compatible = "arm,gic-v3"; 693 reg = <0x5fe00000 0x10000>, /* GICD */ 694 <0x5fe80000 0x80000>; /* GICR */ 695 interrupt-controller; 696 #interrupt-cells = <3>; 697 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 698 }; 699 700 sysctrl@61840000 { 701 compatible = "socionext,uniphier-ld20-sysctrl", 702 "simple-mfd", "syscon"; 703 reg = <0x61840000 0x10000>; 704 705 sys_clk: clock { 706 compatible = "socionext,uniphier-ld20-clock"; 707 #clock-cells = <1>; 708 }; 709 710 sys_rst: reset { 711 compatible = "socionext,uniphier-ld20-reset"; 712 #reset-cells = <1>; 713 }; 714 715 watchdog { 716 compatible = "socionext,uniphier-wdt"; 717 }; 718 719 pvtctl: thermal-sensor { 720 compatible = "socionext,uniphier-ld20-thermal"; 721 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 722 #thermal-sensor-cells = <0>; 723 socionext,tmod-calibration = <0x0f22 0x68ee>; 724 }; 725 }; 726 727 eth: ethernet@65000000 { 728 compatible = "socionext,uniphier-ld20-ave4"; 729 status = "disabled"; 730 reg = <0x65000000 0x8500>; 731 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_ether_rgmii>; 734 clock-names = "ether"; 735 clocks = <&sys_clk 6>; 736 reset-names = "ether"; 737 resets = <&sys_rst 6>; 738 phy-mode = "rgmii-id"; 739 local-mac-address = [00 00 00 00 00 00]; 740 socionext,syscon-phy-mode = <&soc_glue 0>; 741 742 mdio: mdio { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 }; 746 }; 747 748 usb: usb@65a00000 { 749 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 750 status = "disabled"; 751 reg = <0x65a00000 0xcd00>; 752 interrupt-names = "host"; 753 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 754 pinctrl-names = "default"; 755 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, 756 <&pinctrl_usb2>, <&pinctrl_usb3>; 757 clock-names = "ref", "bus_early", "suspend"; 758 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; 759 resets = <&usb_rst 15>; 760 phys = <&usb_hsphy0>, <&usb_hsphy1>, 761 <&usb_hsphy2>, <&usb_hsphy3>, 762 <&usb_ssphy0>, <&usb_ssphy1>; 763 dr_mode = "host"; 764 }; 765 766 usb-controller@65b00000 { 767 compatible = "socionext,uniphier-ld20-dwc3-glue", 768 "simple-mfd"; 769 #address-cells = <1>; 770 #size-cells = <1>; 771 ranges = <0 0x65b00000 0x400>; 772 773 usb_rst: reset@0 { 774 compatible = "socionext,uniphier-ld20-usb3-reset"; 775 reg = <0x0 0x4>; 776 #reset-cells = <1>; 777 clock-names = "link"; 778 clocks = <&sys_clk 14>; 779 reset-names = "link"; 780 resets = <&sys_rst 14>; 781 }; 782 783 usb_vbus0: regulator@100 { 784 compatible = "socionext,uniphier-ld20-usb3-regulator"; 785 reg = <0x100 0x10>; 786 clock-names = "link"; 787 clocks = <&sys_clk 14>; 788 reset-names = "link"; 789 resets = <&sys_rst 14>; 790 }; 791 792 usb_vbus1: regulator@110 { 793 compatible = "socionext,uniphier-ld20-usb3-regulator"; 794 reg = <0x110 0x10>; 795 clock-names = "link"; 796 clocks = <&sys_clk 14>; 797 reset-names = "link"; 798 resets = <&sys_rst 14>; 799 }; 800 801 usb_vbus2: regulator@120 { 802 compatible = "socionext,uniphier-ld20-usb3-regulator"; 803 reg = <0x120 0x10>; 804 clock-names = "link"; 805 clocks = <&sys_clk 14>; 806 reset-names = "link"; 807 resets = <&sys_rst 14>; 808 }; 809 810 usb_vbus3: regulator@130 { 811 compatible = "socionext,uniphier-ld20-usb3-regulator"; 812 reg = <0x130 0x10>; 813 clock-names = "link"; 814 clocks = <&sys_clk 14>; 815 reset-names = "link"; 816 resets = <&sys_rst 14>; 817 }; 818 819 usb_hsphy0: hs-phy@200 { 820 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 821 reg = <0x200 0x10>; 822 #phy-cells = <0>; 823 clock-names = "link", "phy"; 824 clocks = <&sys_clk 14>, <&sys_clk 16>; 825 reset-names = "link", "phy"; 826 resets = <&sys_rst 14>, <&sys_rst 16>; 827 vbus-supply = <&usb_vbus0>; 828 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 829 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 830 <&usb_hs_i0>; 831 }; 832 833 usb_hsphy1: hs-phy@210 { 834 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 835 reg = <0x210 0x10>; 836 #phy-cells = <0>; 837 clock-names = "link", "phy"; 838 clocks = <&sys_clk 14>, <&sys_clk 16>; 839 reset-names = "link", "phy"; 840 resets = <&sys_rst 14>, <&sys_rst 16>; 841 vbus-supply = <&usb_vbus1>; 842 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 843 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 844 <&usb_hs_i0>; 845 }; 846 847 usb_hsphy2: hs-phy@220 { 848 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 849 reg = <0x220 0x10>; 850 #phy-cells = <0>; 851 clock-names = "link", "phy"; 852 clocks = <&sys_clk 14>, <&sys_clk 17>; 853 reset-names = "link", "phy"; 854 resets = <&sys_rst 14>, <&sys_rst 17>; 855 vbus-supply = <&usb_vbus2>; 856 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 857 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 858 <&usb_hs_i2>; 859 }; 860 861 usb_hsphy3: hs-phy@230 { 862 compatible = "socionext,uniphier-ld20-usb3-hsphy"; 863 reg = <0x230 0x10>; 864 #phy-cells = <0>; 865 clock-names = "link", "phy"; 866 clocks = <&sys_clk 14>, <&sys_clk 17>; 867 reset-names = "link", "phy"; 868 resets = <&sys_rst 14>, <&sys_rst 17>; 869 vbus-supply = <&usb_vbus3>; 870 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 871 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 872 <&usb_hs_i2>; 873 }; 874 875 usb_ssphy0: ss-phy@300 { 876 compatible = "socionext,uniphier-ld20-usb3-ssphy"; 877 reg = <0x300 0x10>; 878 #phy-cells = <0>; 879 clock-names = "link", "phy"; 880 clocks = <&sys_clk 14>, <&sys_clk 18>; 881 reset-names = "link", "phy"; 882 resets = <&sys_rst 14>, <&sys_rst 18>; 883 vbus-supply = <&usb_vbus0>; 884 }; 885 886 usb_ssphy1: ss-phy@310 { 887 compatible = "socionext,uniphier-ld20-usb3-ssphy"; 888 reg = <0x310 0x10>; 889 #phy-cells = <0>; 890 clock-names = "link", "phy"; 891 clocks = <&sys_clk 14>, <&sys_clk 19>; 892 reset-names = "link", "phy"; 893 resets = <&sys_rst 14>, <&sys_rst 19>; 894 vbus-supply = <&usb_vbus1>; 895 }; 896 }; 897 898 pcie: pcie@66000000 { 899 compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; 900 status = "disabled"; 901 reg-names = "dbi", "link", "config"; 902 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 903 <0x2fff0000 0x10000>; 904 #address-cells = <3>; 905 #size-cells = <2>; 906 clocks = <&sys_clk 24>; 907 resets = <&sys_rst 24>; 908 num-lanes = <1>; 909 num-viewport = <1>; 910 bus-range = <0x0 0xff>; 911 device_type = "pci"; 912 ranges = 913 /* downstream I/O */ 914 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 915 /* non-prefetchable memory */ 916 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 917 #interrupt-cells = <1>; 918 interrupt-names = "dma", "msi"; 919 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 921 interrupt-map-mask = <0 0 0 7>; 922 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 923 <0 0 0 2 &pcie_intc 1>, /* INTB */ 924 <0 0 0 3 &pcie_intc 2>, /* INTC */ 925 <0 0 0 4 &pcie_intc 3>; /* INTD */ 926 phy-names = "pcie-phy"; 927 phys = <&pcie_phy>; 928 929 pcie_intc: legacy-interrupt-controller { 930 interrupt-controller; 931 #interrupt-cells = <1>; 932 interrupt-parent = <&gic>; 933 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 934 }; 935 }; 936 937 pcie_phy: phy@66038000 { 938 compatible = "socionext,uniphier-ld20-pcie-phy"; 939 reg = <0x66038000 0x4000>; 940 #phy-cells = <0>; 941 clock-names = "link"; 942 clocks = <&sys_clk 24>; 943 reset-names = "link"; 944 resets = <&sys_rst 24>; 945 socionext,syscon = <&soc_glue>; 946 }; 947 948 nand: nand-controller@68000000 { 949 compatible = "socionext,uniphier-denali-nand-v5b"; 950 status = "disabled"; 951 reg-names = "nand_data", "denali_reg"; 952 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&pinctrl_nand>; 958 clock-names = "nand", "nand_x", "ecc"; 959 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 960 reset-names = "nand", "reg"; 961 resets = <&sys_rst 2>, <&sys_rst 2>; 962 }; 963 }; 964}; 965 966#include "uniphier-pinctrl.dtsi" 967 968&pinctrl_aout1 { 969 drive-strength = <4>; /* default: 3.5mA */ 970 971 ao1dacck { 972 pins = "AO1DACCK"; 973 drive-strength = <5>; /* 5mA */ 974 }; 975}; 976 977&pinctrl_aoutiec1 { 978 drive-strength = <4>; /* default: 3.5mA */ 979 980 ao1arc { 981 pins = "AO1ARC"; 982 drive-strength = <11>; /* 11mA */ 983 }; 984}; 985