1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10#include <dt-bindings/thermal/thermal.h> 11 12/memreserve/ 0x80000000 0x02000000; 13 14/ { 15 compatible = "socionext,uniphier-ld20"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 }; 33 34 cluster1 { 35 core0 { 36 cpu = <&cpu2>; 37 }; 38 core1 { 39 cpu = <&cpu3>; 40 }; 41 }; 42 }; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a72", "arm,armv8"; 47 reg = <0 0x000>; 48 clocks = <&sys_clk 32>; 49 enable-method = "psci"; 50 operating-points-v2 = <&cluster0_opp>; 51 #cooling-cells = <2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a72", "arm,armv8"; 57 reg = <0 0x001>; 58 clocks = <&sys_clk 32>; 59 enable-method = "psci"; 60 operating-points-v2 = <&cluster0_opp>; 61 }; 62 63 cpu2: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53", "arm,armv8"; 66 reg = <0 0x100>; 67 clocks = <&sys_clk 33>; 68 enable-method = "psci"; 69 operating-points-v2 = <&cluster1_opp>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu3: cpu@101 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53", "arm,armv8"; 76 reg = <0 0x101>; 77 clocks = <&sys_clk 33>; 78 enable-method = "psci"; 79 operating-points-v2 = <&cluster1_opp>; 80 }; 81 }; 82 83 cluster0_opp: opp-table0 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-250000000 { 88 opp-hz = /bits/ 64 <250000000>; 89 clock-latency-ns = <300>; 90 }; 91 opp-275000000 { 92 opp-hz = /bits/ 64 <275000000>; 93 clock-latency-ns = <300>; 94 }; 95 opp-500000000 { 96 opp-hz = /bits/ 64 <500000000>; 97 clock-latency-ns = <300>; 98 }; 99 opp-550000000 { 100 opp-hz = /bits/ 64 <550000000>; 101 clock-latency-ns = <300>; 102 }; 103 opp-666667000 { 104 opp-hz = /bits/ 64 <666667000>; 105 clock-latency-ns = <300>; 106 }; 107 opp-733334000 { 108 opp-hz = /bits/ 64 <733334000>; 109 clock-latency-ns = <300>; 110 }; 111 opp-1000000000 { 112 opp-hz = /bits/ 64 <1000000000>; 113 clock-latency-ns = <300>; 114 }; 115 opp-1100000000 { 116 opp-hz = /bits/ 64 <1100000000>; 117 clock-latency-ns = <300>; 118 }; 119 }; 120 121 cluster1_opp: opp-table1 { 122 compatible = "operating-points-v2"; 123 opp-shared; 124 125 opp-250000000 { 126 opp-hz = /bits/ 64 <250000000>; 127 clock-latency-ns = <300>; 128 }; 129 opp-275000000 { 130 opp-hz = /bits/ 64 <275000000>; 131 clock-latency-ns = <300>; 132 }; 133 opp-500000000 { 134 opp-hz = /bits/ 64 <500000000>; 135 clock-latency-ns = <300>; 136 }; 137 opp-550000000 { 138 opp-hz = /bits/ 64 <550000000>; 139 clock-latency-ns = <300>; 140 }; 141 opp-666667000 { 142 opp-hz = /bits/ 64 <666667000>; 143 clock-latency-ns = <300>; 144 }; 145 opp-733334000 { 146 opp-hz = /bits/ 64 <733334000>; 147 clock-latency-ns = <300>; 148 }; 149 opp-1000000000 { 150 opp-hz = /bits/ 64 <1000000000>; 151 clock-latency-ns = <300>; 152 }; 153 opp-1100000000 { 154 opp-hz = /bits/ 64 <1100000000>; 155 clock-latency-ns = <300>; 156 }; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0"; 161 method = "smc"; 162 }; 163 164 clocks { 165 refclk: ref { 166 compatible = "fixed-clock"; 167 #clock-cells = <0>; 168 clock-frequency = <25000000>; 169 }; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <1 13 4>, 175 <1 14 4>, 176 <1 11 4>, 177 <1 10 4>; 178 }; 179 180 thermal-zones { 181 cpu-thermal { 182 polling-delay-passive = <250>; /* 250ms */ 183 polling-delay = <1000>; /* 1000ms */ 184 thermal-sensors = <&pvtctl>; 185 186 trips { 187 cpu_crit: cpu-crit { 188 temperature = <110000>; /* 110C */ 189 hysteresis = <2000>; 190 type = "critical"; 191 }; 192 cpu_alert: cpu-alert { 193 temperature = <100000>; /* 100C */ 194 hysteresis = <2000>; 195 type = "passive"; 196 }; 197 }; 198 199 cooling-maps { 200 map0 { 201 trip = <&cpu_alert>; 202 cooling-device = <&cpu0 203 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 204 }; 205 map1 { 206 trip = <&cpu_alert>; 207 cooling-device = <&cpu2 208 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209 }; 210 }; 211 }; 212 }; 213 214 soc@0 { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges = <0 0 0 0xffffffff>; 219 220 serial0: serial@54006800 { 221 compatible = "socionext,uniphier-uart"; 222 status = "disabled"; 223 reg = <0x54006800 0x40>; 224 interrupts = <0 33 4>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_uart0>; 227 clocks = <&peri_clk 0>; 228 }; 229 230 serial1: serial@54006900 { 231 compatible = "socionext,uniphier-uart"; 232 status = "disabled"; 233 reg = <0x54006900 0x40>; 234 interrupts = <0 35 4>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_uart1>; 237 clocks = <&peri_clk 1>; 238 }; 239 240 serial2: serial@54006a00 { 241 compatible = "socionext,uniphier-uart"; 242 status = "disabled"; 243 reg = <0x54006a00 0x40>; 244 interrupts = <0 37 4>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_uart2>; 247 clocks = <&peri_clk 2>; 248 }; 249 250 serial3: serial@54006b00 { 251 compatible = "socionext,uniphier-uart"; 252 status = "disabled"; 253 reg = <0x54006b00 0x40>; 254 interrupts = <0 177 4>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_uart3>; 257 clocks = <&peri_clk 3>; 258 }; 259 260 gpio: gpio@55000000 { 261 compatible = "socionext,uniphier-gpio"; 262 reg = <0x55000000 0x200>; 263 interrupt-parent = <&aidet>; 264 interrupt-controller; 265 #interrupt-cells = <2>; 266 gpio-controller; 267 #gpio-cells = <2>; 268 gpio-ranges = <&pinctrl 0 0 0>, 269 <&pinctrl 96 0 0>, 270 <&pinctrl 160 0 0>; 271 gpio-ranges-group-names = "gpio_range0", 272 "gpio_range1", 273 "gpio_range2"; 274 ngpios = <205>; 275 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 276 <21 217 3>; 277 }; 278 279 adamv@57920000 { 280 compatible = "socionext,uniphier-ld20-adamv", 281 "simple-mfd", "syscon"; 282 reg = <0x57920000 0x1000>; 283 284 adamv_rst: reset { 285 compatible = "socionext,uniphier-ld20-adamv-reset"; 286 #reset-cells = <1>; 287 }; 288 }; 289 290 i2c0: i2c@58780000 { 291 compatible = "socionext,uniphier-fi2c"; 292 status = "disabled"; 293 reg = <0x58780000 0x80>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 interrupts = <0 41 4>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_i2c0>; 299 clocks = <&peri_clk 4>; 300 clock-frequency = <100000>; 301 }; 302 303 i2c1: i2c@58781000 { 304 compatible = "socionext,uniphier-fi2c"; 305 status = "disabled"; 306 reg = <0x58781000 0x80>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 interrupts = <0 42 4>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_i2c1>; 312 clocks = <&peri_clk 5>; 313 clock-frequency = <100000>; 314 }; 315 316 i2c2: i2c@58782000 { 317 compatible = "socionext,uniphier-fi2c"; 318 reg = <0x58782000 0x80>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 interrupts = <0 43 4>; 322 clocks = <&peri_clk 6>; 323 clock-frequency = <400000>; 324 }; 325 326 i2c3: i2c@58783000 { 327 compatible = "socionext,uniphier-fi2c"; 328 status = "disabled"; 329 reg = <0x58783000 0x80>; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 interrupts = <0 44 4>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_i2c3>; 335 clocks = <&peri_clk 7>; 336 clock-frequency = <100000>; 337 }; 338 339 i2c4: i2c@58784000 { 340 compatible = "socionext,uniphier-fi2c"; 341 status = "disabled"; 342 reg = <0x58784000 0x80>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 interrupts = <0 45 4>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_i2c4>; 348 clocks = <&peri_clk 8>; 349 clock-frequency = <100000>; 350 }; 351 352 i2c5: i2c@58785000 { 353 compatible = "socionext,uniphier-fi2c"; 354 reg = <0x58785000 0x80>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 interrupts = <0 25 4>; 358 clocks = <&peri_clk 9>; 359 clock-frequency = <400000>; 360 }; 361 362 system_bus: system-bus@58c00000 { 363 compatible = "socionext,uniphier-system-bus"; 364 status = "disabled"; 365 reg = <0x58c00000 0x400>; 366 #address-cells = <2>; 367 #size-cells = <1>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_system_bus>; 370 }; 371 372 smpctrl@59801000 { 373 compatible = "socionext,uniphier-smpctrl"; 374 reg = <0x59801000 0x400>; 375 }; 376 377 sdctrl@59810000 { 378 compatible = "socionext,uniphier-ld20-sdctrl", 379 "simple-mfd", "syscon"; 380 reg = <0x59810000 0x400>; 381 382 sd_clk: clock { 383 compatible = "socionext,uniphier-ld20-sd-clock"; 384 #clock-cells = <1>; 385 }; 386 387 sd_rst: reset { 388 compatible = "socionext,uniphier-ld20-sd-reset"; 389 #reset-cells = <1>; 390 }; 391 }; 392 393 perictrl@59820000 { 394 compatible = "socionext,uniphier-ld20-perictrl", 395 "simple-mfd", "syscon"; 396 reg = <0x59820000 0x200>; 397 398 peri_clk: clock { 399 compatible = "socionext,uniphier-ld20-peri-clock"; 400 #clock-cells = <1>; 401 }; 402 403 peri_rst: reset { 404 compatible = "socionext,uniphier-ld20-peri-reset"; 405 #reset-cells = <1>; 406 }; 407 }; 408 409 emmc: sdhc@5a000000 { 410 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 411 reg = <0x5a000000 0x400>; 412 interrupts = <0 78 4>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_emmc>; 415 clocks = <&sys_clk 4>; 416 bus-width = <8>; 417 mmc-ddr-1_8v; 418 mmc-hs200-1_8v; 419 cdns,phy-input-delay-legacy = <4>; 420 cdns,phy-input-delay-mmc-highspeed = <2>; 421 cdns,phy-input-delay-mmc-ddr = <3>; 422 cdns,phy-dll-delay-sdclk = <21>; 423 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 424 }; 425 426 soc-glue@5f800000 { 427 compatible = "socionext,uniphier-ld20-soc-glue", 428 "simple-mfd", "syscon"; 429 reg = <0x5f800000 0x2000>; 430 431 pinctrl: pinctrl { 432 compatible = "socionext,uniphier-ld20-pinctrl"; 433 }; 434 }; 435 436 soc-glue@5f900000 { 437 compatible = "socionext,uniphier-ld20-soc-glue-debug", 438 "simple-mfd"; 439 #address-cells = <1>; 440 #size-cells = <1>; 441 ranges = <0 0x5f900000 0x2000>; 442 443 efuse@100 { 444 compatible = "socionext,uniphier-efuse"; 445 reg = <0x100 0x28>; 446 }; 447 448 efuse@200 { 449 compatible = "socionext,uniphier-efuse"; 450 reg = <0x200 0x68>; 451 }; 452 }; 453 454 aidet: aidet@5fc20000 { 455 compatible = "socionext,uniphier-ld20-aidet"; 456 reg = <0x5fc20000 0x200>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 }; 460 461 gic: interrupt-controller@5fe00000 { 462 compatible = "arm,gic-v3"; 463 reg = <0x5fe00000 0x10000>, /* GICD */ 464 <0x5fe80000 0x80000>; /* GICR */ 465 interrupt-controller; 466 #interrupt-cells = <3>; 467 interrupts = <1 9 4>; 468 }; 469 470 sysctrl@61840000 { 471 compatible = "socionext,uniphier-ld20-sysctrl", 472 "simple-mfd", "syscon"; 473 reg = <0x61840000 0x10000>; 474 475 sys_clk: clock { 476 compatible = "socionext,uniphier-ld20-clock"; 477 #clock-cells = <1>; 478 }; 479 480 sys_rst: reset { 481 compatible = "socionext,uniphier-ld20-reset"; 482 #reset-cells = <1>; 483 }; 484 485 watchdog { 486 compatible = "socionext,uniphier-wdt"; 487 }; 488 489 pvtctl: pvtctl { 490 compatible = "socionext,uniphier-ld20-thermal"; 491 interrupts = <0 3 4>; 492 #thermal-sensor-cells = <0>; 493 socionext,tmod-calibration = <0x0f22 0x68ee>; 494 }; 495 }; 496 497 nand: nand@68000000 { 498 compatible = "socionext,uniphier-denali-nand-v5b"; 499 status = "disabled"; 500 reg-names = "nand_data", "denali_reg"; 501 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 502 interrupts = <0 65 4>; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&pinctrl_nand>; 505 clocks = <&sys_clk 2>; 506 }; 507 }; 508}; 509 510#include "uniphier-pinctrl.dtsi" 511