1cea59bd0SMasahiro Yamada/* 2cea59bd0SMasahiro Yamada * Device Tree Source for UniPhier LD20 SoC 3cea59bd0SMasahiro Yamada * 4cea59bd0SMasahiro Yamada * Copyright (C) 2015-2016 Socionext Inc. 5cea59bd0SMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6cea59bd0SMasahiro Yamada * 712301cffSMasahiro Yamada * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8cea59bd0SMasahiro Yamada */ 9cea59bd0SMasahiro Yamada 10b6e5ec20SMasahiro Yamada#include <dt-bindings/gpio/gpio.h> 118311ca57SMasahiro Yamada#include <dt-bindings/gpio/uniphier-gpio.h> 12dba74980SKunihiko Hayashi#include <dt-bindings/thermal/thermal.h> 13dba74980SKunihiko Hayashi 1479d4be39SMasahiro Yamada/memreserve/ 0x80000000 0x02000000; 15cea59bd0SMasahiro Yamada 16cea59bd0SMasahiro Yamada/ { 17cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-ld20"; 18cea59bd0SMasahiro Yamada #address-cells = <2>; 19cea59bd0SMasahiro Yamada #size-cells = <2>; 20cea59bd0SMasahiro Yamada interrupt-parent = <&gic>; 21cea59bd0SMasahiro Yamada 22cea59bd0SMasahiro Yamada cpus { 23cea59bd0SMasahiro Yamada #address-cells = <2>; 24cea59bd0SMasahiro Yamada #size-cells = <0>; 25cea59bd0SMasahiro Yamada 26cea59bd0SMasahiro Yamada cpu-map { 27cea59bd0SMasahiro Yamada cluster0 { 28cea59bd0SMasahiro Yamada core0 { 29cea59bd0SMasahiro Yamada cpu = <&cpu0>; 30cea59bd0SMasahiro Yamada }; 31cea59bd0SMasahiro Yamada core1 { 32cea59bd0SMasahiro Yamada cpu = <&cpu1>; 33cea59bd0SMasahiro Yamada }; 34cea59bd0SMasahiro Yamada }; 35cea59bd0SMasahiro Yamada 36cea59bd0SMasahiro Yamada cluster1 { 37cea59bd0SMasahiro Yamada core0 { 38cea59bd0SMasahiro Yamada cpu = <&cpu2>; 39cea59bd0SMasahiro Yamada }; 40cea59bd0SMasahiro Yamada core1 { 41cea59bd0SMasahiro Yamada cpu = <&cpu3>; 42cea59bd0SMasahiro Yamada }; 43cea59bd0SMasahiro Yamada }; 44cea59bd0SMasahiro Yamada }; 45cea59bd0SMasahiro Yamada 46cea59bd0SMasahiro Yamada cpu0: cpu@0 { 47cea59bd0SMasahiro Yamada device_type = "cpu"; 48cea59bd0SMasahiro Yamada compatible = "arm,cortex-a72", "arm,armv8"; 49cea59bd0SMasahiro Yamada reg = <0 0x000>; 50183ad366SMasahiro Yamada clocks = <&sys_clk 32>; 512f81137fSMasahiro Yamada enable-method = "psci"; 52183ad366SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 53dba74980SKunihiko Hayashi #cooling-cells = <2>; 54cea59bd0SMasahiro Yamada }; 55cea59bd0SMasahiro Yamada 56cea59bd0SMasahiro Yamada cpu1: cpu@1 { 57cea59bd0SMasahiro Yamada device_type = "cpu"; 58cea59bd0SMasahiro Yamada compatible = "arm,cortex-a72", "arm,armv8"; 59cea59bd0SMasahiro Yamada reg = <0 0x001>; 60183ad366SMasahiro Yamada clocks = <&sys_clk 32>; 612f81137fSMasahiro Yamada enable-method = "psci"; 62183ad366SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 63cea59bd0SMasahiro Yamada }; 64cea59bd0SMasahiro Yamada 65cea59bd0SMasahiro Yamada cpu2: cpu@100 { 66cea59bd0SMasahiro Yamada device_type = "cpu"; 67cea59bd0SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 68cea59bd0SMasahiro Yamada reg = <0 0x100>; 69183ad366SMasahiro Yamada clocks = <&sys_clk 33>; 702f81137fSMasahiro Yamada enable-method = "psci"; 71183ad366SMasahiro Yamada operating-points-v2 = <&cluster1_opp>; 72dba74980SKunihiko Hayashi #cooling-cells = <2>; 73cea59bd0SMasahiro Yamada }; 74cea59bd0SMasahiro Yamada 75cea59bd0SMasahiro Yamada cpu3: cpu@101 { 76cea59bd0SMasahiro Yamada device_type = "cpu"; 77cea59bd0SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 78cea59bd0SMasahiro Yamada reg = <0 0x101>; 79183ad366SMasahiro Yamada clocks = <&sys_clk 33>; 802f81137fSMasahiro Yamada enable-method = "psci"; 81183ad366SMasahiro Yamada operating-points-v2 = <&cluster1_opp>; 82183ad366SMasahiro Yamada }; 83183ad366SMasahiro Yamada }; 84183ad366SMasahiro Yamada 859cd7d03fSMasahiro Yamada cluster0_opp: opp-table0 { 86183ad366SMasahiro Yamada compatible = "operating-points-v2"; 87183ad366SMasahiro Yamada opp-shared; 88183ad366SMasahiro Yamada 893fc9a121SViresh Kumar opp-250000000 { 90183ad366SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 91183ad366SMasahiro Yamada clock-latency-ns = <300>; 92183ad366SMasahiro Yamada }; 933fc9a121SViresh Kumar opp-275000000 { 94183ad366SMasahiro Yamada opp-hz = /bits/ 64 <275000000>; 95183ad366SMasahiro Yamada clock-latency-ns = <300>; 96183ad366SMasahiro Yamada }; 973fc9a121SViresh Kumar opp-500000000 { 98183ad366SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 99183ad366SMasahiro Yamada clock-latency-ns = <300>; 100183ad366SMasahiro Yamada }; 1013fc9a121SViresh Kumar opp-550000000 { 102183ad366SMasahiro Yamada opp-hz = /bits/ 64 <550000000>; 103183ad366SMasahiro Yamada clock-latency-ns = <300>; 104183ad366SMasahiro Yamada }; 1053fc9a121SViresh Kumar opp-666667000 { 106183ad366SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 107183ad366SMasahiro Yamada clock-latency-ns = <300>; 108183ad366SMasahiro Yamada }; 1093fc9a121SViresh Kumar opp-733334000 { 110183ad366SMasahiro Yamada opp-hz = /bits/ 64 <733334000>; 111183ad366SMasahiro Yamada clock-latency-ns = <300>; 112183ad366SMasahiro Yamada }; 1133fc9a121SViresh Kumar opp-1000000000 { 114183ad366SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 115183ad366SMasahiro Yamada clock-latency-ns = <300>; 116183ad366SMasahiro Yamada }; 1173fc9a121SViresh Kumar opp-1100000000 { 118183ad366SMasahiro Yamada opp-hz = /bits/ 64 <1100000000>; 119183ad366SMasahiro Yamada clock-latency-ns = <300>; 120183ad366SMasahiro Yamada }; 121183ad366SMasahiro Yamada }; 122183ad366SMasahiro Yamada 1239cd7d03fSMasahiro Yamada cluster1_opp: opp-table1 { 124183ad366SMasahiro Yamada compatible = "operating-points-v2"; 125183ad366SMasahiro Yamada opp-shared; 126183ad366SMasahiro Yamada 1273fc9a121SViresh Kumar opp-250000000 { 128183ad366SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 129183ad366SMasahiro Yamada clock-latency-ns = <300>; 130183ad366SMasahiro Yamada }; 1313fc9a121SViresh Kumar opp-275000000 { 132183ad366SMasahiro Yamada opp-hz = /bits/ 64 <275000000>; 133183ad366SMasahiro Yamada clock-latency-ns = <300>; 134183ad366SMasahiro Yamada }; 1353fc9a121SViresh Kumar opp-500000000 { 136183ad366SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 137183ad366SMasahiro Yamada clock-latency-ns = <300>; 138183ad366SMasahiro Yamada }; 1393fc9a121SViresh Kumar opp-550000000 { 140183ad366SMasahiro Yamada opp-hz = /bits/ 64 <550000000>; 141183ad366SMasahiro Yamada clock-latency-ns = <300>; 142183ad366SMasahiro Yamada }; 1433fc9a121SViresh Kumar opp-666667000 { 144183ad366SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 145183ad366SMasahiro Yamada clock-latency-ns = <300>; 146183ad366SMasahiro Yamada }; 1473fc9a121SViresh Kumar opp-733334000 { 148183ad366SMasahiro Yamada opp-hz = /bits/ 64 <733334000>; 149183ad366SMasahiro Yamada clock-latency-ns = <300>; 150183ad366SMasahiro Yamada }; 1513fc9a121SViresh Kumar opp-1000000000 { 152183ad366SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 153183ad366SMasahiro Yamada clock-latency-ns = <300>; 154183ad366SMasahiro Yamada }; 1553fc9a121SViresh Kumar opp-1100000000 { 156183ad366SMasahiro Yamada opp-hz = /bits/ 64 <1100000000>; 157183ad366SMasahiro Yamada clock-latency-ns = <300>; 158cea59bd0SMasahiro Yamada }; 159cea59bd0SMasahiro Yamada }; 160cea59bd0SMasahiro Yamada 1612f81137fSMasahiro Yamada psci { 1622f81137fSMasahiro Yamada compatible = "arm,psci-1.0"; 1632f81137fSMasahiro Yamada method = "smc"; 1642f81137fSMasahiro Yamada }; 1652f81137fSMasahiro Yamada 166cea59bd0SMasahiro Yamada clocks { 167cea59bd0SMasahiro Yamada refclk: ref { 168cea59bd0SMasahiro Yamada compatible = "fixed-clock"; 169cea59bd0SMasahiro Yamada #clock-cells = <0>; 170cea59bd0SMasahiro Yamada clock-frequency = <25000000>; 171cea59bd0SMasahiro Yamada }; 172cea59bd0SMasahiro Yamada }; 173cea59bd0SMasahiro Yamada 174b6e5ec20SMasahiro Yamada emmc_pwrseq: emmc-pwrseq { 175b6e5ec20SMasahiro Yamada compatible = "mmc-pwrseq-emmc"; 1768311ca57SMasahiro Yamada reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 177b6e5ec20SMasahiro Yamada }; 178b6e5ec20SMasahiro Yamada 179cea59bd0SMasahiro Yamada timer { 180cea59bd0SMasahiro Yamada compatible = "arm,armv8-timer"; 18137179033SArnd Bergmann interrupts = <1 13 4>, 18237179033SArnd Bergmann <1 14 4>, 18337179033SArnd Bergmann <1 11 4>, 18437179033SArnd Bergmann <1 10 4>; 185cea59bd0SMasahiro Yamada }; 186cea59bd0SMasahiro Yamada 187dba74980SKunihiko Hayashi thermal-zones { 188dba74980SKunihiko Hayashi cpu-thermal { 189dba74980SKunihiko Hayashi polling-delay-passive = <250>; /* 250ms */ 190dba74980SKunihiko Hayashi polling-delay = <1000>; /* 1000ms */ 191dba74980SKunihiko Hayashi thermal-sensors = <&pvtctl>; 192dba74980SKunihiko Hayashi 193dba74980SKunihiko Hayashi trips { 194dba74980SKunihiko Hayashi cpu_crit: cpu-crit { 195dba74980SKunihiko Hayashi temperature = <110000>; /* 110C */ 196dba74980SKunihiko Hayashi hysteresis = <2000>; 197dba74980SKunihiko Hayashi type = "critical"; 198dba74980SKunihiko Hayashi }; 199dba74980SKunihiko Hayashi cpu_alert: cpu-alert { 200dba74980SKunihiko Hayashi temperature = <100000>; /* 100C */ 201dba74980SKunihiko Hayashi hysteresis = <2000>; 202dba74980SKunihiko Hayashi type = "passive"; 203dba74980SKunihiko Hayashi }; 204dba74980SKunihiko Hayashi }; 205dba74980SKunihiko Hayashi 206dba74980SKunihiko Hayashi cooling-maps { 207dba74980SKunihiko Hayashi map0 { 208dba74980SKunihiko Hayashi trip = <&cpu_alert>; 209dba74980SKunihiko Hayashi cooling-device = <&cpu0 210dba74980SKunihiko Hayashi THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211dba74980SKunihiko Hayashi }; 212dba74980SKunihiko Hayashi map1 { 213dba74980SKunihiko Hayashi trip = <&cpu_alert>; 214dba74980SKunihiko Hayashi cooling-device = <&cpu2 215dba74980SKunihiko Hayashi THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 216dba74980SKunihiko Hayashi }; 217dba74980SKunihiko Hayashi }; 218dba74980SKunihiko Hayashi }; 219dba74980SKunihiko Hayashi }; 220dba74980SKunihiko Hayashi 221b5027603SMasahiro Yamada soc@0 { 222cea59bd0SMasahiro Yamada compatible = "simple-bus"; 223cea59bd0SMasahiro Yamada #address-cells = <1>; 224cea59bd0SMasahiro Yamada #size-cells = <1>; 225cea59bd0SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 226cea59bd0SMasahiro Yamada 227cea59bd0SMasahiro Yamada serial0: serial@54006800 { 228cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-uart"; 229cea59bd0SMasahiro Yamada status = "disabled"; 230cea59bd0SMasahiro Yamada reg = <0x54006800 0x40>; 231cea59bd0SMasahiro Yamada interrupts = <0 33 4>; 232cea59bd0SMasahiro Yamada pinctrl-names = "default"; 233cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 23442aee275SMasahiro Yamada clocks = <&peri_clk 0>; 23576c48e1eSMasahiro Yamada resets = <&peri_rst 0>; 236cea59bd0SMasahiro Yamada }; 237cea59bd0SMasahiro Yamada 238cea59bd0SMasahiro Yamada serial1: serial@54006900 { 239cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-uart"; 240cea59bd0SMasahiro Yamada status = "disabled"; 241cea59bd0SMasahiro Yamada reg = <0x54006900 0x40>; 242cea59bd0SMasahiro Yamada interrupts = <0 35 4>; 243cea59bd0SMasahiro Yamada pinctrl-names = "default"; 244cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 24542aee275SMasahiro Yamada clocks = <&peri_clk 1>; 24676c48e1eSMasahiro Yamada resets = <&peri_rst 1>; 247cea59bd0SMasahiro Yamada }; 248cea59bd0SMasahiro Yamada 249cea59bd0SMasahiro Yamada serial2: serial@54006a00 { 250cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-uart"; 251cea59bd0SMasahiro Yamada status = "disabled"; 252cea59bd0SMasahiro Yamada reg = <0x54006a00 0x40>; 253cea59bd0SMasahiro Yamada interrupts = <0 37 4>; 254cea59bd0SMasahiro Yamada pinctrl-names = "default"; 255cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 25642aee275SMasahiro Yamada clocks = <&peri_clk 2>; 25776c48e1eSMasahiro Yamada resets = <&peri_rst 2>; 258cea59bd0SMasahiro Yamada }; 259cea59bd0SMasahiro Yamada 260cea59bd0SMasahiro Yamada serial3: serial@54006b00 { 261cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-uart"; 262cea59bd0SMasahiro Yamada status = "disabled"; 263cea59bd0SMasahiro Yamada reg = <0x54006b00 0x40>; 264cea59bd0SMasahiro Yamada interrupts = <0 177 4>; 265cea59bd0SMasahiro Yamada pinctrl-names = "default"; 266cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 26742aee275SMasahiro Yamada clocks = <&peri_clk 3>; 26876c48e1eSMasahiro Yamada resets = <&peri_rst 3>; 269cea59bd0SMasahiro Yamada }; 270cea59bd0SMasahiro Yamada 271277b51e7SMasahiro Yamada gpio: gpio@55000000 { 272277b51e7SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 273277b51e7SMasahiro Yamada reg = <0x55000000 0x200>; 274277b51e7SMasahiro Yamada interrupt-parent = <&aidet>; 275277b51e7SMasahiro Yamada interrupt-controller; 276277b51e7SMasahiro Yamada #interrupt-cells = <2>; 277277b51e7SMasahiro Yamada gpio-controller; 278277b51e7SMasahiro Yamada #gpio-cells = <2>; 279277b51e7SMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 280277b51e7SMasahiro Yamada <&pinctrl 96 0 0>, 281277b51e7SMasahiro Yamada <&pinctrl 160 0 0>; 282277b51e7SMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 283277b51e7SMasahiro Yamada "gpio_range1", 284277b51e7SMasahiro Yamada "gpio_range2"; 285277b51e7SMasahiro Yamada ngpios = <205>; 286277b51e7SMasahiro Yamada socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 287277b51e7SMasahiro Yamada <21 217 3>; 288277b51e7SMasahiro Yamada }; 289277b51e7SMasahiro Yamada 290178b3568SKatsuhiro Suzuki adamv@57920000 { 291178b3568SKatsuhiro Suzuki compatible = "socionext,uniphier-ld20-adamv", 292178b3568SKatsuhiro Suzuki "simple-mfd", "syscon"; 293178b3568SKatsuhiro Suzuki reg = <0x57920000 0x1000>; 294178b3568SKatsuhiro Suzuki 295178b3568SKatsuhiro Suzuki adamv_rst: reset { 296178b3568SKatsuhiro Suzuki compatible = "socionext,uniphier-ld20-adamv-reset"; 297178b3568SKatsuhiro Suzuki #reset-cells = <1>; 298178b3568SKatsuhiro Suzuki }; 299178b3568SKatsuhiro Suzuki }; 300178b3568SKatsuhiro Suzuki 301cea59bd0SMasahiro Yamada i2c0: i2c@58780000 { 302cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 303cea59bd0SMasahiro Yamada status = "disabled"; 304cea59bd0SMasahiro Yamada reg = <0x58780000 0x80>; 305cea59bd0SMasahiro Yamada #address-cells = <1>; 306cea59bd0SMasahiro Yamada #size-cells = <0>; 307cea59bd0SMasahiro Yamada interrupts = <0 41 4>; 308cea59bd0SMasahiro Yamada pinctrl-names = "default"; 309cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 31042aee275SMasahiro Yamada clocks = <&peri_clk 4>; 31176c48e1eSMasahiro Yamada resets = <&peri_rst 4>; 312cea59bd0SMasahiro Yamada clock-frequency = <100000>; 313cea59bd0SMasahiro Yamada }; 314cea59bd0SMasahiro Yamada 315cea59bd0SMasahiro Yamada i2c1: i2c@58781000 { 316cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 317cea59bd0SMasahiro Yamada status = "disabled"; 318cea59bd0SMasahiro Yamada reg = <0x58781000 0x80>; 319cea59bd0SMasahiro Yamada #address-cells = <1>; 320cea59bd0SMasahiro Yamada #size-cells = <0>; 321cea59bd0SMasahiro Yamada interrupts = <0 42 4>; 322cea59bd0SMasahiro Yamada pinctrl-names = "default"; 323cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 32442aee275SMasahiro Yamada clocks = <&peri_clk 5>; 32576c48e1eSMasahiro Yamada resets = <&peri_rst 5>; 326cea59bd0SMasahiro Yamada clock-frequency = <100000>; 327cea59bd0SMasahiro Yamada }; 328cea59bd0SMasahiro Yamada 329cea59bd0SMasahiro Yamada i2c2: i2c@58782000 { 330cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 331cea59bd0SMasahiro Yamada reg = <0x58782000 0x80>; 332cea59bd0SMasahiro Yamada #address-cells = <1>; 333cea59bd0SMasahiro Yamada #size-cells = <0>; 334cea59bd0SMasahiro Yamada interrupts = <0 43 4>; 33542aee275SMasahiro Yamada clocks = <&peri_clk 6>; 33676c48e1eSMasahiro Yamada resets = <&peri_rst 6>; 337cea59bd0SMasahiro Yamada clock-frequency = <400000>; 338cea59bd0SMasahiro Yamada }; 339cea59bd0SMasahiro Yamada 340cea59bd0SMasahiro Yamada i2c3: i2c@58783000 { 341cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 342cea59bd0SMasahiro Yamada status = "disabled"; 343cea59bd0SMasahiro Yamada reg = <0x58783000 0x80>; 344cea59bd0SMasahiro Yamada #address-cells = <1>; 345cea59bd0SMasahiro Yamada #size-cells = <0>; 346cea59bd0SMasahiro Yamada interrupts = <0 44 4>; 347cea59bd0SMasahiro Yamada pinctrl-names = "default"; 348cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 34942aee275SMasahiro Yamada clocks = <&peri_clk 7>; 35076c48e1eSMasahiro Yamada resets = <&peri_rst 7>; 351cea59bd0SMasahiro Yamada clock-frequency = <100000>; 352cea59bd0SMasahiro Yamada }; 353cea59bd0SMasahiro Yamada 354cea59bd0SMasahiro Yamada i2c4: i2c@58784000 { 355cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 356cea59bd0SMasahiro Yamada status = "disabled"; 357cea59bd0SMasahiro Yamada reg = <0x58784000 0x80>; 358cea59bd0SMasahiro Yamada #address-cells = <1>; 359cea59bd0SMasahiro Yamada #size-cells = <0>; 360cea59bd0SMasahiro Yamada interrupts = <0 45 4>; 361cea59bd0SMasahiro Yamada pinctrl-names = "default"; 362cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c4>; 36342aee275SMasahiro Yamada clocks = <&peri_clk 8>; 36476c48e1eSMasahiro Yamada resets = <&peri_rst 8>; 365cea59bd0SMasahiro Yamada clock-frequency = <100000>; 366cea59bd0SMasahiro Yamada }; 367cea59bd0SMasahiro Yamada 368cea59bd0SMasahiro Yamada i2c5: i2c@58785000 { 369cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 370cea59bd0SMasahiro Yamada reg = <0x58785000 0x80>; 371cea59bd0SMasahiro Yamada #address-cells = <1>; 372cea59bd0SMasahiro Yamada #size-cells = <0>; 373cea59bd0SMasahiro Yamada interrupts = <0 25 4>; 37442aee275SMasahiro Yamada clocks = <&peri_clk 9>; 37576c48e1eSMasahiro Yamada resets = <&peri_rst 9>; 376cea59bd0SMasahiro Yamada clock-frequency = <400000>; 377cea59bd0SMasahiro Yamada }; 378cea59bd0SMasahiro Yamada 379cea59bd0SMasahiro Yamada system_bus: system-bus@58c00000 { 380cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 381cea59bd0SMasahiro Yamada status = "disabled"; 382cea59bd0SMasahiro Yamada reg = <0x58c00000 0x400>; 383cea59bd0SMasahiro Yamada #address-cells = <2>; 384cea59bd0SMasahiro Yamada #size-cells = <1>; 3855d9a83c9SMasahiro Yamada pinctrl-names = "default"; 3865d9a83c9SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 387cea59bd0SMasahiro Yamada }; 388cea59bd0SMasahiro Yamada 389b10ee7e3SMasahiro Yamada smpctrl@59801000 { 390cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 391cea59bd0SMasahiro Yamada reg = <0x59801000 0x400>; 392cea59bd0SMasahiro Yamada }; 393cea59bd0SMasahiro Yamada 3948e68c65dSMasahiro Yamada sdctrl@59810000 { 3958e68c65dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sdctrl", 39642aee275SMasahiro Yamada "simple-mfd", "syscon"; 397555861fbSMasahiro Yamada reg = <0x59810000 0x400>; 39842aee275SMasahiro Yamada 3998e68c65dSMasahiro Yamada sd_clk: clock { 4008e68c65dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sd-clock"; 40142aee275SMasahiro Yamada #clock-cells = <1>; 40242aee275SMasahiro Yamada }; 40342aee275SMasahiro Yamada 4048e68c65dSMasahiro Yamada sd_rst: reset { 4058e68c65dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sd-reset"; 40642aee275SMasahiro Yamada #reset-cells = <1>; 40742aee275SMasahiro Yamada }; 40842aee275SMasahiro Yamada }; 40942aee275SMasahiro Yamada 41042aee275SMasahiro Yamada perictrl@59820000 { 411fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld20-perictrl", 41242aee275SMasahiro Yamada "simple-mfd", "syscon"; 41342aee275SMasahiro Yamada reg = <0x59820000 0x200>; 41442aee275SMasahiro Yamada 41542aee275SMasahiro Yamada peri_clk: clock { 41642aee275SMasahiro Yamada compatible = "socionext,uniphier-ld20-peri-clock"; 41742aee275SMasahiro Yamada #clock-cells = <1>; 41842aee275SMasahiro Yamada }; 41942aee275SMasahiro Yamada 42042aee275SMasahiro Yamada peri_rst: reset { 42142aee275SMasahiro Yamada compatible = "socionext,uniphier-ld20-peri-reset"; 42242aee275SMasahiro Yamada #reset-cells = <1>; 42342aee275SMasahiro Yamada }; 42442aee275SMasahiro Yamada }; 42542aee275SMasahiro Yamada 4263a93cc26SMasahiro Yamada emmc: sdhc@5a000000 { 4273a93cc26SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 4283a93cc26SMasahiro Yamada reg = <0x5a000000 0x400>; 4293a93cc26SMasahiro Yamada interrupts = <0 78 4>; 4309c0a9700SMasahiro Yamada pinctrl-names = "default"; 4319c0a9700SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 4323a93cc26SMasahiro Yamada clocks = <&sys_clk 4>; 43376c48e1eSMasahiro Yamada resets = <&sys_rst 4>; 4343a93cc26SMasahiro Yamada bus-width = <8>; 4353a93cc26SMasahiro Yamada mmc-ddr-1_8v; 4363a93cc26SMasahiro Yamada mmc-hs200-1_8v; 437b6e5ec20SMasahiro Yamada mmc-pwrseq = <&emmc_pwrseq>; 438ba6f7011SMasahiro Yamada cdns,phy-input-delay-legacy = <4>; 439ba6f7011SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 440ba6f7011SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 441e345ededSMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 442e345ededSMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 4433a93cc26SMasahiro Yamada }; 4443a93cc26SMasahiro Yamada 445cea59bd0SMasahiro Yamada soc-glue@5f800000 { 446fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld20-soc-glue", 4479d4f5505SMasahiro Yamada "simple-mfd", "syscon"; 448cea59bd0SMasahiro Yamada reg = <0x5f800000 0x2000>; 449cea59bd0SMasahiro Yamada 450cea59bd0SMasahiro Yamada pinctrl: pinctrl { 451cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-ld20-pinctrl"; 452cea59bd0SMasahiro Yamada }; 453cea59bd0SMasahiro Yamada }; 454cea59bd0SMasahiro Yamada 455f05851e1SKeiji Hayashibara soc-glue@5f900000 { 456f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-ld20-soc-glue-debug", 457f05851e1SKeiji Hayashibara "simple-mfd"; 458f05851e1SKeiji Hayashibara #address-cells = <1>; 459f05851e1SKeiji Hayashibara #size-cells = <1>; 460f05851e1SKeiji Hayashibara ranges = <0 0x5f900000 0x2000>; 461f05851e1SKeiji Hayashibara 462f05851e1SKeiji Hayashibara efuse@100 { 463f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 464f05851e1SKeiji Hayashibara reg = <0x100 0x28>; 465f05851e1SKeiji Hayashibara }; 466f05851e1SKeiji Hayashibara 467f05851e1SKeiji Hayashibara efuse@200 { 468f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 469f05851e1SKeiji Hayashibara reg = <0x200 0x68>; 470f05851e1SKeiji Hayashibara }; 471f05851e1SKeiji Hayashibara }; 472f05851e1SKeiji Hayashibara 4733dfc6e98SMasahiro Yamada aidet: aidet@5fc20000 { 4743dfc6e98SMasahiro Yamada compatible = "socionext,uniphier-ld20-aidet"; 4753dfc6e98SMasahiro Yamada reg = <0x5fc20000 0x200>; 4763dfc6e98SMasahiro Yamada interrupt-controller; 4773dfc6e98SMasahiro Yamada #interrupt-cells = <2>; 4783dfc6e98SMasahiro Yamada }; 4793dfc6e98SMasahiro Yamada 480cea59bd0SMasahiro Yamada gic: interrupt-controller@5fe00000 { 481cea59bd0SMasahiro Yamada compatible = "arm,gic-v3"; 482cea59bd0SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 483cea59bd0SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 484cea59bd0SMasahiro Yamada interrupt-controller; 485cea59bd0SMasahiro Yamada #interrupt-cells = <3>; 486cea59bd0SMasahiro Yamada interrupts = <1 9 4>; 487cea59bd0SMasahiro Yamada }; 48842aee275SMasahiro Yamada 48942aee275SMasahiro Yamada sysctrl@61840000 { 490fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld20-sysctrl", 49142aee275SMasahiro Yamada "simple-mfd", "syscon"; 4921ef64af8SMasahiro Yamada reg = <0x61840000 0x10000>; 49342aee275SMasahiro Yamada 49442aee275SMasahiro Yamada sys_clk: clock { 49542aee275SMasahiro Yamada compatible = "socionext,uniphier-ld20-clock"; 49642aee275SMasahiro Yamada #clock-cells = <1>; 49742aee275SMasahiro Yamada }; 49842aee275SMasahiro Yamada 49942aee275SMasahiro Yamada sys_rst: reset { 50042aee275SMasahiro Yamada compatible = "socionext,uniphier-ld20-reset"; 50142aee275SMasahiro Yamada #reset-cells = <1>; 50242aee275SMasahiro Yamada }; 5034c4c960aSKeiji Hayashibara 5044c4c960aSKeiji Hayashibara watchdog { 5054c4c960aSKeiji Hayashibara compatible = "socionext,uniphier-wdt"; 5064c4c960aSKeiji Hayashibara }; 507dba74980SKunihiko Hayashi 508dba74980SKunihiko Hayashi pvtctl: pvtctl { 509dba74980SKunihiko Hayashi compatible = "socionext,uniphier-ld20-thermal"; 510dba74980SKunihiko Hayashi interrupts = <0 3 4>; 511dba74980SKunihiko Hayashi #thermal-sensor-cells = <0>; 512dba74980SKunihiko Hayashi socionext,tmod-calibration = <0x0f22 0x68ee>; 513dba74980SKunihiko Hayashi }; 51442aee275SMasahiro Yamada }; 515e5aefb38SMasahiro Yamada 516e5aefb38SMasahiro Yamada nand: nand@68000000 { 517e5aefb38SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 518e5aefb38SMasahiro Yamada status = "disabled"; 519e5aefb38SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 520e5aefb38SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 521e5aefb38SMasahiro Yamada interrupts = <0 65 4>; 522e5aefb38SMasahiro Yamada pinctrl-names = "default"; 523e5aefb38SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 524e5aefb38SMasahiro Yamada clocks = <&sys_clk 2>; 52576c48e1eSMasahiro Yamada resets = <&sys_rst 2>; 526e5aefb38SMasahiro Yamada }; 527cea59bd0SMasahiro Yamada }; 528cea59bd0SMasahiro Yamada}; 529cea59bd0SMasahiro Yamada 5305740ea4eSMasahiro Yamada#include "uniphier-pinctrl.dtsi" 531