1cea59bd0SMasahiro Yamada/* 2cea59bd0SMasahiro Yamada * Device Tree Source for UniPhier LD20 SoC 3cea59bd0SMasahiro Yamada * 4cea59bd0SMasahiro Yamada * Copyright (C) 2015-2016 Socionext Inc. 5cea59bd0SMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6cea59bd0SMasahiro Yamada * 712301cffSMasahiro Yamada * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8cea59bd0SMasahiro Yamada */ 9cea59bd0SMasahiro Yamada 10b6e5ec20SMasahiro Yamada#include <dt-bindings/gpio/gpio.h> 11dba74980SKunihiko Hayashi#include <dt-bindings/thermal/thermal.h> 12dba74980SKunihiko Hayashi 1379d4be39SMasahiro Yamada/memreserve/ 0x80000000 0x02000000; 14cea59bd0SMasahiro Yamada 15cea59bd0SMasahiro Yamada/ { 16cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-ld20"; 17cea59bd0SMasahiro Yamada #address-cells = <2>; 18cea59bd0SMasahiro Yamada #size-cells = <2>; 19cea59bd0SMasahiro Yamada interrupt-parent = <&gic>; 20cea59bd0SMasahiro Yamada 21cea59bd0SMasahiro Yamada cpus { 22cea59bd0SMasahiro Yamada #address-cells = <2>; 23cea59bd0SMasahiro Yamada #size-cells = <0>; 24cea59bd0SMasahiro Yamada 25cea59bd0SMasahiro Yamada cpu-map { 26cea59bd0SMasahiro Yamada cluster0 { 27cea59bd0SMasahiro Yamada core0 { 28cea59bd0SMasahiro Yamada cpu = <&cpu0>; 29cea59bd0SMasahiro Yamada }; 30cea59bd0SMasahiro Yamada core1 { 31cea59bd0SMasahiro Yamada cpu = <&cpu1>; 32cea59bd0SMasahiro Yamada }; 33cea59bd0SMasahiro Yamada }; 34cea59bd0SMasahiro Yamada 35cea59bd0SMasahiro Yamada cluster1 { 36cea59bd0SMasahiro Yamada core0 { 37cea59bd0SMasahiro Yamada cpu = <&cpu2>; 38cea59bd0SMasahiro Yamada }; 39cea59bd0SMasahiro Yamada core1 { 40cea59bd0SMasahiro Yamada cpu = <&cpu3>; 41cea59bd0SMasahiro Yamada }; 42cea59bd0SMasahiro Yamada }; 43cea59bd0SMasahiro Yamada }; 44cea59bd0SMasahiro Yamada 45cea59bd0SMasahiro Yamada cpu0: cpu@0 { 46cea59bd0SMasahiro Yamada device_type = "cpu"; 47cea59bd0SMasahiro Yamada compatible = "arm,cortex-a72", "arm,armv8"; 48cea59bd0SMasahiro Yamada reg = <0 0x000>; 49183ad366SMasahiro Yamada clocks = <&sys_clk 32>; 502f81137fSMasahiro Yamada enable-method = "psci"; 51183ad366SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 52dba74980SKunihiko Hayashi #cooling-cells = <2>; 53cea59bd0SMasahiro Yamada }; 54cea59bd0SMasahiro Yamada 55cea59bd0SMasahiro Yamada cpu1: cpu@1 { 56cea59bd0SMasahiro Yamada device_type = "cpu"; 57cea59bd0SMasahiro Yamada compatible = "arm,cortex-a72", "arm,armv8"; 58cea59bd0SMasahiro Yamada reg = <0 0x001>; 59183ad366SMasahiro Yamada clocks = <&sys_clk 32>; 602f81137fSMasahiro Yamada enable-method = "psci"; 61183ad366SMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 62cea59bd0SMasahiro Yamada }; 63cea59bd0SMasahiro Yamada 64cea59bd0SMasahiro Yamada cpu2: cpu@100 { 65cea59bd0SMasahiro Yamada device_type = "cpu"; 66cea59bd0SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 67cea59bd0SMasahiro Yamada reg = <0 0x100>; 68183ad366SMasahiro Yamada clocks = <&sys_clk 33>; 692f81137fSMasahiro Yamada enable-method = "psci"; 70183ad366SMasahiro Yamada operating-points-v2 = <&cluster1_opp>; 71dba74980SKunihiko Hayashi #cooling-cells = <2>; 72cea59bd0SMasahiro Yamada }; 73cea59bd0SMasahiro Yamada 74cea59bd0SMasahiro Yamada cpu3: cpu@101 { 75cea59bd0SMasahiro Yamada device_type = "cpu"; 76cea59bd0SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 77cea59bd0SMasahiro Yamada reg = <0 0x101>; 78183ad366SMasahiro Yamada clocks = <&sys_clk 33>; 792f81137fSMasahiro Yamada enable-method = "psci"; 80183ad366SMasahiro Yamada operating-points-v2 = <&cluster1_opp>; 81183ad366SMasahiro Yamada }; 82183ad366SMasahiro Yamada }; 83183ad366SMasahiro Yamada 849cd7d03fSMasahiro Yamada cluster0_opp: opp-table0 { 85183ad366SMasahiro Yamada compatible = "operating-points-v2"; 86183ad366SMasahiro Yamada opp-shared; 87183ad366SMasahiro Yamada 883fc9a121SViresh Kumar opp-250000000 { 89183ad366SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 90183ad366SMasahiro Yamada clock-latency-ns = <300>; 91183ad366SMasahiro Yamada }; 923fc9a121SViresh Kumar opp-275000000 { 93183ad366SMasahiro Yamada opp-hz = /bits/ 64 <275000000>; 94183ad366SMasahiro Yamada clock-latency-ns = <300>; 95183ad366SMasahiro Yamada }; 963fc9a121SViresh Kumar opp-500000000 { 97183ad366SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 98183ad366SMasahiro Yamada clock-latency-ns = <300>; 99183ad366SMasahiro Yamada }; 1003fc9a121SViresh Kumar opp-550000000 { 101183ad366SMasahiro Yamada opp-hz = /bits/ 64 <550000000>; 102183ad366SMasahiro Yamada clock-latency-ns = <300>; 103183ad366SMasahiro Yamada }; 1043fc9a121SViresh Kumar opp-666667000 { 105183ad366SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 106183ad366SMasahiro Yamada clock-latency-ns = <300>; 107183ad366SMasahiro Yamada }; 1083fc9a121SViresh Kumar opp-733334000 { 109183ad366SMasahiro Yamada opp-hz = /bits/ 64 <733334000>; 110183ad366SMasahiro Yamada clock-latency-ns = <300>; 111183ad366SMasahiro Yamada }; 1123fc9a121SViresh Kumar opp-1000000000 { 113183ad366SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 114183ad366SMasahiro Yamada clock-latency-ns = <300>; 115183ad366SMasahiro Yamada }; 1163fc9a121SViresh Kumar opp-1100000000 { 117183ad366SMasahiro Yamada opp-hz = /bits/ 64 <1100000000>; 118183ad366SMasahiro Yamada clock-latency-ns = <300>; 119183ad366SMasahiro Yamada }; 120183ad366SMasahiro Yamada }; 121183ad366SMasahiro Yamada 1229cd7d03fSMasahiro Yamada cluster1_opp: opp-table1 { 123183ad366SMasahiro Yamada compatible = "operating-points-v2"; 124183ad366SMasahiro Yamada opp-shared; 125183ad366SMasahiro Yamada 1263fc9a121SViresh Kumar opp-250000000 { 127183ad366SMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 128183ad366SMasahiro Yamada clock-latency-ns = <300>; 129183ad366SMasahiro Yamada }; 1303fc9a121SViresh Kumar opp-275000000 { 131183ad366SMasahiro Yamada opp-hz = /bits/ 64 <275000000>; 132183ad366SMasahiro Yamada clock-latency-ns = <300>; 133183ad366SMasahiro Yamada }; 1343fc9a121SViresh Kumar opp-500000000 { 135183ad366SMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 136183ad366SMasahiro Yamada clock-latency-ns = <300>; 137183ad366SMasahiro Yamada }; 1383fc9a121SViresh Kumar opp-550000000 { 139183ad366SMasahiro Yamada opp-hz = /bits/ 64 <550000000>; 140183ad366SMasahiro Yamada clock-latency-ns = <300>; 141183ad366SMasahiro Yamada }; 1423fc9a121SViresh Kumar opp-666667000 { 143183ad366SMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 144183ad366SMasahiro Yamada clock-latency-ns = <300>; 145183ad366SMasahiro Yamada }; 1463fc9a121SViresh Kumar opp-733334000 { 147183ad366SMasahiro Yamada opp-hz = /bits/ 64 <733334000>; 148183ad366SMasahiro Yamada clock-latency-ns = <300>; 149183ad366SMasahiro Yamada }; 1503fc9a121SViresh Kumar opp-1000000000 { 151183ad366SMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 152183ad366SMasahiro Yamada clock-latency-ns = <300>; 153183ad366SMasahiro Yamada }; 1543fc9a121SViresh Kumar opp-1100000000 { 155183ad366SMasahiro Yamada opp-hz = /bits/ 64 <1100000000>; 156183ad366SMasahiro Yamada clock-latency-ns = <300>; 157cea59bd0SMasahiro Yamada }; 158cea59bd0SMasahiro Yamada }; 159cea59bd0SMasahiro Yamada 1602f81137fSMasahiro Yamada psci { 1612f81137fSMasahiro Yamada compatible = "arm,psci-1.0"; 1622f81137fSMasahiro Yamada method = "smc"; 1632f81137fSMasahiro Yamada }; 1642f81137fSMasahiro Yamada 165cea59bd0SMasahiro Yamada clocks { 166cea59bd0SMasahiro Yamada refclk: ref { 167cea59bd0SMasahiro Yamada compatible = "fixed-clock"; 168cea59bd0SMasahiro Yamada #clock-cells = <0>; 169cea59bd0SMasahiro Yamada clock-frequency = <25000000>; 170cea59bd0SMasahiro Yamada }; 171cea59bd0SMasahiro Yamada }; 172cea59bd0SMasahiro Yamada 173b6e5ec20SMasahiro Yamada emmc_pwrseq: emmc-pwrseq { 174b6e5ec20SMasahiro Yamada compatible = "mmc-pwrseq-emmc"; 175b6e5ec20SMasahiro Yamada reset-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; 176b6e5ec20SMasahiro Yamada }; 177b6e5ec20SMasahiro Yamada 178cea59bd0SMasahiro Yamada timer { 179cea59bd0SMasahiro Yamada compatible = "arm,armv8-timer"; 18037179033SArnd Bergmann interrupts = <1 13 4>, 18137179033SArnd Bergmann <1 14 4>, 18237179033SArnd Bergmann <1 11 4>, 18337179033SArnd Bergmann <1 10 4>; 184cea59bd0SMasahiro Yamada }; 185cea59bd0SMasahiro Yamada 186dba74980SKunihiko Hayashi thermal-zones { 187dba74980SKunihiko Hayashi cpu-thermal { 188dba74980SKunihiko Hayashi polling-delay-passive = <250>; /* 250ms */ 189dba74980SKunihiko Hayashi polling-delay = <1000>; /* 1000ms */ 190dba74980SKunihiko Hayashi thermal-sensors = <&pvtctl>; 191dba74980SKunihiko Hayashi 192dba74980SKunihiko Hayashi trips { 193dba74980SKunihiko Hayashi cpu_crit: cpu-crit { 194dba74980SKunihiko Hayashi temperature = <110000>; /* 110C */ 195dba74980SKunihiko Hayashi hysteresis = <2000>; 196dba74980SKunihiko Hayashi type = "critical"; 197dba74980SKunihiko Hayashi }; 198dba74980SKunihiko Hayashi cpu_alert: cpu-alert { 199dba74980SKunihiko Hayashi temperature = <100000>; /* 100C */ 200dba74980SKunihiko Hayashi hysteresis = <2000>; 201dba74980SKunihiko Hayashi type = "passive"; 202dba74980SKunihiko Hayashi }; 203dba74980SKunihiko Hayashi }; 204dba74980SKunihiko Hayashi 205dba74980SKunihiko Hayashi cooling-maps { 206dba74980SKunihiko Hayashi map0 { 207dba74980SKunihiko Hayashi trip = <&cpu_alert>; 208dba74980SKunihiko Hayashi cooling-device = <&cpu0 209dba74980SKunihiko Hayashi THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 210dba74980SKunihiko Hayashi }; 211dba74980SKunihiko Hayashi map1 { 212dba74980SKunihiko Hayashi trip = <&cpu_alert>; 213dba74980SKunihiko Hayashi cooling-device = <&cpu2 214dba74980SKunihiko Hayashi THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 215dba74980SKunihiko Hayashi }; 216dba74980SKunihiko Hayashi }; 217dba74980SKunihiko Hayashi }; 218dba74980SKunihiko Hayashi }; 219dba74980SKunihiko Hayashi 220b5027603SMasahiro Yamada soc@0 { 221cea59bd0SMasahiro Yamada compatible = "simple-bus"; 222cea59bd0SMasahiro Yamada #address-cells = <1>; 223cea59bd0SMasahiro Yamada #size-cells = <1>; 224cea59bd0SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 225cea59bd0SMasahiro Yamada 226cea59bd0SMasahiro Yamada serial0: serial@54006800 { 227cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-uart"; 228cea59bd0SMasahiro Yamada status = "disabled"; 229cea59bd0SMasahiro Yamada reg = <0x54006800 0x40>; 230cea59bd0SMasahiro Yamada interrupts = <0 33 4>; 231cea59bd0SMasahiro Yamada pinctrl-names = "default"; 232cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 23342aee275SMasahiro Yamada clocks = <&peri_clk 0>; 23476c48e1eSMasahiro Yamada resets = <&peri_rst 0>; 235cea59bd0SMasahiro Yamada }; 236cea59bd0SMasahiro Yamada 237cea59bd0SMasahiro Yamada serial1: serial@54006900 { 238cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-uart"; 239cea59bd0SMasahiro Yamada status = "disabled"; 240cea59bd0SMasahiro Yamada reg = <0x54006900 0x40>; 241cea59bd0SMasahiro Yamada interrupts = <0 35 4>; 242cea59bd0SMasahiro Yamada pinctrl-names = "default"; 243cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 24442aee275SMasahiro Yamada clocks = <&peri_clk 1>; 24576c48e1eSMasahiro Yamada resets = <&peri_rst 1>; 246cea59bd0SMasahiro Yamada }; 247cea59bd0SMasahiro Yamada 248cea59bd0SMasahiro Yamada serial2: serial@54006a00 { 249cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-uart"; 250cea59bd0SMasahiro Yamada status = "disabled"; 251cea59bd0SMasahiro Yamada reg = <0x54006a00 0x40>; 252cea59bd0SMasahiro Yamada interrupts = <0 37 4>; 253cea59bd0SMasahiro Yamada pinctrl-names = "default"; 254cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 25542aee275SMasahiro Yamada clocks = <&peri_clk 2>; 25676c48e1eSMasahiro Yamada resets = <&peri_rst 2>; 257cea59bd0SMasahiro Yamada }; 258cea59bd0SMasahiro Yamada 259cea59bd0SMasahiro Yamada serial3: serial@54006b00 { 260cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-uart"; 261cea59bd0SMasahiro Yamada status = "disabled"; 262cea59bd0SMasahiro Yamada reg = <0x54006b00 0x40>; 263cea59bd0SMasahiro Yamada interrupts = <0 177 4>; 264cea59bd0SMasahiro Yamada pinctrl-names = "default"; 265cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 26642aee275SMasahiro Yamada clocks = <&peri_clk 3>; 26776c48e1eSMasahiro Yamada resets = <&peri_rst 3>; 268cea59bd0SMasahiro Yamada }; 269cea59bd0SMasahiro Yamada 270277b51e7SMasahiro Yamada gpio: gpio@55000000 { 271277b51e7SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 272277b51e7SMasahiro Yamada reg = <0x55000000 0x200>; 273277b51e7SMasahiro Yamada interrupt-parent = <&aidet>; 274277b51e7SMasahiro Yamada interrupt-controller; 275277b51e7SMasahiro Yamada #interrupt-cells = <2>; 276277b51e7SMasahiro Yamada gpio-controller; 277277b51e7SMasahiro Yamada #gpio-cells = <2>; 278277b51e7SMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 279277b51e7SMasahiro Yamada <&pinctrl 96 0 0>, 280277b51e7SMasahiro Yamada <&pinctrl 160 0 0>; 281277b51e7SMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 282277b51e7SMasahiro Yamada "gpio_range1", 283277b51e7SMasahiro Yamada "gpio_range2"; 284277b51e7SMasahiro Yamada ngpios = <205>; 285277b51e7SMasahiro Yamada socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 286277b51e7SMasahiro Yamada <21 217 3>; 287277b51e7SMasahiro Yamada }; 288277b51e7SMasahiro Yamada 289178b3568SKatsuhiro Suzuki adamv@57920000 { 290178b3568SKatsuhiro Suzuki compatible = "socionext,uniphier-ld20-adamv", 291178b3568SKatsuhiro Suzuki "simple-mfd", "syscon"; 292178b3568SKatsuhiro Suzuki reg = <0x57920000 0x1000>; 293178b3568SKatsuhiro Suzuki 294178b3568SKatsuhiro Suzuki adamv_rst: reset { 295178b3568SKatsuhiro Suzuki compatible = "socionext,uniphier-ld20-adamv-reset"; 296178b3568SKatsuhiro Suzuki #reset-cells = <1>; 297178b3568SKatsuhiro Suzuki }; 298178b3568SKatsuhiro Suzuki }; 299178b3568SKatsuhiro Suzuki 300cea59bd0SMasahiro Yamada i2c0: i2c@58780000 { 301cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 302cea59bd0SMasahiro Yamada status = "disabled"; 303cea59bd0SMasahiro Yamada reg = <0x58780000 0x80>; 304cea59bd0SMasahiro Yamada #address-cells = <1>; 305cea59bd0SMasahiro Yamada #size-cells = <0>; 306cea59bd0SMasahiro Yamada interrupts = <0 41 4>; 307cea59bd0SMasahiro Yamada pinctrl-names = "default"; 308cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 30942aee275SMasahiro Yamada clocks = <&peri_clk 4>; 31076c48e1eSMasahiro Yamada resets = <&peri_rst 4>; 311cea59bd0SMasahiro Yamada clock-frequency = <100000>; 312cea59bd0SMasahiro Yamada }; 313cea59bd0SMasahiro Yamada 314cea59bd0SMasahiro Yamada i2c1: i2c@58781000 { 315cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 316cea59bd0SMasahiro Yamada status = "disabled"; 317cea59bd0SMasahiro Yamada reg = <0x58781000 0x80>; 318cea59bd0SMasahiro Yamada #address-cells = <1>; 319cea59bd0SMasahiro Yamada #size-cells = <0>; 320cea59bd0SMasahiro Yamada interrupts = <0 42 4>; 321cea59bd0SMasahiro Yamada pinctrl-names = "default"; 322cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 32342aee275SMasahiro Yamada clocks = <&peri_clk 5>; 32476c48e1eSMasahiro Yamada resets = <&peri_rst 5>; 325cea59bd0SMasahiro Yamada clock-frequency = <100000>; 326cea59bd0SMasahiro Yamada }; 327cea59bd0SMasahiro Yamada 328cea59bd0SMasahiro Yamada i2c2: i2c@58782000 { 329cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 330cea59bd0SMasahiro Yamada reg = <0x58782000 0x80>; 331cea59bd0SMasahiro Yamada #address-cells = <1>; 332cea59bd0SMasahiro Yamada #size-cells = <0>; 333cea59bd0SMasahiro Yamada interrupts = <0 43 4>; 33442aee275SMasahiro Yamada clocks = <&peri_clk 6>; 33576c48e1eSMasahiro Yamada resets = <&peri_rst 6>; 336cea59bd0SMasahiro Yamada clock-frequency = <400000>; 337cea59bd0SMasahiro Yamada }; 338cea59bd0SMasahiro Yamada 339cea59bd0SMasahiro Yamada i2c3: i2c@58783000 { 340cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 341cea59bd0SMasahiro Yamada status = "disabled"; 342cea59bd0SMasahiro Yamada reg = <0x58783000 0x80>; 343cea59bd0SMasahiro Yamada #address-cells = <1>; 344cea59bd0SMasahiro Yamada #size-cells = <0>; 345cea59bd0SMasahiro Yamada interrupts = <0 44 4>; 346cea59bd0SMasahiro Yamada pinctrl-names = "default"; 347cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 34842aee275SMasahiro Yamada clocks = <&peri_clk 7>; 34976c48e1eSMasahiro Yamada resets = <&peri_rst 7>; 350cea59bd0SMasahiro Yamada clock-frequency = <100000>; 351cea59bd0SMasahiro Yamada }; 352cea59bd0SMasahiro Yamada 353cea59bd0SMasahiro Yamada i2c4: i2c@58784000 { 354cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 355cea59bd0SMasahiro Yamada status = "disabled"; 356cea59bd0SMasahiro Yamada reg = <0x58784000 0x80>; 357cea59bd0SMasahiro Yamada #address-cells = <1>; 358cea59bd0SMasahiro Yamada #size-cells = <0>; 359cea59bd0SMasahiro Yamada interrupts = <0 45 4>; 360cea59bd0SMasahiro Yamada pinctrl-names = "default"; 361cea59bd0SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c4>; 36242aee275SMasahiro Yamada clocks = <&peri_clk 8>; 36376c48e1eSMasahiro Yamada resets = <&peri_rst 8>; 364cea59bd0SMasahiro Yamada clock-frequency = <100000>; 365cea59bd0SMasahiro Yamada }; 366cea59bd0SMasahiro Yamada 367cea59bd0SMasahiro Yamada i2c5: i2c@58785000 { 368cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 369cea59bd0SMasahiro Yamada reg = <0x58785000 0x80>; 370cea59bd0SMasahiro Yamada #address-cells = <1>; 371cea59bd0SMasahiro Yamada #size-cells = <0>; 372cea59bd0SMasahiro Yamada interrupts = <0 25 4>; 37342aee275SMasahiro Yamada clocks = <&peri_clk 9>; 37476c48e1eSMasahiro Yamada resets = <&peri_rst 9>; 375cea59bd0SMasahiro Yamada clock-frequency = <400000>; 376cea59bd0SMasahiro Yamada }; 377cea59bd0SMasahiro Yamada 378cea59bd0SMasahiro Yamada system_bus: system-bus@58c00000 { 379cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 380cea59bd0SMasahiro Yamada status = "disabled"; 381cea59bd0SMasahiro Yamada reg = <0x58c00000 0x400>; 382cea59bd0SMasahiro Yamada #address-cells = <2>; 383cea59bd0SMasahiro Yamada #size-cells = <1>; 3845d9a83c9SMasahiro Yamada pinctrl-names = "default"; 3855d9a83c9SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 386cea59bd0SMasahiro Yamada }; 387cea59bd0SMasahiro Yamada 388b10ee7e3SMasahiro Yamada smpctrl@59801000 { 389cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 390cea59bd0SMasahiro Yamada reg = <0x59801000 0x400>; 391cea59bd0SMasahiro Yamada }; 392cea59bd0SMasahiro Yamada 3938e68c65dSMasahiro Yamada sdctrl@59810000 { 3948e68c65dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sdctrl", 39542aee275SMasahiro Yamada "simple-mfd", "syscon"; 396555861fbSMasahiro Yamada reg = <0x59810000 0x400>; 39742aee275SMasahiro Yamada 3988e68c65dSMasahiro Yamada sd_clk: clock { 3998e68c65dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sd-clock"; 40042aee275SMasahiro Yamada #clock-cells = <1>; 40142aee275SMasahiro Yamada }; 40242aee275SMasahiro Yamada 4038e68c65dSMasahiro Yamada sd_rst: reset { 4048e68c65dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sd-reset"; 40542aee275SMasahiro Yamada #reset-cells = <1>; 40642aee275SMasahiro Yamada }; 40742aee275SMasahiro Yamada }; 40842aee275SMasahiro Yamada 40942aee275SMasahiro Yamada perictrl@59820000 { 410fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld20-perictrl", 41142aee275SMasahiro Yamada "simple-mfd", "syscon"; 41242aee275SMasahiro Yamada reg = <0x59820000 0x200>; 41342aee275SMasahiro Yamada 41442aee275SMasahiro Yamada peri_clk: clock { 41542aee275SMasahiro Yamada compatible = "socionext,uniphier-ld20-peri-clock"; 41642aee275SMasahiro Yamada #clock-cells = <1>; 41742aee275SMasahiro Yamada }; 41842aee275SMasahiro Yamada 41942aee275SMasahiro Yamada peri_rst: reset { 42042aee275SMasahiro Yamada compatible = "socionext,uniphier-ld20-peri-reset"; 42142aee275SMasahiro Yamada #reset-cells = <1>; 42242aee275SMasahiro Yamada }; 42342aee275SMasahiro Yamada }; 42442aee275SMasahiro Yamada 4253a93cc26SMasahiro Yamada emmc: sdhc@5a000000 { 4263a93cc26SMasahiro Yamada compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 4273a93cc26SMasahiro Yamada reg = <0x5a000000 0x400>; 4283a93cc26SMasahiro Yamada interrupts = <0 78 4>; 4299c0a9700SMasahiro Yamada pinctrl-names = "default"; 4309c0a9700SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 4313a93cc26SMasahiro Yamada clocks = <&sys_clk 4>; 43276c48e1eSMasahiro Yamada resets = <&sys_rst 4>; 4333a93cc26SMasahiro Yamada bus-width = <8>; 4343a93cc26SMasahiro Yamada mmc-ddr-1_8v; 4353a93cc26SMasahiro Yamada mmc-hs200-1_8v; 436b6e5ec20SMasahiro Yamada mmc-pwrseq = <&emmc_pwrseq>; 437ba6f7011SMasahiro Yamada cdns,phy-input-delay-legacy = <4>; 438ba6f7011SMasahiro Yamada cdns,phy-input-delay-mmc-highspeed = <2>; 439ba6f7011SMasahiro Yamada cdns,phy-input-delay-mmc-ddr = <3>; 440e345ededSMasahiro Yamada cdns,phy-dll-delay-sdclk = <21>; 441e345ededSMasahiro Yamada cdns,phy-dll-delay-sdclk-hsmmc = <21>; 4423a93cc26SMasahiro Yamada }; 4433a93cc26SMasahiro Yamada 444cea59bd0SMasahiro Yamada soc-glue@5f800000 { 445fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld20-soc-glue", 4469d4f5505SMasahiro Yamada "simple-mfd", "syscon"; 447cea59bd0SMasahiro Yamada reg = <0x5f800000 0x2000>; 448cea59bd0SMasahiro Yamada 449cea59bd0SMasahiro Yamada pinctrl: pinctrl { 450cea59bd0SMasahiro Yamada compatible = "socionext,uniphier-ld20-pinctrl"; 451cea59bd0SMasahiro Yamada }; 452cea59bd0SMasahiro Yamada }; 453cea59bd0SMasahiro Yamada 454f05851e1SKeiji Hayashibara soc-glue@5f900000 { 455f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-ld20-soc-glue-debug", 456f05851e1SKeiji Hayashibara "simple-mfd"; 457f05851e1SKeiji Hayashibara #address-cells = <1>; 458f05851e1SKeiji Hayashibara #size-cells = <1>; 459f05851e1SKeiji Hayashibara ranges = <0 0x5f900000 0x2000>; 460f05851e1SKeiji Hayashibara 461f05851e1SKeiji Hayashibara efuse@100 { 462f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 463f05851e1SKeiji Hayashibara reg = <0x100 0x28>; 464f05851e1SKeiji Hayashibara }; 465f05851e1SKeiji Hayashibara 466f05851e1SKeiji Hayashibara efuse@200 { 467f05851e1SKeiji Hayashibara compatible = "socionext,uniphier-efuse"; 468f05851e1SKeiji Hayashibara reg = <0x200 0x68>; 469f05851e1SKeiji Hayashibara }; 470f05851e1SKeiji Hayashibara }; 471f05851e1SKeiji Hayashibara 4723dfc6e98SMasahiro Yamada aidet: aidet@5fc20000 { 4733dfc6e98SMasahiro Yamada compatible = "socionext,uniphier-ld20-aidet"; 4743dfc6e98SMasahiro Yamada reg = <0x5fc20000 0x200>; 4753dfc6e98SMasahiro Yamada interrupt-controller; 4763dfc6e98SMasahiro Yamada #interrupt-cells = <2>; 4773dfc6e98SMasahiro Yamada }; 4783dfc6e98SMasahiro Yamada 479cea59bd0SMasahiro Yamada gic: interrupt-controller@5fe00000 { 480cea59bd0SMasahiro Yamada compatible = "arm,gic-v3"; 481cea59bd0SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 482cea59bd0SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 483cea59bd0SMasahiro Yamada interrupt-controller; 484cea59bd0SMasahiro Yamada #interrupt-cells = <3>; 485cea59bd0SMasahiro Yamada interrupts = <1 9 4>; 486cea59bd0SMasahiro Yamada }; 48742aee275SMasahiro Yamada 48842aee275SMasahiro Yamada sysctrl@61840000 { 489fb28cef0SMasahiro Yamada compatible = "socionext,uniphier-ld20-sysctrl", 49042aee275SMasahiro Yamada "simple-mfd", "syscon"; 4911ef64af8SMasahiro Yamada reg = <0x61840000 0x10000>; 49242aee275SMasahiro Yamada 49342aee275SMasahiro Yamada sys_clk: clock { 49442aee275SMasahiro Yamada compatible = "socionext,uniphier-ld20-clock"; 49542aee275SMasahiro Yamada #clock-cells = <1>; 49642aee275SMasahiro Yamada }; 49742aee275SMasahiro Yamada 49842aee275SMasahiro Yamada sys_rst: reset { 49942aee275SMasahiro Yamada compatible = "socionext,uniphier-ld20-reset"; 50042aee275SMasahiro Yamada #reset-cells = <1>; 50142aee275SMasahiro Yamada }; 5024c4c960aSKeiji Hayashibara 5034c4c960aSKeiji Hayashibara watchdog { 5044c4c960aSKeiji Hayashibara compatible = "socionext,uniphier-wdt"; 5054c4c960aSKeiji Hayashibara }; 506dba74980SKunihiko Hayashi 507dba74980SKunihiko Hayashi pvtctl: pvtctl { 508dba74980SKunihiko Hayashi compatible = "socionext,uniphier-ld20-thermal"; 509dba74980SKunihiko Hayashi interrupts = <0 3 4>; 510dba74980SKunihiko Hayashi #thermal-sensor-cells = <0>; 511dba74980SKunihiko Hayashi socionext,tmod-calibration = <0x0f22 0x68ee>; 512dba74980SKunihiko Hayashi }; 51342aee275SMasahiro Yamada }; 514e5aefb38SMasahiro Yamada 515e5aefb38SMasahiro Yamada nand: nand@68000000 { 516e5aefb38SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5b"; 517e5aefb38SMasahiro Yamada status = "disabled"; 518e5aefb38SMasahiro Yamada reg-names = "nand_data", "denali_reg"; 519e5aefb38SMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 520e5aefb38SMasahiro Yamada interrupts = <0 65 4>; 521e5aefb38SMasahiro Yamada pinctrl-names = "default"; 522e5aefb38SMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 523e5aefb38SMasahiro Yamada clocks = <&sys_clk 2>; 52476c48e1eSMasahiro Yamada resets = <&sys_rst 2>; 525e5aefb38SMasahiro Yamada }; 526cea59bd0SMasahiro Yamada }; 527cea59bd0SMasahiro Yamada}; 528cea59bd0SMasahiro Yamada 5295740ea4eSMasahiro Yamada#include "uniphier-pinctrl.dtsi" 530