xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/socionext/uniphier-ld20.dtsi (revision 4c4c960a)

/*
 * Device Tree Source for UniPhier LD20 SoC
 *
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/memreserve/ 0x80000000 0x02000000;

/ {
	compatible = "socionext,uniphier-ld20";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
				core1 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0 0x000>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0 0x001>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x100>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster1_opp>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x101>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster1_opp>;
		};
	};

	cluster0_opp: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};
		opp-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			clock-latency-ns = <300>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
		opp-550000000 {
			opp-hz = /bits/ 64 <550000000>;
			clock-latency-ns = <300>;
		};
		opp-666667000 {
			opp-hz = /bits/ 64 <666667000>;
			clock-latency-ns = <300>;
		};
		opp-733334000 {
			opp-hz = /bits/ 64 <733334000>;
			clock-latency-ns = <300>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			clock-latency-ns = <300>;
		};
		opp-1100000000 {
			opp-hz = /bits/ 64 <1100000000>;
			clock-latency-ns = <300>;
		};
	};

	cluster1_opp: opp_table1 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};
		opp-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			clock-latency-ns = <300>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
		opp-550000000 {
			opp-hz = /bits/ 64 <550000000>;
			clock-latency-ns = <300>;
		};
		opp-666667000 {
			opp-hz = /bits/ 64 <666667000>;
			clock-latency-ns = <300>;
		};
		opp-733334000 {
			opp-hz = /bits/ 64 <733334000>;
			clock-latency-ns = <300>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			clock-latency-ns = <300>;
		};
		opp-1100000000 {
			opp-hz = /bits/ 64 <1100000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 4>,
			     <1 14 4>,
			     <1 11 4>,
			     <1 10 4>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			clocks = <&peri_clk 6>;
			clock-frequency = <400000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			clock-frequency = <100000>;
		};

		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c4>;
			clocks = <&peri_clk 8>;
			clock-frequency = <100000>;
		};

		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-ld20-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;

			sd_clk: clock {
				compatible = "socionext,uniphier-ld20-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-ld20-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-ld20-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-ld20-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-ld20-peri-reset";
				#reset-cells = <1>;
			};
		};

		emmc: sdhc@5a000000 {
			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
			reg = <0x5a000000 0x400>;
			interrupts = <0 78 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&sys_clk 4>;
			bus-width = <8>;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			cdns,phy-input-delay-legacy = <4>;
			cdns,phy-input-delay-mmc-highspeed = <2>;
			cdns,phy-input-delay-mmc-ddr = <3>;
			cdns,phy-dll-delay-sdclk = <21>;
			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-ld20-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-ld20-pinctrl";
			};
		};

		gic: interrupt-controller@5fe00000 {
			compatible = "arm,gic-v3";
			reg = <0x5fe00000 0x10000>,	/* GICD */
			      <0x5fe80000 0x80000>;	/* GICR */
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 4>;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-ld20-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-ld20-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-ld20-reset";
				#reset-cells = <1>;
			};

			watchdog {
				compatible = "socionext,uniphier-wdt";
			};
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"