14e50d217SPeter Geis// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 24e50d217SPeter Geis/* 34e50d217SPeter Geis * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 44e50d217SPeter Geis */ 54e50d217SPeter Geis 64e50d217SPeter Geis#include <dt-bindings/clock/rk3568-cru.h> 74e50d217SPeter Geis#include <dt-bindings/interrupt-controller/arm-gic.h> 84e50d217SPeter Geis#include <dt-bindings/interrupt-controller/irq.h> 94e50d217SPeter Geis#include <dt-bindings/phy/phy.h> 104e50d217SPeter Geis#include <dt-bindings/pinctrl/rockchip.h> 114e50d217SPeter Geis#include <dt-bindings/power/rk3568-power.h> 124e50d217SPeter Geis#include <dt-bindings/soc/rockchip,boot-mode.h> 134e50d217SPeter Geis#include <dt-bindings/thermal/thermal.h> 144e50d217SPeter Geis 154e50d217SPeter Geis/ { 164e50d217SPeter Geis interrupt-parent = <&gic>; 174e50d217SPeter Geis #address-cells = <2>; 184e50d217SPeter Geis #size-cells = <2>; 194e50d217SPeter Geis 204e50d217SPeter Geis aliases { 214e50d217SPeter Geis gpio0 = &gpio0; 224e50d217SPeter Geis gpio1 = &gpio1; 234e50d217SPeter Geis gpio2 = &gpio2; 244e50d217SPeter Geis gpio3 = &gpio3; 254e50d217SPeter Geis gpio4 = &gpio4; 264e50d217SPeter Geis i2c0 = &i2c0; 274e50d217SPeter Geis i2c1 = &i2c1; 284e50d217SPeter Geis i2c2 = &i2c2; 294e50d217SPeter Geis i2c3 = &i2c3; 304e50d217SPeter Geis i2c4 = &i2c4; 314e50d217SPeter Geis i2c5 = &i2c5; 324e50d217SPeter Geis serial0 = &uart0; 334e50d217SPeter Geis serial1 = &uart1; 344e50d217SPeter Geis serial2 = &uart2; 354e50d217SPeter Geis serial3 = &uart3; 364e50d217SPeter Geis serial4 = &uart4; 374e50d217SPeter Geis serial5 = &uart5; 384e50d217SPeter Geis serial6 = &uart6; 394e50d217SPeter Geis serial7 = &uart7; 404e50d217SPeter Geis serial8 = &uart8; 414e50d217SPeter Geis serial9 = &uart9; 424e50d217SPeter Geis }; 434e50d217SPeter Geis 444e50d217SPeter Geis cpus { 454e50d217SPeter Geis #address-cells = <2>; 464e50d217SPeter Geis #size-cells = <0>; 474e50d217SPeter Geis 484e50d217SPeter Geis cpu0: cpu@0 { 494e50d217SPeter Geis device_type = "cpu"; 504e50d217SPeter Geis compatible = "arm,cortex-a55"; 514e50d217SPeter Geis reg = <0x0 0x0>; 524e50d217SPeter Geis clocks = <&scmi_clk 0>; 534e50d217SPeter Geis enable-method = "psci"; 544e50d217SPeter Geis operating-points-v2 = <&cpu0_opp_table>; 554e50d217SPeter Geis }; 564e50d217SPeter Geis 574e50d217SPeter Geis cpu1: cpu@100 { 584e50d217SPeter Geis device_type = "cpu"; 594e50d217SPeter Geis compatible = "arm,cortex-a55"; 604e50d217SPeter Geis reg = <0x0 0x100>; 614e50d217SPeter Geis enable-method = "psci"; 624e50d217SPeter Geis operating-points-v2 = <&cpu0_opp_table>; 634e50d217SPeter Geis }; 644e50d217SPeter Geis 654e50d217SPeter Geis cpu2: cpu@200 { 664e50d217SPeter Geis device_type = "cpu"; 674e50d217SPeter Geis compatible = "arm,cortex-a55"; 684e50d217SPeter Geis reg = <0x0 0x200>; 694e50d217SPeter Geis enable-method = "psci"; 704e50d217SPeter Geis operating-points-v2 = <&cpu0_opp_table>; 714e50d217SPeter Geis }; 724e50d217SPeter Geis 734e50d217SPeter Geis cpu3: cpu@300 { 744e50d217SPeter Geis device_type = "cpu"; 754e50d217SPeter Geis compatible = "arm,cortex-a55"; 764e50d217SPeter Geis reg = <0x0 0x300>; 774e50d217SPeter Geis enable-method = "psci"; 784e50d217SPeter Geis operating-points-v2 = <&cpu0_opp_table>; 794e50d217SPeter Geis }; 804e50d217SPeter Geis }; 814e50d217SPeter Geis 824e50d217SPeter Geis cpu0_opp_table: cpu0-opp-table { 834e50d217SPeter Geis compatible = "operating-points-v2"; 844e50d217SPeter Geis opp-shared; 854e50d217SPeter Geis 864e50d217SPeter Geis opp-408000000 { 874e50d217SPeter Geis opp-hz = /bits/ 64 <408000000>; 884e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 894e50d217SPeter Geis clock-latency-ns = <40000>; 904e50d217SPeter Geis }; 914e50d217SPeter Geis 924e50d217SPeter Geis opp-600000000 { 934e50d217SPeter Geis opp-hz = /bits/ 64 <600000000>; 944e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 954e50d217SPeter Geis }; 964e50d217SPeter Geis 974e50d217SPeter Geis opp-816000000 { 984e50d217SPeter Geis opp-hz = /bits/ 64 <816000000>; 994e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 1004e50d217SPeter Geis opp-suspend; 1014e50d217SPeter Geis }; 1024e50d217SPeter Geis 1034e50d217SPeter Geis opp-1104000000 { 1044e50d217SPeter Geis opp-hz = /bits/ 64 <1104000000>; 1054e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 1064e50d217SPeter Geis }; 1074e50d217SPeter Geis 1084e50d217SPeter Geis opp-1416000000 { 1094e50d217SPeter Geis opp-hz = /bits/ 64 <1416000000>; 1104e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 1114e50d217SPeter Geis }; 1124e50d217SPeter Geis 1134e50d217SPeter Geis opp-1608000000 { 1144e50d217SPeter Geis opp-hz = /bits/ 64 <1608000000>; 1154e50d217SPeter Geis opp-microvolt = <975000 975000 1150000>; 1164e50d217SPeter Geis }; 1174e50d217SPeter Geis 1184e50d217SPeter Geis opp-1800000000 { 1194e50d217SPeter Geis opp-hz = /bits/ 64 <1800000000>; 1204e50d217SPeter Geis opp-microvolt = <1050000 1050000 1150000>; 1214e50d217SPeter Geis }; 1224e50d217SPeter Geis }; 1234e50d217SPeter Geis 1244e50d217SPeter Geis firmware { 1254e50d217SPeter Geis scmi: scmi { 1264e50d217SPeter Geis compatible = "arm,scmi-smc"; 1274e50d217SPeter Geis arm,smc-id = <0x82000010>; 1284e50d217SPeter Geis shmem = <&scmi_shmem>; 1294e50d217SPeter Geis #address-cells = <1>; 1304e50d217SPeter Geis #size-cells = <0>; 1314e50d217SPeter Geis 1324e50d217SPeter Geis scmi_clk: protocol@14 { 1334e50d217SPeter Geis reg = <0x14>; 1344e50d217SPeter Geis #clock-cells = <1>; 1354e50d217SPeter Geis }; 1364e50d217SPeter Geis }; 1374e50d217SPeter Geis }; 1384e50d217SPeter Geis 1394e50d217SPeter Geis pmu { 1404e50d217SPeter Geis compatible = "arm,cortex-a55-pmu"; 1414e50d217SPeter Geis interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 1424e50d217SPeter Geis <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1434e50d217SPeter Geis <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 1444e50d217SPeter Geis <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1454e50d217SPeter Geis interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1464e50d217SPeter Geis }; 1474e50d217SPeter Geis 1484e50d217SPeter Geis psci { 1494e50d217SPeter Geis compatible = "arm,psci-1.0"; 1504e50d217SPeter Geis method = "smc"; 1514e50d217SPeter Geis }; 1524e50d217SPeter Geis 1534e50d217SPeter Geis timer { 1544e50d217SPeter Geis compatible = "arm,armv8-timer"; 1554e50d217SPeter Geis interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 1564e50d217SPeter Geis <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 1574e50d217SPeter Geis <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 1584e50d217SPeter Geis <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 1594e50d217SPeter Geis arm,no-tick-in-suspend; 1604e50d217SPeter Geis }; 1614e50d217SPeter Geis 1624e50d217SPeter Geis xin24m: xin24m { 1634e50d217SPeter Geis compatible = "fixed-clock"; 1644e50d217SPeter Geis clock-frequency = <24000000>; 1654e50d217SPeter Geis clock-output-names = "xin24m"; 1664e50d217SPeter Geis #clock-cells = <0>; 1674e50d217SPeter Geis }; 1684e50d217SPeter Geis 1694e50d217SPeter Geis xin32k: xin32k { 1704e50d217SPeter Geis compatible = "fixed-clock"; 1714e50d217SPeter Geis clock-frequency = <32768>; 1724e50d217SPeter Geis clock-output-names = "xin32k"; 1734e50d217SPeter Geis pinctrl-0 = <&clk32k_out0>; 1744e50d217SPeter Geis pinctrl-names = "default"; 1754e50d217SPeter Geis #clock-cells = <0>; 1764e50d217SPeter Geis }; 1774e50d217SPeter Geis 1784e50d217SPeter Geis sram@10f000 { 1794e50d217SPeter Geis compatible = "mmio-sram"; 1804e50d217SPeter Geis reg = <0x0 0x0010f000 0x0 0x100>; 1814e50d217SPeter Geis #address-cells = <1>; 1824e50d217SPeter Geis #size-cells = <1>; 1834e50d217SPeter Geis ranges = <0 0x0 0x0010f000 0x100>; 1844e50d217SPeter Geis 1854e50d217SPeter Geis scmi_shmem: sram@0 { 1864e50d217SPeter Geis compatible = "arm,scmi-shmem"; 1874e50d217SPeter Geis reg = <0x0 0x100>; 1884e50d217SPeter Geis }; 1894e50d217SPeter Geis }; 1904e50d217SPeter Geis 1914e50d217SPeter Geis gic: interrupt-controller@fd400000 { 1924e50d217SPeter Geis compatible = "arm,gic-v3"; 1934e50d217SPeter Geis reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 1944e50d217SPeter Geis <0x0 0xfd460000 0 0x80000>; /* GICR */ 1954e50d217SPeter Geis interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1964e50d217SPeter Geis interrupt-controller; 1974e50d217SPeter Geis #interrupt-cells = <3>; 198b6c1a590SPeter Geis mbi-alias = <0x0 0xfd410000>; 1994e50d217SPeter Geis mbi-ranges = <296 24>; 2004e50d217SPeter Geis msi-controller; 2014e50d217SPeter Geis }; 2024e50d217SPeter Geis 2034e50d217SPeter Geis pmugrf: syscon@fdc20000 { 2044e50d217SPeter Geis compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 2054e50d217SPeter Geis reg = <0x0 0xfdc20000 0x0 0x10000>; 2064e50d217SPeter Geis }; 2074e50d217SPeter Geis 2084e50d217SPeter Geis grf: syscon@fdc60000 { 2094e50d217SPeter Geis compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 2104e50d217SPeter Geis reg = <0x0 0xfdc60000 0x0 0x10000>; 2114e50d217SPeter Geis }; 2124e50d217SPeter Geis 2134e50d217SPeter Geis pmucru: clock-controller@fdd00000 { 2144e50d217SPeter Geis compatible = "rockchip,rk3568-pmucru"; 2154e50d217SPeter Geis reg = <0x0 0xfdd00000 0x0 0x1000>; 2164e50d217SPeter Geis #clock-cells = <1>; 2174e50d217SPeter Geis #reset-cells = <1>; 2184e50d217SPeter Geis }; 2194e50d217SPeter Geis 2204e50d217SPeter Geis cru: clock-controller@fdd20000 { 2214e50d217SPeter Geis compatible = "rockchip,rk3568-cru"; 2224e50d217SPeter Geis reg = <0x0 0xfdd20000 0x0 0x1000>; 2234e50d217SPeter Geis #clock-cells = <1>; 2244e50d217SPeter Geis #reset-cells = <1>; 225*f7c5b9c2SPeter Geis assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 226*f7c5b9c2SPeter Geis assigned-clock-rates = <1200000000>, <200000000>; 2274e50d217SPeter Geis }; 2284e50d217SPeter Geis 2294e50d217SPeter Geis i2c0: i2c@fdd40000 { 2304e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 2314e50d217SPeter Geis reg = <0x0 0xfdd40000 0x0 0x1000>; 2324e50d217SPeter Geis interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 2334e50d217SPeter Geis clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 2344e50d217SPeter Geis clock-names = "i2c", "pclk"; 2354e50d217SPeter Geis pinctrl-0 = <&i2c0_xfer>; 2364e50d217SPeter Geis pinctrl-names = "default"; 2374e50d217SPeter Geis #address-cells = <1>; 2384e50d217SPeter Geis #size-cells = <0>; 2394e50d217SPeter Geis status = "disabled"; 2404e50d217SPeter Geis }; 2414e50d217SPeter Geis 2424e50d217SPeter Geis uart0: serial@fdd50000 { 2434e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2444e50d217SPeter Geis reg = <0x0 0xfdd50000 0x0 0x100>; 2454e50d217SPeter Geis interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2464e50d217SPeter Geis clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 2474e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 2484e50d217SPeter Geis dmas = <&dmac0 0>, <&dmac0 1>; 2494e50d217SPeter Geis pinctrl-0 = <&uart0_xfer>; 2504e50d217SPeter Geis pinctrl-names = "default"; 2514e50d217SPeter Geis reg-io-width = <4>; 2524e50d217SPeter Geis reg-shift = <2>; 2534e50d217SPeter Geis status = "disabled"; 2544e50d217SPeter Geis }; 2554e50d217SPeter Geis 2564e50d217SPeter Geis pmu: power-management@fdd90000 { 2574e50d217SPeter Geis compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 2584e50d217SPeter Geis reg = <0x0 0xfdd90000 0x0 0x1000>; 2594e50d217SPeter Geis 2604e50d217SPeter Geis power: power-controller { 2614e50d217SPeter Geis compatible = "rockchip,rk3568-power-controller"; 2624e50d217SPeter Geis #power-domain-cells = <1>; 2634e50d217SPeter Geis #address-cells = <1>; 2644e50d217SPeter Geis #size-cells = <0>; 2654e50d217SPeter Geis 2664e50d217SPeter Geis /* These power domains are grouped by VD_GPU */ 2674e50d217SPeter Geis power-domain@RK3568_PD_GPU { 2684e50d217SPeter Geis reg = <RK3568_PD_GPU>; 2694e50d217SPeter Geis clocks = <&cru ACLK_GPU_PRE>, 2704e50d217SPeter Geis <&cru PCLK_GPU_PRE>; 2714e50d217SPeter Geis pm_qos = <&qos_gpu>; 2724e50d217SPeter Geis #power-domain-cells = <0>; 2734e50d217SPeter Geis }; 2744e50d217SPeter Geis 2754e50d217SPeter Geis /* These power domains are grouped by VD_LOGIC */ 2764e50d217SPeter Geis power-domain@RK3568_PD_VI { 2774e50d217SPeter Geis reg = <RK3568_PD_VI>; 2784e50d217SPeter Geis clocks = <&cru HCLK_VI>, 2794e50d217SPeter Geis <&cru PCLK_VI>; 2804e50d217SPeter Geis pm_qos = <&qos_isp>, 2814e50d217SPeter Geis <&qos_vicap0>, 2824e50d217SPeter Geis <&qos_vicap1>; 2834e50d217SPeter Geis #power-domain-cells = <0>; 2844e50d217SPeter Geis }; 2854e50d217SPeter Geis 2864e50d217SPeter Geis power-domain@RK3568_PD_VO { 2874e50d217SPeter Geis reg = <RK3568_PD_VO>; 2884e50d217SPeter Geis clocks = <&cru HCLK_VO>, 2894e50d217SPeter Geis <&cru PCLK_VO>, 2904e50d217SPeter Geis <&cru ACLK_VOP_PRE>; 2914e50d217SPeter Geis pm_qos = <&qos_hdcp>, 2924e50d217SPeter Geis <&qos_vop_m0>, 2934e50d217SPeter Geis <&qos_vop_m1>; 2944e50d217SPeter Geis #power-domain-cells = <0>; 2954e50d217SPeter Geis }; 2964e50d217SPeter Geis 2974e50d217SPeter Geis power-domain@RK3568_PD_RGA { 2984e50d217SPeter Geis reg = <RK3568_PD_RGA>; 2994e50d217SPeter Geis clocks = <&cru HCLK_RGA_PRE>, 3004e50d217SPeter Geis <&cru PCLK_RGA_PRE>; 3014e50d217SPeter Geis pm_qos = <&qos_ebc>, 3024e50d217SPeter Geis <&qos_iep>, 3034e50d217SPeter Geis <&qos_jpeg_dec>, 3044e50d217SPeter Geis <&qos_jpeg_enc>, 3054e50d217SPeter Geis <&qos_rga_rd>, 3064e50d217SPeter Geis <&qos_rga_wr>; 3074e50d217SPeter Geis #power-domain-cells = <0>; 3084e50d217SPeter Geis }; 3094e50d217SPeter Geis 3104e50d217SPeter Geis power-domain@RK3568_PD_VPU { 3114e50d217SPeter Geis reg = <RK3568_PD_VPU>; 3124e50d217SPeter Geis clocks = <&cru HCLK_VPU_PRE>; 3134e50d217SPeter Geis pm_qos = <&qos_vpu>; 3144e50d217SPeter Geis #power-domain-cells = <0>; 3154e50d217SPeter Geis }; 3164e50d217SPeter Geis 3174e50d217SPeter Geis power-domain@RK3568_PD_RKVDEC { 3184e50d217SPeter Geis clocks = <&cru HCLK_RKVDEC_PRE>; 3194e50d217SPeter Geis reg = <RK3568_PD_RKVDEC>; 3204e50d217SPeter Geis pm_qos = <&qos_rkvdec>; 3214e50d217SPeter Geis #power-domain-cells = <0>; 3224e50d217SPeter Geis }; 3234e50d217SPeter Geis 3244e50d217SPeter Geis power-domain@RK3568_PD_RKVENC { 3254e50d217SPeter Geis reg = <RK3568_PD_RKVENC>; 3264e50d217SPeter Geis clocks = <&cru HCLK_RKVENC_PRE>; 3274e50d217SPeter Geis pm_qos = <&qos_rkvenc_rd_m0>, 3284e50d217SPeter Geis <&qos_rkvenc_rd_m1>, 3294e50d217SPeter Geis <&qos_rkvenc_wr_m0>; 3304e50d217SPeter Geis #power-domain-cells = <0>; 3314e50d217SPeter Geis }; 3324e50d217SPeter Geis }; 3334e50d217SPeter Geis }; 3344e50d217SPeter Geis 3354e50d217SPeter Geis sdmmc2: mmc@fe000000 { 3364e50d217SPeter Geis compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 3374e50d217SPeter Geis reg = <0x0 0xfe000000 0x0 0x4000>; 3384e50d217SPeter Geis interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3394e50d217SPeter Geis clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 3404e50d217SPeter Geis <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 3414e50d217SPeter Geis clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 3424e50d217SPeter Geis fifo-depth = <0x100>; 3434e50d217SPeter Geis max-frequency = <150000000>; 3444e50d217SPeter Geis resets = <&cru SRST_SDMMC2>; 3454e50d217SPeter Geis reset-names = "reset"; 3464e50d217SPeter Geis status = "disabled"; 3474e50d217SPeter Geis }; 3484e50d217SPeter Geis 3490dcec571SPeter Geis gmac1: ethernet@fe010000 { 3500dcec571SPeter Geis compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 3510dcec571SPeter Geis reg = <0x0 0xfe010000 0x0 0x10000>; 3520dcec571SPeter Geis interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 3530dcec571SPeter Geis <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 3540dcec571SPeter Geis interrupt-names = "macirq", "eth_wake_irq"; 3550dcec571SPeter Geis clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 3560dcec571SPeter Geis <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 3570dcec571SPeter Geis <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 3580dcec571SPeter Geis <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 3590dcec571SPeter Geis clock-names = "stmmaceth", "mac_clk_rx", 3600dcec571SPeter Geis "mac_clk_tx", "clk_mac_refout", 3610dcec571SPeter Geis "aclk_mac", "pclk_mac", 3620dcec571SPeter Geis "clk_mac_speed", "ptp_ref"; 3630dcec571SPeter Geis resets = <&cru SRST_A_GMAC1>; 3640dcec571SPeter Geis reset-names = "stmmaceth"; 3650dcec571SPeter Geis rockchip,grf = <&grf>; 3660dcec571SPeter Geis snps,axi-config = <&gmac1_stmmac_axi_setup>; 3670dcec571SPeter Geis snps,mixed-burst; 3680dcec571SPeter Geis snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 3690dcec571SPeter Geis snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 3700dcec571SPeter Geis snps,tso; 3710dcec571SPeter Geis status = "disabled"; 3720dcec571SPeter Geis 3730dcec571SPeter Geis mdio1: mdio { 3740dcec571SPeter Geis compatible = "snps,dwmac-mdio"; 3750dcec571SPeter Geis #address-cells = <0x1>; 3760dcec571SPeter Geis #size-cells = <0x0>; 3770dcec571SPeter Geis }; 3780dcec571SPeter Geis 3790dcec571SPeter Geis gmac1_stmmac_axi_setup: stmmac-axi-config { 3800dcec571SPeter Geis snps,blen = <0 0 0 0 16 8 4>; 3810dcec571SPeter Geis snps,rd_osr_lmt = <8>; 3820dcec571SPeter Geis snps,wr_osr_lmt = <4>; 3830dcec571SPeter Geis }; 3840dcec571SPeter Geis 3850dcec571SPeter Geis gmac1_mtl_rx_setup: rx-queues-config { 3860dcec571SPeter Geis snps,rx-queues-to-use = <1>; 3870dcec571SPeter Geis queue0 {}; 3880dcec571SPeter Geis }; 3890dcec571SPeter Geis 3900dcec571SPeter Geis gmac1_mtl_tx_setup: tx-queues-config { 3910dcec571SPeter Geis snps,tx-queues-to-use = <1>; 3920dcec571SPeter Geis queue0 {}; 3930dcec571SPeter Geis }; 3940dcec571SPeter Geis }; 3950dcec571SPeter Geis 3964e50d217SPeter Geis qos_gpu: qos@fe128000 { 3974e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 3984e50d217SPeter Geis reg = <0x0 0xfe128000 0x0 0x20>; 3994e50d217SPeter Geis }; 4004e50d217SPeter Geis 4014e50d217SPeter Geis qos_rkvenc_rd_m0: qos@fe138080 { 4024e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4034e50d217SPeter Geis reg = <0x0 0xfe138080 0x0 0x20>; 4044e50d217SPeter Geis }; 4054e50d217SPeter Geis 4064e50d217SPeter Geis qos_rkvenc_rd_m1: qos@fe138100 { 4074e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4084e50d217SPeter Geis reg = <0x0 0xfe138100 0x0 0x20>; 4094e50d217SPeter Geis }; 4104e50d217SPeter Geis 4114e50d217SPeter Geis qos_rkvenc_wr_m0: qos@fe138180 { 4124e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4134e50d217SPeter Geis reg = <0x0 0xfe138180 0x0 0x20>; 4144e50d217SPeter Geis }; 4154e50d217SPeter Geis 4164e50d217SPeter Geis qos_isp: qos@fe148000 { 4174e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4184e50d217SPeter Geis reg = <0x0 0xfe148000 0x0 0x20>; 4194e50d217SPeter Geis }; 4204e50d217SPeter Geis 4214e50d217SPeter Geis qos_vicap0: qos@fe148080 { 4224e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4234e50d217SPeter Geis reg = <0x0 0xfe148080 0x0 0x20>; 4244e50d217SPeter Geis }; 4254e50d217SPeter Geis 4264e50d217SPeter Geis qos_vicap1: qos@fe148100 { 4274e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4284e50d217SPeter Geis reg = <0x0 0xfe148100 0x0 0x20>; 4294e50d217SPeter Geis }; 4304e50d217SPeter Geis 4314e50d217SPeter Geis qos_vpu: qos@fe150000 { 4324e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4334e50d217SPeter Geis reg = <0x0 0xfe150000 0x0 0x20>; 4344e50d217SPeter Geis }; 4354e50d217SPeter Geis 4364e50d217SPeter Geis qos_ebc: qos@fe158000 { 4374e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4384e50d217SPeter Geis reg = <0x0 0xfe158000 0x0 0x20>; 4394e50d217SPeter Geis }; 4404e50d217SPeter Geis 4414e50d217SPeter Geis qos_iep: qos@fe158100 { 4424e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4434e50d217SPeter Geis reg = <0x0 0xfe158100 0x0 0x20>; 4444e50d217SPeter Geis }; 4454e50d217SPeter Geis 4464e50d217SPeter Geis qos_jpeg_dec: qos@fe158180 { 4474e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4484e50d217SPeter Geis reg = <0x0 0xfe158180 0x0 0x20>; 4494e50d217SPeter Geis }; 4504e50d217SPeter Geis 4514e50d217SPeter Geis qos_jpeg_enc: qos@fe158200 { 4524e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4534e50d217SPeter Geis reg = <0x0 0xfe158200 0x0 0x20>; 4544e50d217SPeter Geis }; 4554e50d217SPeter Geis 4564e50d217SPeter Geis qos_rga_rd: qos@fe158280 { 4574e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4584e50d217SPeter Geis reg = <0x0 0xfe158280 0x0 0x20>; 4594e50d217SPeter Geis }; 4604e50d217SPeter Geis 4614e50d217SPeter Geis qos_rga_wr: qos@fe158300 { 4624e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4634e50d217SPeter Geis reg = <0x0 0xfe158300 0x0 0x20>; 4644e50d217SPeter Geis }; 4654e50d217SPeter Geis 4664e50d217SPeter Geis qos_npu: qos@fe180000 { 4674e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4684e50d217SPeter Geis reg = <0x0 0xfe180000 0x0 0x20>; 4694e50d217SPeter Geis }; 4704e50d217SPeter Geis 4714e50d217SPeter Geis qos_pcie2x1: qos@fe190000 { 4724e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4734e50d217SPeter Geis reg = <0x0 0xfe190000 0x0 0x20>; 4744e50d217SPeter Geis }; 4754e50d217SPeter Geis 4764e50d217SPeter Geis qos_sata1: qos@fe190280 { 4774e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4784e50d217SPeter Geis reg = <0x0 0xfe190280 0x0 0x20>; 4794e50d217SPeter Geis }; 4804e50d217SPeter Geis 4814e50d217SPeter Geis qos_sata2: qos@fe190300 { 4824e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4834e50d217SPeter Geis reg = <0x0 0xfe190300 0x0 0x20>; 4844e50d217SPeter Geis }; 4854e50d217SPeter Geis 4864e50d217SPeter Geis qos_usb3_0: qos@fe190380 { 4874e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4884e50d217SPeter Geis reg = <0x0 0xfe190380 0x0 0x20>; 4894e50d217SPeter Geis }; 4904e50d217SPeter Geis 4914e50d217SPeter Geis qos_usb3_1: qos@fe190400 { 4924e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4934e50d217SPeter Geis reg = <0x0 0xfe190400 0x0 0x20>; 4944e50d217SPeter Geis }; 4954e50d217SPeter Geis 4964e50d217SPeter Geis qos_rkvdec: qos@fe198000 { 4974e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4984e50d217SPeter Geis reg = <0x0 0xfe198000 0x0 0x20>; 4994e50d217SPeter Geis }; 5004e50d217SPeter Geis 5014e50d217SPeter Geis qos_hdcp: qos@fe1a8000 { 5024e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5034e50d217SPeter Geis reg = <0x0 0xfe1a8000 0x0 0x20>; 5044e50d217SPeter Geis }; 5054e50d217SPeter Geis 5064e50d217SPeter Geis qos_vop_m0: qos@fe1a8080 { 5074e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5084e50d217SPeter Geis reg = <0x0 0xfe1a8080 0x0 0x20>; 5094e50d217SPeter Geis }; 5104e50d217SPeter Geis 5114e50d217SPeter Geis qos_vop_m1: qos@fe1a8100 { 5124e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5134e50d217SPeter Geis reg = <0x0 0xfe1a8100 0x0 0x20>; 5144e50d217SPeter Geis }; 5154e50d217SPeter Geis 5164e50d217SPeter Geis sdmmc0: mmc@fe2b0000 { 5174e50d217SPeter Geis compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 5184e50d217SPeter Geis reg = <0x0 0xfe2b0000 0x0 0x4000>; 5194e50d217SPeter Geis interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 5204e50d217SPeter Geis clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 5214e50d217SPeter Geis <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 5224e50d217SPeter Geis clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 5234e50d217SPeter Geis fifo-depth = <0x100>; 5244e50d217SPeter Geis max-frequency = <150000000>; 5254e50d217SPeter Geis resets = <&cru SRST_SDMMC0>; 5264e50d217SPeter Geis reset-names = "reset"; 5274e50d217SPeter Geis status = "disabled"; 5284e50d217SPeter Geis }; 5294e50d217SPeter Geis 5304e50d217SPeter Geis sdmmc1: mmc@fe2c0000 { 5314e50d217SPeter Geis compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 5324e50d217SPeter Geis reg = <0x0 0xfe2c0000 0x0 0x4000>; 5334e50d217SPeter Geis interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 5344e50d217SPeter Geis clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 5354e50d217SPeter Geis <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 5364e50d217SPeter Geis clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 5374e50d217SPeter Geis fifo-depth = <0x100>; 5384e50d217SPeter Geis max-frequency = <150000000>; 5394e50d217SPeter Geis resets = <&cru SRST_SDMMC1>; 5404e50d217SPeter Geis reset-names = "reset"; 5414e50d217SPeter Geis status = "disabled"; 5424e50d217SPeter Geis }; 5434e50d217SPeter Geis 5444e50d217SPeter Geis sdhci: mmc@fe310000 { 5454e50d217SPeter Geis compatible = "rockchip,rk3568-dwcmshc"; 5464e50d217SPeter Geis reg = <0x0 0xfe310000 0x0 0x10000>; 5474e50d217SPeter Geis interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5484e50d217SPeter Geis assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 5494e50d217SPeter Geis assigned-clock-rates = <200000000>, <24000000>; 5504e50d217SPeter Geis clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 5514e50d217SPeter Geis <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 5524e50d217SPeter Geis <&cru TCLK_EMMC>; 5534e50d217SPeter Geis clock-names = "core", "bus", "axi", "block", "timer"; 5544e50d217SPeter Geis status = "disabled"; 5554e50d217SPeter Geis }; 5564e50d217SPeter Geis 5574e50d217SPeter Geis dmac0: dmac@fe530000 { 5584e50d217SPeter Geis compatible = "arm,pl330", "arm,primecell"; 5594e50d217SPeter Geis reg = <0x0 0xfe530000 0x0 0x4000>; 5604e50d217SPeter Geis interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 5614e50d217SPeter Geis <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5624e50d217SPeter Geis arm,pl330-periph-burst; 5634e50d217SPeter Geis clocks = <&cru ACLK_BUS>; 5644e50d217SPeter Geis clock-names = "apb_pclk"; 5654e50d217SPeter Geis #dma-cells = <1>; 5664e50d217SPeter Geis }; 5674e50d217SPeter Geis 5684e50d217SPeter Geis dmac1: dmac@fe550000 { 5694e50d217SPeter Geis compatible = "arm,pl330", "arm,primecell"; 5704e50d217SPeter Geis reg = <0x0 0xfe550000 0x0 0x4000>; 5714e50d217SPeter Geis interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 5724e50d217SPeter Geis <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 5734e50d217SPeter Geis arm,pl330-periph-burst; 5744e50d217SPeter Geis clocks = <&cru ACLK_BUS>; 5754e50d217SPeter Geis clock-names = "apb_pclk"; 5764e50d217SPeter Geis #dma-cells = <1>; 5774e50d217SPeter Geis }; 5784e50d217SPeter Geis 5794e50d217SPeter Geis i2c1: i2c@fe5a0000 { 5804e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 5814e50d217SPeter Geis reg = <0x0 0xfe5a0000 0x0 0x1000>; 5824e50d217SPeter Geis interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 5834e50d217SPeter Geis clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 5844e50d217SPeter Geis clock-names = "i2c", "pclk"; 5854e50d217SPeter Geis pinctrl-0 = <&i2c1_xfer>; 5864e50d217SPeter Geis pinctrl-names = "default"; 5874e50d217SPeter Geis #address-cells = <1>; 5884e50d217SPeter Geis #size-cells = <0>; 5894e50d217SPeter Geis status = "disabled"; 5904e50d217SPeter Geis }; 5914e50d217SPeter Geis 5924e50d217SPeter Geis i2c2: i2c@fe5b0000 { 5934e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 5944e50d217SPeter Geis reg = <0x0 0xfe5b0000 0x0 0x1000>; 5954e50d217SPeter Geis interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 5964e50d217SPeter Geis clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 5974e50d217SPeter Geis clock-names = "i2c", "pclk"; 5984e50d217SPeter Geis pinctrl-0 = <&i2c2m0_xfer>; 5994e50d217SPeter Geis pinctrl-names = "default"; 6004e50d217SPeter Geis #address-cells = <1>; 6014e50d217SPeter Geis #size-cells = <0>; 6024e50d217SPeter Geis status = "disabled"; 6034e50d217SPeter Geis }; 6044e50d217SPeter Geis 6054e50d217SPeter Geis i2c3: i2c@fe5c0000 { 6064e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 6074e50d217SPeter Geis reg = <0x0 0xfe5c0000 0x0 0x1000>; 6084e50d217SPeter Geis interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 6094e50d217SPeter Geis clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 6104e50d217SPeter Geis clock-names = "i2c", "pclk"; 6114e50d217SPeter Geis pinctrl-0 = <&i2c3m0_xfer>; 6124e50d217SPeter Geis pinctrl-names = "default"; 6134e50d217SPeter Geis #address-cells = <1>; 6144e50d217SPeter Geis #size-cells = <0>; 6154e50d217SPeter Geis status = "disabled"; 6164e50d217SPeter Geis }; 6174e50d217SPeter Geis 6184e50d217SPeter Geis i2c4: i2c@fe5d0000 { 6194e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 6204e50d217SPeter Geis reg = <0x0 0xfe5d0000 0x0 0x1000>; 6214e50d217SPeter Geis interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 6224e50d217SPeter Geis clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 6234e50d217SPeter Geis clock-names = "i2c", "pclk"; 6244e50d217SPeter Geis pinctrl-0 = <&i2c4m0_xfer>; 6254e50d217SPeter Geis pinctrl-names = "default"; 6264e50d217SPeter Geis #address-cells = <1>; 6274e50d217SPeter Geis #size-cells = <0>; 6284e50d217SPeter Geis status = "disabled"; 6294e50d217SPeter Geis }; 6304e50d217SPeter Geis 6314e50d217SPeter Geis i2c5: i2c@fe5e0000 { 6324e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 6334e50d217SPeter Geis reg = <0x0 0xfe5e0000 0x0 0x1000>; 6344e50d217SPeter Geis interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 6354e50d217SPeter Geis clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 6364e50d217SPeter Geis clock-names = "i2c", "pclk"; 6374e50d217SPeter Geis pinctrl-0 = <&i2c5m0_xfer>; 6384e50d217SPeter Geis pinctrl-names = "default"; 6394e50d217SPeter Geis #address-cells = <1>; 6404e50d217SPeter Geis #size-cells = <0>; 6414e50d217SPeter Geis status = "disabled"; 6424e50d217SPeter Geis }; 6434e50d217SPeter Geis 6440edcfec3SLiang Chen wdt: watchdog@fe600000 { 6450edcfec3SLiang Chen compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 6460edcfec3SLiang Chen reg = <0x0 0xfe600000 0x0 0x100>; 6470edcfec3SLiang Chen interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 6480edcfec3SLiang Chen clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 6490edcfec3SLiang Chen clock-names = "tclk", "pclk"; 6500edcfec3SLiang Chen }; 6510edcfec3SLiang Chen 6524e50d217SPeter Geis uart1: serial@fe650000 { 6534e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 6544e50d217SPeter Geis reg = <0x0 0xfe650000 0x0 0x100>; 6554e50d217SPeter Geis interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 6564e50d217SPeter Geis clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 6574e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 6584e50d217SPeter Geis dmas = <&dmac0 2>, <&dmac0 3>; 6594e50d217SPeter Geis pinctrl-0 = <&uart1m0_xfer>; 6604e50d217SPeter Geis pinctrl-names = "default"; 6614e50d217SPeter Geis reg-io-width = <4>; 6624e50d217SPeter Geis reg-shift = <2>; 6634e50d217SPeter Geis status = "disabled"; 6644e50d217SPeter Geis }; 6654e50d217SPeter Geis 6664e50d217SPeter Geis uart2: serial@fe660000 { 6674e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 6684e50d217SPeter Geis reg = <0x0 0xfe660000 0x0 0x100>; 6694e50d217SPeter Geis interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 6704e50d217SPeter Geis clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 6714e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 6724e50d217SPeter Geis dmas = <&dmac0 4>, <&dmac0 5>; 6734e50d217SPeter Geis pinctrl-0 = <&uart2m0_xfer>; 6744e50d217SPeter Geis pinctrl-names = "default"; 6754e50d217SPeter Geis reg-io-width = <4>; 6764e50d217SPeter Geis reg-shift = <2>; 6774e50d217SPeter Geis status = "disabled"; 6784e50d217SPeter Geis }; 6794e50d217SPeter Geis 6804e50d217SPeter Geis uart3: serial@fe670000 { 6814e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 6824e50d217SPeter Geis reg = <0x0 0xfe670000 0x0 0x100>; 6834e50d217SPeter Geis interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 6844e50d217SPeter Geis clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 6854e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 6864e50d217SPeter Geis dmas = <&dmac0 6>, <&dmac0 7>; 6874e50d217SPeter Geis pinctrl-0 = <&uart3m0_xfer>; 6884e50d217SPeter Geis pinctrl-names = "default"; 6894e50d217SPeter Geis reg-io-width = <4>; 6904e50d217SPeter Geis reg-shift = <2>; 6914e50d217SPeter Geis status = "disabled"; 6924e50d217SPeter Geis }; 6934e50d217SPeter Geis 6944e50d217SPeter Geis uart4: serial@fe680000 { 6954e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 6964e50d217SPeter Geis reg = <0x0 0xfe680000 0x0 0x100>; 6974e50d217SPeter Geis interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 6984e50d217SPeter Geis clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 6994e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7004e50d217SPeter Geis dmas = <&dmac0 8>, <&dmac0 9>; 7014e50d217SPeter Geis pinctrl-0 = <&uart4m0_xfer>; 7024e50d217SPeter Geis pinctrl-names = "default"; 7034e50d217SPeter Geis reg-io-width = <4>; 7044e50d217SPeter Geis reg-shift = <2>; 7054e50d217SPeter Geis status = "disabled"; 7064e50d217SPeter Geis }; 7074e50d217SPeter Geis 7084e50d217SPeter Geis uart5: serial@fe690000 { 7094e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7104e50d217SPeter Geis reg = <0x0 0xfe690000 0x0 0x100>; 7114e50d217SPeter Geis interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 7124e50d217SPeter Geis clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 7134e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7144e50d217SPeter Geis dmas = <&dmac0 10>, <&dmac0 11>; 7154e50d217SPeter Geis pinctrl-0 = <&uart5m0_xfer>; 7164e50d217SPeter Geis pinctrl-names = "default"; 7174e50d217SPeter Geis reg-io-width = <4>; 7184e50d217SPeter Geis reg-shift = <2>; 7194e50d217SPeter Geis status = "disabled"; 7204e50d217SPeter Geis }; 7214e50d217SPeter Geis 7224e50d217SPeter Geis uart6: serial@fe6a0000 { 7234e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7244e50d217SPeter Geis reg = <0x0 0xfe6a0000 0x0 0x100>; 7254e50d217SPeter Geis interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 7264e50d217SPeter Geis clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 7274e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7284e50d217SPeter Geis dmas = <&dmac0 12>, <&dmac0 13>; 7294e50d217SPeter Geis pinctrl-0 = <&uart6m0_xfer>; 7304e50d217SPeter Geis pinctrl-names = "default"; 7314e50d217SPeter Geis reg-io-width = <4>; 7324e50d217SPeter Geis reg-shift = <2>; 7334e50d217SPeter Geis status = "disabled"; 7344e50d217SPeter Geis }; 7354e50d217SPeter Geis 7364e50d217SPeter Geis uart7: serial@fe6b0000 { 7374e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7384e50d217SPeter Geis reg = <0x0 0xfe6b0000 0x0 0x100>; 7394e50d217SPeter Geis interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 7404e50d217SPeter Geis clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 7414e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7424e50d217SPeter Geis dmas = <&dmac0 14>, <&dmac0 15>; 7434e50d217SPeter Geis pinctrl-0 = <&uart7m0_xfer>; 7444e50d217SPeter Geis pinctrl-names = "default"; 7454e50d217SPeter Geis reg-io-width = <4>; 7464e50d217SPeter Geis reg-shift = <2>; 7474e50d217SPeter Geis status = "disabled"; 7484e50d217SPeter Geis }; 7494e50d217SPeter Geis 7504e50d217SPeter Geis uart8: serial@fe6c0000 { 7514e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7524e50d217SPeter Geis reg = <0x0 0xfe6c0000 0x0 0x100>; 7534e50d217SPeter Geis interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 7544e50d217SPeter Geis clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 7554e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7564e50d217SPeter Geis dmas = <&dmac0 16>, <&dmac0 17>; 7574e50d217SPeter Geis pinctrl-0 = <&uart8m0_xfer>; 7584e50d217SPeter Geis pinctrl-names = "default"; 7594e50d217SPeter Geis reg-io-width = <4>; 7604e50d217SPeter Geis reg-shift = <2>; 7614e50d217SPeter Geis status = "disabled"; 7624e50d217SPeter Geis }; 7634e50d217SPeter Geis 7644e50d217SPeter Geis uart9: serial@fe6d0000 { 7654e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7664e50d217SPeter Geis reg = <0x0 0xfe6d0000 0x0 0x100>; 7674e50d217SPeter Geis interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 7684e50d217SPeter Geis clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 7694e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7704e50d217SPeter Geis dmas = <&dmac0 18>, <&dmac0 19>; 7714e50d217SPeter Geis pinctrl-0 = <&uart9m0_xfer>; 7724e50d217SPeter Geis pinctrl-names = "default"; 7734e50d217SPeter Geis reg-io-width = <4>; 7744e50d217SPeter Geis reg-shift = <2>; 7754e50d217SPeter Geis status = "disabled"; 7764e50d217SPeter Geis }; 7774e50d217SPeter Geis 7784e50d217SPeter Geis saradc: saradc@fe720000 { 7794e50d217SPeter Geis compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 7804e50d217SPeter Geis reg = <0x0 0xfe720000 0x0 0x100>; 7814e50d217SPeter Geis interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 7824e50d217SPeter Geis clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 7834e50d217SPeter Geis clock-names = "saradc", "apb_pclk"; 7844e50d217SPeter Geis resets = <&cru SRST_P_SARADC>; 7854e50d217SPeter Geis reset-names = "saradc-apb"; 7864e50d217SPeter Geis #io-channel-cells = <1>; 7874e50d217SPeter Geis status = "disabled"; 7884e50d217SPeter Geis }; 7894e50d217SPeter Geis 7904e50d217SPeter Geis pinctrl: pinctrl { 7914e50d217SPeter Geis compatible = "rockchip,rk3568-pinctrl"; 7924e50d217SPeter Geis rockchip,grf = <&grf>; 7934e50d217SPeter Geis rockchip,pmu = <&pmugrf>; 7944e50d217SPeter Geis #address-cells = <2>; 7954e50d217SPeter Geis #size-cells = <2>; 7964e50d217SPeter Geis ranges; 7974e50d217SPeter Geis 7984e50d217SPeter Geis gpio0: gpio@fdd60000 { 7994e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 8004e50d217SPeter Geis reg = <0x0 0xfdd60000 0x0 0x100>; 8014e50d217SPeter Geis interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 8024e50d217SPeter Geis clocks = <&pmucru PCLK_GPIO0>; 8034e50d217SPeter Geis gpio-controller; 8044e50d217SPeter Geis #gpio-cells = <2>; 8054e50d217SPeter Geis interrupt-controller; 8064e50d217SPeter Geis #interrupt-cells = <2>; 8074e50d217SPeter Geis }; 8084e50d217SPeter Geis 8094e50d217SPeter Geis gpio1: gpio@fe740000 { 8104e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 8114e50d217SPeter Geis reg = <0x0 0xfe740000 0x0 0x100>; 8124e50d217SPeter Geis interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 8134e50d217SPeter Geis clocks = <&cru PCLK_GPIO1>; 8144e50d217SPeter Geis gpio-controller; 8154e50d217SPeter Geis #gpio-cells = <2>; 8164e50d217SPeter Geis interrupt-controller; 8174e50d217SPeter Geis #interrupt-cells = <2>; 8184e50d217SPeter Geis }; 8194e50d217SPeter Geis 8204e50d217SPeter Geis gpio2: gpio@fe750000 { 8214e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 8224e50d217SPeter Geis reg = <0x0 0xfe750000 0x0 0x100>; 8234e50d217SPeter Geis interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 8244e50d217SPeter Geis clocks = <&cru PCLK_GPIO2>; 8254e50d217SPeter Geis gpio-controller; 8264e50d217SPeter Geis #gpio-cells = <2>; 8274e50d217SPeter Geis interrupt-controller; 8284e50d217SPeter Geis #interrupt-cells = <2>; 8294e50d217SPeter Geis }; 8304e50d217SPeter Geis 8314e50d217SPeter Geis gpio3: gpio@fe760000 { 8324e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 8334e50d217SPeter Geis reg = <0x0 0xfe760000 0x0 0x100>; 8344e50d217SPeter Geis interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 8354e50d217SPeter Geis clocks = <&cru PCLK_GPIO3>; 8364e50d217SPeter Geis gpio-controller; 8374e50d217SPeter Geis #gpio-cells = <2>; 8384e50d217SPeter Geis interrupt-controller; 8394e50d217SPeter Geis #interrupt-cells = <2>; 8404e50d217SPeter Geis }; 8414e50d217SPeter Geis 8424e50d217SPeter Geis gpio4: gpio@fe770000 { 8434e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 8444e50d217SPeter Geis reg = <0x0 0xfe770000 0x0 0x100>; 8454e50d217SPeter Geis interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 8464e50d217SPeter Geis clocks = <&cru PCLK_GPIO4>; 8474e50d217SPeter Geis gpio-controller; 8484e50d217SPeter Geis #gpio-cells = <2>; 8494e50d217SPeter Geis interrupt-controller; 8504e50d217SPeter Geis #interrupt-cells = <2>; 8514e50d217SPeter Geis }; 8524e50d217SPeter Geis }; 8534e50d217SPeter Geis}; 8544e50d217SPeter Geis 8554e50d217SPeter Geis#include "rk3568-pinctrl.dtsi" 856