14e50d217SPeter Geis// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 24e50d217SPeter Geis/* 34e50d217SPeter Geis * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 44e50d217SPeter Geis */ 54e50d217SPeter Geis 64e50d217SPeter Geis#include <dt-bindings/clock/rk3568-cru.h> 74e50d217SPeter Geis#include <dt-bindings/interrupt-controller/arm-gic.h> 84e50d217SPeter Geis#include <dt-bindings/interrupt-controller/irq.h> 94e50d217SPeter Geis#include <dt-bindings/phy/phy.h> 104e50d217SPeter Geis#include <dt-bindings/pinctrl/rockchip.h> 114e50d217SPeter Geis#include <dt-bindings/power/rk3568-power.h> 124e50d217SPeter Geis#include <dt-bindings/soc/rockchip,boot-mode.h> 134e50d217SPeter Geis#include <dt-bindings/thermal/thermal.h> 144e50d217SPeter Geis 154e50d217SPeter Geis/ { 164e50d217SPeter Geis interrupt-parent = <&gic>; 174e50d217SPeter Geis #address-cells = <2>; 184e50d217SPeter Geis #size-cells = <2>; 194e50d217SPeter Geis 204e50d217SPeter Geis aliases { 214e50d217SPeter Geis gpio0 = &gpio0; 224e50d217SPeter Geis gpio1 = &gpio1; 234e50d217SPeter Geis gpio2 = &gpio2; 244e50d217SPeter Geis gpio3 = &gpio3; 254e50d217SPeter Geis gpio4 = &gpio4; 264e50d217SPeter Geis i2c0 = &i2c0; 274e50d217SPeter Geis i2c1 = &i2c1; 284e50d217SPeter Geis i2c2 = &i2c2; 294e50d217SPeter Geis i2c3 = &i2c3; 304e50d217SPeter Geis i2c4 = &i2c4; 314e50d217SPeter Geis i2c5 = &i2c5; 324e50d217SPeter Geis serial0 = &uart0; 334e50d217SPeter Geis serial1 = &uart1; 344e50d217SPeter Geis serial2 = &uart2; 354e50d217SPeter Geis serial3 = &uart3; 364e50d217SPeter Geis serial4 = &uart4; 374e50d217SPeter Geis serial5 = &uart5; 384e50d217SPeter Geis serial6 = &uart6; 394e50d217SPeter Geis serial7 = &uart7; 404e50d217SPeter Geis serial8 = &uart8; 414e50d217SPeter Geis serial9 = &uart9; 424e50d217SPeter Geis }; 434e50d217SPeter Geis 444e50d217SPeter Geis cpus { 454e50d217SPeter Geis #address-cells = <2>; 464e50d217SPeter Geis #size-cells = <0>; 474e50d217SPeter Geis 484e50d217SPeter Geis cpu0: cpu@0 { 494e50d217SPeter Geis device_type = "cpu"; 504e50d217SPeter Geis compatible = "arm,cortex-a55"; 514e50d217SPeter Geis reg = <0x0 0x0>; 524e50d217SPeter Geis clocks = <&scmi_clk 0>; 531330875dSPeter Geis #cooling-cells = <2>; 544e50d217SPeter Geis enable-method = "psci"; 554e50d217SPeter Geis operating-points-v2 = <&cpu0_opp_table>; 564e50d217SPeter Geis }; 574e50d217SPeter Geis 584e50d217SPeter Geis cpu1: cpu@100 { 594e50d217SPeter Geis device_type = "cpu"; 604e50d217SPeter Geis compatible = "arm,cortex-a55"; 614e50d217SPeter Geis reg = <0x0 0x100>; 621330875dSPeter Geis #cooling-cells = <2>; 634e50d217SPeter Geis enable-method = "psci"; 644e50d217SPeter Geis operating-points-v2 = <&cpu0_opp_table>; 654e50d217SPeter Geis }; 664e50d217SPeter Geis 674e50d217SPeter Geis cpu2: cpu@200 { 684e50d217SPeter Geis device_type = "cpu"; 694e50d217SPeter Geis compatible = "arm,cortex-a55"; 704e50d217SPeter Geis reg = <0x0 0x200>; 711330875dSPeter Geis #cooling-cells = <2>; 724e50d217SPeter Geis enable-method = "psci"; 734e50d217SPeter Geis operating-points-v2 = <&cpu0_opp_table>; 744e50d217SPeter Geis }; 754e50d217SPeter Geis 764e50d217SPeter Geis cpu3: cpu@300 { 774e50d217SPeter Geis device_type = "cpu"; 784e50d217SPeter Geis compatible = "arm,cortex-a55"; 794e50d217SPeter Geis reg = <0x0 0x300>; 801330875dSPeter Geis #cooling-cells = <2>; 814e50d217SPeter Geis enable-method = "psci"; 824e50d217SPeter Geis operating-points-v2 = <&cpu0_opp_table>; 834e50d217SPeter Geis }; 844e50d217SPeter Geis }; 854e50d217SPeter Geis 86a30f3d90SKrzysztof Kozlowski cpu0_opp_table: opp-table-0 { 874e50d217SPeter Geis compatible = "operating-points-v2"; 884e50d217SPeter Geis opp-shared; 894e50d217SPeter Geis 904e50d217SPeter Geis opp-408000000 { 914e50d217SPeter Geis opp-hz = /bits/ 64 <408000000>; 924e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 934e50d217SPeter Geis clock-latency-ns = <40000>; 944e50d217SPeter Geis }; 954e50d217SPeter Geis 964e50d217SPeter Geis opp-600000000 { 974e50d217SPeter Geis opp-hz = /bits/ 64 <600000000>; 984e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 994e50d217SPeter Geis }; 1004e50d217SPeter Geis 1014e50d217SPeter Geis opp-816000000 { 1024e50d217SPeter Geis opp-hz = /bits/ 64 <816000000>; 1034e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 1044e50d217SPeter Geis opp-suspend; 1054e50d217SPeter Geis }; 1064e50d217SPeter Geis 1074e50d217SPeter Geis opp-1104000000 { 1084e50d217SPeter Geis opp-hz = /bits/ 64 <1104000000>; 1094e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 1104e50d217SPeter Geis }; 1114e50d217SPeter Geis 1124e50d217SPeter Geis opp-1416000000 { 1134e50d217SPeter Geis opp-hz = /bits/ 64 <1416000000>; 1144e50d217SPeter Geis opp-microvolt = <900000 900000 1150000>; 1154e50d217SPeter Geis }; 1164e50d217SPeter Geis 1174e50d217SPeter Geis opp-1608000000 { 1184e50d217SPeter Geis opp-hz = /bits/ 64 <1608000000>; 1194e50d217SPeter Geis opp-microvolt = <975000 975000 1150000>; 1204e50d217SPeter Geis }; 1214e50d217SPeter Geis 1224e50d217SPeter Geis opp-1800000000 { 1234e50d217SPeter Geis opp-hz = /bits/ 64 <1800000000>; 1244e50d217SPeter Geis opp-microvolt = <1050000 1050000 1150000>; 1254e50d217SPeter Geis }; 1264e50d217SPeter Geis }; 1274e50d217SPeter Geis 1284e50d217SPeter Geis firmware { 1294e50d217SPeter Geis scmi: scmi { 1304e50d217SPeter Geis compatible = "arm,scmi-smc"; 1314e50d217SPeter Geis arm,smc-id = <0x82000010>; 1324e50d217SPeter Geis shmem = <&scmi_shmem>; 1334e50d217SPeter Geis #address-cells = <1>; 1344e50d217SPeter Geis #size-cells = <0>; 1354e50d217SPeter Geis 1364e50d217SPeter Geis scmi_clk: protocol@14 { 1374e50d217SPeter Geis reg = <0x14>; 1384e50d217SPeter Geis #clock-cells = <1>; 1394e50d217SPeter Geis }; 1404e50d217SPeter Geis }; 1414e50d217SPeter Geis }; 1424e50d217SPeter Geis 1434e50d217SPeter Geis pmu { 1444e50d217SPeter Geis compatible = "arm,cortex-a55-pmu"; 1454e50d217SPeter Geis interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 1464e50d217SPeter Geis <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1474e50d217SPeter Geis <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 1484e50d217SPeter Geis <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1494e50d217SPeter Geis interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1504e50d217SPeter Geis }; 1514e50d217SPeter Geis 1524e50d217SPeter Geis psci { 1534e50d217SPeter Geis compatible = "arm,psci-1.0"; 1544e50d217SPeter Geis method = "smc"; 1554e50d217SPeter Geis }; 1564e50d217SPeter Geis 1574e50d217SPeter Geis timer { 1584e50d217SPeter Geis compatible = "arm,armv8-timer"; 1594e50d217SPeter Geis interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 1604e50d217SPeter Geis <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 1614e50d217SPeter Geis <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 1624e50d217SPeter Geis <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 1634e50d217SPeter Geis arm,no-tick-in-suspend; 1644e50d217SPeter Geis }; 1654e50d217SPeter Geis 1664e50d217SPeter Geis xin24m: xin24m { 1674e50d217SPeter Geis compatible = "fixed-clock"; 1684e50d217SPeter Geis clock-frequency = <24000000>; 1694e50d217SPeter Geis clock-output-names = "xin24m"; 1704e50d217SPeter Geis #clock-cells = <0>; 1714e50d217SPeter Geis }; 1724e50d217SPeter Geis 1734e50d217SPeter Geis xin32k: xin32k { 1744e50d217SPeter Geis compatible = "fixed-clock"; 1754e50d217SPeter Geis clock-frequency = <32768>; 1764e50d217SPeter Geis clock-output-names = "xin32k"; 1774e50d217SPeter Geis pinctrl-0 = <&clk32k_out0>; 1784e50d217SPeter Geis pinctrl-names = "default"; 1794e50d217SPeter Geis #clock-cells = <0>; 1804e50d217SPeter Geis }; 1814e50d217SPeter Geis 1824e50d217SPeter Geis sram@10f000 { 1834e50d217SPeter Geis compatible = "mmio-sram"; 1844e50d217SPeter Geis reg = <0x0 0x0010f000 0x0 0x100>; 1854e50d217SPeter Geis #address-cells = <1>; 1864e50d217SPeter Geis #size-cells = <1>; 1874e50d217SPeter Geis ranges = <0 0x0 0x0010f000 0x100>; 1884e50d217SPeter Geis 1894e50d217SPeter Geis scmi_shmem: sram@0 { 1904e50d217SPeter Geis compatible = "arm,scmi-shmem"; 1914e50d217SPeter Geis reg = <0x0 0x100>; 1924e50d217SPeter Geis }; 1934e50d217SPeter Geis }; 1944e50d217SPeter Geis 1954e50d217SPeter Geis gic: interrupt-controller@fd400000 { 1964e50d217SPeter Geis compatible = "arm,gic-v3"; 1974e50d217SPeter Geis reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 1984e50d217SPeter Geis <0x0 0xfd460000 0 0x80000>; /* GICR */ 1994e50d217SPeter Geis interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2004e50d217SPeter Geis interrupt-controller; 2014e50d217SPeter Geis #interrupt-cells = <3>; 202b6c1a590SPeter Geis mbi-alias = <0x0 0xfd410000>; 2034e50d217SPeter Geis mbi-ranges = <296 24>; 2044e50d217SPeter Geis msi-controller; 2054e50d217SPeter Geis }; 2064e50d217SPeter Geis 2074e50d217SPeter Geis pmugrf: syscon@fdc20000 { 2084e50d217SPeter Geis compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 2094e50d217SPeter Geis reg = <0x0 0xfdc20000 0x0 0x10000>; 2102dbcb251SMichael Riesch 2112dbcb251SMichael Riesch pmu_io_domains: io-domains { 2122dbcb251SMichael Riesch compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 2132dbcb251SMichael Riesch status = "disabled"; 2142dbcb251SMichael Riesch }; 2154e50d217SPeter Geis }; 2164e50d217SPeter Geis 2174e50d217SPeter Geis grf: syscon@fdc60000 { 2184e50d217SPeter Geis compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 2194e50d217SPeter Geis reg = <0x0 0xfdc60000 0x0 0x10000>; 2204e50d217SPeter Geis }; 2214e50d217SPeter Geis 2224e50d217SPeter Geis pmucru: clock-controller@fdd00000 { 2234e50d217SPeter Geis compatible = "rockchip,rk3568-pmucru"; 2244e50d217SPeter Geis reg = <0x0 0xfdd00000 0x0 0x1000>; 2254e50d217SPeter Geis #clock-cells = <1>; 2264e50d217SPeter Geis #reset-cells = <1>; 2274e50d217SPeter Geis }; 2284e50d217SPeter Geis 2294e50d217SPeter Geis cru: clock-controller@fdd20000 { 2304e50d217SPeter Geis compatible = "rockchip,rk3568-cru"; 2314e50d217SPeter Geis reg = <0x0 0xfdd20000 0x0 0x1000>; 2324e50d217SPeter Geis #clock-cells = <1>; 2334e50d217SPeter Geis #reset-cells = <1>; 234f7c5b9c2SPeter Geis assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 235f7c5b9c2SPeter Geis assigned-clock-rates = <1200000000>, <200000000>; 23695ad4dbeSMichael Riesch rockchip,grf = <&grf>; 2374e50d217SPeter Geis }; 2384e50d217SPeter Geis 2394e50d217SPeter Geis i2c0: i2c@fdd40000 { 2404e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 2414e50d217SPeter Geis reg = <0x0 0xfdd40000 0x0 0x1000>; 2424e50d217SPeter Geis interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 2434e50d217SPeter Geis clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 2444e50d217SPeter Geis clock-names = "i2c", "pclk"; 2454e50d217SPeter Geis pinctrl-0 = <&i2c0_xfer>; 2464e50d217SPeter Geis pinctrl-names = "default"; 2474e50d217SPeter Geis #address-cells = <1>; 2484e50d217SPeter Geis #size-cells = <0>; 2494e50d217SPeter Geis status = "disabled"; 2504e50d217SPeter Geis }; 2514e50d217SPeter Geis 2524e50d217SPeter Geis uart0: serial@fdd50000 { 2534e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 2544e50d217SPeter Geis reg = <0x0 0xfdd50000 0x0 0x100>; 2554e50d217SPeter Geis interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2564e50d217SPeter Geis clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 2574e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 2584e50d217SPeter Geis dmas = <&dmac0 0>, <&dmac0 1>; 2594e50d217SPeter Geis pinctrl-0 = <&uart0_xfer>; 2604e50d217SPeter Geis pinctrl-names = "default"; 2614e50d217SPeter Geis reg-io-width = <4>; 2624e50d217SPeter Geis reg-shift = <2>; 2634e50d217SPeter Geis status = "disabled"; 2644e50d217SPeter Geis }; 2654e50d217SPeter Geis 26698419a39SLiang Chen pwm0: pwm@fdd70000 { 26798419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 26898419a39SLiang Chen reg = <0x0 0xfdd70000 0x0 0x10>; 26998419a39SLiang Chen clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 27098419a39SLiang Chen clock-names = "pwm", "pclk"; 27198419a39SLiang Chen pinctrl-0 = <&pwm0m0_pins>; 27298419a39SLiang Chen pinctrl-names = "active"; 27398419a39SLiang Chen #pwm-cells = <3>; 27498419a39SLiang Chen status = "disabled"; 27598419a39SLiang Chen }; 27698419a39SLiang Chen 27798419a39SLiang Chen pwm1: pwm@fdd70010 { 27898419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 27998419a39SLiang Chen reg = <0x0 0xfdd70010 0x0 0x10>; 28098419a39SLiang Chen clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 28198419a39SLiang Chen clock-names = "pwm", "pclk"; 28298419a39SLiang Chen pinctrl-0 = <&pwm1m0_pins>; 28398419a39SLiang Chen pinctrl-names = "active"; 28498419a39SLiang Chen #pwm-cells = <3>; 28598419a39SLiang Chen status = "disabled"; 28698419a39SLiang Chen }; 28798419a39SLiang Chen 28898419a39SLiang Chen pwm2: pwm@fdd70020 { 28998419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 29098419a39SLiang Chen reg = <0x0 0xfdd70020 0x0 0x10>; 29198419a39SLiang Chen clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 29298419a39SLiang Chen clock-names = "pwm", "pclk"; 29398419a39SLiang Chen pinctrl-0 = <&pwm2m0_pins>; 29498419a39SLiang Chen pinctrl-names = "active"; 29598419a39SLiang Chen #pwm-cells = <3>; 29698419a39SLiang Chen status = "disabled"; 29798419a39SLiang Chen }; 29898419a39SLiang Chen 29998419a39SLiang Chen pwm3: pwm@fdd70030 { 30098419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 30198419a39SLiang Chen reg = <0x0 0xfdd70030 0x0 0x10>; 30298419a39SLiang Chen clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 30398419a39SLiang Chen clock-names = "pwm", "pclk"; 30498419a39SLiang Chen pinctrl-0 = <&pwm3_pins>; 30598419a39SLiang Chen pinctrl-names = "active"; 30698419a39SLiang Chen #pwm-cells = <3>; 30798419a39SLiang Chen status = "disabled"; 30898419a39SLiang Chen }; 30998419a39SLiang Chen 3104e50d217SPeter Geis pmu: power-management@fdd90000 { 3114e50d217SPeter Geis compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 3124e50d217SPeter Geis reg = <0x0 0xfdd90000 0x0 0x1000>; 3134e50d217SPeter Geis 3144e50d217SPeter Geis power: power-controller { 3154e50d217SPeter Geis compatible = "rockchip,rk3568-power-controller"; 3164e50d217SPeter Geis #power-domain-cells = <1>; 3174e50d217SPeter Geis #address-cells = <1>; 3184e50d217SPeter Geis #size-cells = <0>; 3194e50d217SPeter Geis 3204e50d217SPeter Geis /* These power domains are grouped by VD_GPU */ 3214e50d217SPeter Geis power-domain@RK3568_PD_GPU { 3224e50d217SPeter Geis reg = <RK3568_PD_GPU>; 3234e50d217SPeter Geis clocks = <&cru ACLK_GPU_PRE>, 3244e50d217SPeter Geis <&cru PCLK_GPU_PRE>; 3254e50d217SPeter Geis pm_qos = <&qos_gpu>; 3264e50d217SPeter Geis #power-domain-cells = <0>; 3274e50d217SPeter Geis }; 3284e50d217SPeter Geis 3294e50d217SPeter Geis /* These power domains are grouped by VD_LOGIC */ 3304e50d217SPeter Geis power-domain@RK3568_PD_VI { 3314e50d217SPeter Geis reg = <RK3568_PD_VI>; 3324e50d217SPeter Geis clocks = <&cru HCLK_VI>, 3334e50d217SPeter Geis <&cru PCLK_VI>; 3344e50d217SPeter Geis pm_qos = <&qos_isp>, 3354e50d217SPeter Geis <&qos_vicap0>, 3364e50d217SPeter Geis <&qos_vicap1>; 3374e50d217SPeter Geis #power-domain-cells = <0>; 3384e50d217SPeter Geis }; 3394e50d217SPeter Geis 3404e50d217SPeter Geis power-domain@RK3568_PD_VO { 3414e50d217SPeter Geis reg = <RK3568_PD_VO>; 3424e50d217SPeter Geis clocks = <&cru HCLK_VO>, 3434e50d217SPeter Geis <&cru PCLK_VO>, 3444e50d217SPeter Geis <&cru ACLK_VOP_PRE>; 3454e50d217SPeter Geis pm_qos = <&qos_hdcp>, 3464e50d217SPeter Geis <&qos_vop_m0>, 3474e50d217SPeter Geis <&qos_vop_m1>; 3484e50d217SPeter Geis #power-domain-cells = <0>; 3494e50d217SPeter Geis }; 3504e50d217SPeter Geis 3514e50d217SPeter Geis power-domain@RK3568_PD_RGA { 3524e50d217SPeter Geis reg = <RK3568_PD_RGA>; 3534e50d217SPeter Geis clocks = <&cru HCLK_RGA_PRE>, 3544e50d217SPeter Geis <&cru PCLK_RGA_PRE>; 3554e50d217SPeter Geis pm_qos = <&qos_ebc>, 3564e50d217SPeter Geis <&qos_iep>, 3574e50d217SPeter Geis <&qos_jpeg_dec>, 3584e50d217SPeter Geis <&qos_jpeg_enc>, 3594e50d217SPeter Geis <&qos_rga_rd>, 3604e50d217SPeter Geis <&qos_rga_wr>; 3614e50d217SPeter Geis #power-domain-cells = <0>; 3624e50d217SPeter Geis }; 3634e50d217SPeter Geis 3644e50d217SPeter Geis power-domain@RK3568_PD_VPU { 3654e50d217SPeter Geis reg = <RK3568_PD_VPU>; 3664e50d217SPeter Geis clocks = <&cru HCLK_VPU_PRE>; 3674e50d217SPeter Geis pm_qos = <&qos_vpu>; 3684e50d217SPeter Geis #power-domain-cells = <0>; 3694e50d217SPeter Geis }; 3704e50d217SPeter Geis 3714e50d217SPeter Geis power-domain@RK3568_PD_RKVDEC { 3724e50d217SPeter Geis clocks = <&cru HCLK_RKVDEC_PRE>; 3734e50d217SPeter Geis reg = <RK3568_PD_RKVDEC>; 3744e50d217SPeter Geis pm_qos = <&qos_rkvdec>; 3754e50d217SPeter Geis #power-domain-cells = <0>; 3764e50d217SPeter Geis }; 3774e50d217SPeter Geis 3784e50d217SPeter Geis power-domain@RK3568_PD_RKVENC { 3794e50d217SPeter Geis reg = <RK3568_PD_RKVENC>; 3804e50d217SPeter Geis clocks = <&cru HCLK_RKVENC_PRE>; 3814e50d217SPeter Geis pm_qos = <&qos_rkvenc_rd_m0>, 3824e50d217SPeter Geis <&qos_rkvenc_rd_m1>, 3834e50d217SPeter Geis <&qos_rkvenc_wr_m0>; 3844e50d217SPeter Geis #power-domain-cells = <0>; 3854e50d217SPeter Geis }; 3864e50d217SPeter Geis }; 3874e50d217SPeter Geis }; 3884e50d217SPeter Geis 3894e50d217SPeter Geis sdmmc2: mmc@fe000000 { 3904e50d217SPeter Geis compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 3914e50d217SPeter Geis reg = <0x0 0xfe000000 0x0 0x4000>; 3924e50d217SPeter Geis interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3934e50d217SPeter Geis clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 3944e50d217SPeter Geis <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 3954e50d217SPeter Geis clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 3964e50d217SPeter Geis fifo-depth = <0x100>; 3974e50d217SPeter Geis max-frequency = <150000000>; 3984e50d217SPeter Geis resets = <&cru SRST_SDMMC2>; 3994e50d217SPeter Geis reset-names = "reset"; 4004e50d217SPeter Geis status = "disabled"; 4014e50d217SPeter Geis }; 4024e50d217SPeter Geis 4030dcec571SPeter Geis gmac1: ethernet@fe010000 { 4040dcec571SPeter Geis compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 4050dcec571SPeter Geis reg = <0x0 0xfe010000 0x0 0x10000>; 4060dcec571SPeter Geis interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 4070dcec571SPeter Geis <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 4080dcec571SPeter Geis interrupt-names = "macirq", "eth_wake_irq"; 4090dcec571SPeter Geis clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 4100dcec571SPeter Geis <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 4110dcec571SPeter Geis <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 4120dcec571SPeter Geis <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 4130dcec571SPeter Geis clock-names = "stmmaceth", "mac_clk_rx", 4140dcec571SPeter Geis "mac_clk_tx", "clk_mac_refout", 4150dcec571SPeter Geis "aclk_mac", "pclk_mac", 4160dcec571SPeter Geis "clk_mac_speed", "ptp_ref"; 4170dcec571SPeter Geis resets = <&cru SRST_A_GMAC1>; 4180dcec571SPeter Geis reset-names = "stmmaceth"; 4190dcec571SPeter Geis rockchip,grf = <&grf>; 4200dcec571SPeter Geis snps,axi-config = <&gmac1_stmmac_axi_setup>; 4210dcec571SPeter Geis snps,mixed-burst; 4220dcec571SPeter Geis snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 4230dcec571SPeter Geis snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 4240dcec571SPeter Geis snps,tso; 4250dcec571SPeter Geis status = "disabled"; 4260dcec571SPeter Geis 4270dcec571SPeter Geis mdio1: mdio { 4280dcec571SPeter Geis compatible = "snps,dwmac-mdio"; 4290dcec571SPeter Geis #address-cells = <0x1>; 4300dcec571SPeter Geis #size-cells = <0x0>; 4310dcec571SPeter Geis }; 4320dcec571SPeter Geis 4330dcec571SPeter Geis gmac1_stmmac_axi_setup: stmmac-axi-config { 4340dcec571SPeter Geis snps,blen = <0 0 0 0 16 8 4>; 4350dcec571SPeter Geis snps,rd_osr_lmt = <8>; 4360dcec571SPeter Geis snps,wr_osr_lmt = <4>; 4370dcec571SPeter Geis }; 4380dcec571SPeter Geis 4390dcec571SPeter Geis gmac1_mtl_rx_setup: rx-queues-config { 4400dcec571SPeter Geis snps,rx-queues-to-use = <1>; 4410dcec571SPeter Geis queue0 {}; 4420dcec571SPeter Geis }; 4430dcec571SPeter Geis 4440dcec571SPeter Geis gmac1_mtl_tx_setup: tx-queues-config { 4450dcec571SPeter Geis snps,tx-queues-to-use = <1>; 4460dcec571SPeter Geis queue0 {}; 4470dcec571SPeter Geis }; 4480dcec571SPeter Geis }; 4490dcec571SPeter Geis 4504e50d217SPeter Geis qos_gpu: qos@fe128000 { 4514e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4524e50d217SPeter Geis reg = <0x0 0xfe128000 0x0 0x20>; 4534e50d217SPeter Geis }; 4544e50d217SPeter Geis 4554e50d217SPeter Geis qos_rkvenc_rd_m0: qos@fe138080 { 4564e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4574e50d217SPeter Geis reg = <0x0 0xfe138080 0x0 0x20>; 4584e50d217SPeter Geis }; 4594e50d217SPeter Geis 4604e50d217SPeter Geis qos_rkvenc_rd_m1: qos@fe138100 { 4614e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4624e50d217SPeter Geis reg = <0x0 0xfe138100 0x0 0x20>; 4634e50d217SPeter Geis }; 4644e50d217SPeter Geis 4654e50d217SPeter Geis qos_rkvenc_wr_m0: qos@fe138180 { 4664e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4674e50d217SPeter Geis reg = <0x0 0xfe138180 0x0 0x20>; 4684e50d217SPeter Geis }; 4694e50d217SPeter Geis 4704e50d217SPeter Geis qos_isp: qos@fe148000 { 4714e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4724e50d217SPeter Geis reg = <0x0 0xfe148000 0x0 0x20>; 4734e50d217SPeter Geis }; 4744e50d217SPeter Geis 4754e50d217SPeter Geis qos_vicap0: qos@fe148080 { 4764e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4774e50d217SPeter Geis reg = <0x0 0xfe148080 0x0 0x20>; 4784e50d217SPeter Geis }; 4794e50d217SPeter Geis 4804e50d217SPeter Geis qos_vicap1: qos@fe148100 { 4814e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4824e50d217SPeter Geis reg = <0x0 0xfe148100 0x0 0x20>; 4834e50d217SPeter Geis }; 4844e50d217SPeter Geis 4854e50d217SPeter Geis qos_vpu: qos@fe150000 { 4864e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4874e50d217SPeter Geis reg = <0x0 0xfe150000 0x0 0x20>; 4884e50d217SPeter Geis }; 4894e50d217SPeter Geis 4904e50d217SPeter Geis qos_ebc: qos@fe158000 { 4914e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4924e50d217SPeter Geis reg = <0x0 0xfe158000 0x0 0x20>; 4934e50d217SPeter Geis }; 4944e50d217SPeter Geis 4954e50d217SPeter Geis qos_iep: qos@fe158100 { 4964e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 4974e50d217SPeter Geis reg = <0x0 0xfe158100 0x0 0x20>; 4984e50d217SPeter Geis }; 4994e50d217SPeter Geis 5004e50d217SPeter Geis qos_jpeg_dec: qos@fe158180 { 5014e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5024e50d217SPeter Geis reg = <0x0 0xfe158180 0x0 0x20>; 5034e50d217SPeter Geis }; 5044e50d217SPeter Geis 5054e50d217SPeter Geis qos_jpeg_enc: qos@fe158200 { 5064e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5074e50d217SPeter Geis reg = <0x0 0xfe158200 0x0 0x20>; 5084e50d217SPeter Geis }; 5094e50d217SPeter Geis 5104e50d217SPeter Geis qos_rga_rd: qos@fe158280 { 5114e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5124e50d217SPeter Geis reg = <0x0 0xfe158280 0x0 0x20>; 5134e50d217SPeter Geis }; 5144e50d217SPeter Geis 5154e50d217SPeter Geis qos_rga_wr: qos@fe158300 { 5164e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5174e50d217SPeter Geis reg = <0x0 0xfe158300 0x0 0x20>; 5184e50d217SPeter Geis }; 5194e50d217SPeter Geis 5204e50d217SPeter Geis qos_npu: qos@fe180000 { 5214e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5224e50d217SPeter Geis reg = <0x0 0xfe180000 0x0 0x20>; 5234e50d217SPeter Geis }; 5244e50d217SPeter Geis 5254e50d217SPeter Geis qos_pcie2x1: qos@fe190000 { 5264e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5274e50d217SPeter Geis reg = <0x0 0xfe190000 0x0 0x20>; 5284e50d217SPeter Geis }; 5294e50d217SPeter Geis 5304e50d217SPeter Geis qos_sata1: qos@fe190280 { 5314e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5324e50d217SPeter Geis reg = <0x0 0xfe190280 0x0 0x20>; 5334e50d217SPeter Geis }; 5344e50d217SPeter Geis 5354e50d217SPeter Geis qos_sata2: qos@fe190300 { 5364e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5374e50d217SPeter Geis reg = <0x0 0xfe190300 0x0 0x20>; 5384e50d217SPeter Geis }; 5394e50d217SPeter Geis 5404e50d217SPeter Geis qos_usb3_0: qos@fe190380 { 5414e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5424e50d217SPeter Geis reg = <0x0 0xfe190380 0x0 0x20>; 5434e50d217SPeter Geis }; 5444e50d217SPeter Geis 5454e50d217SPeter Geis qos_usb3_1: qos@fe190400 { 5464e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5474e50d217SPeter Geis reg = <0x0 0xfe190400 0x0 0x20>; 5484e50d217SPeter Geis }; 5494e50d217SPeter Geis 5504e50d217SPeter Geis qos_rkvdec: qos@fe198000 { 5514e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5524e50d217SPeter Geis reg = <0x0 0xfe198000 0x0 0x20>; 5534e50d217SPeter Geis }; 5544e50d217SPeter Geis 5554e50d217SPeter Geis qos_hdcp: qos@fe1a8000 { 5564e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5574e50d217SPeter Geis reg = <0x0 0xfe1a8000 0x0 0x20>; 5584e50d217SPeter Geis }; 5594e50d217SPeter Geis 5604e50d217SPeter Geis qos_vop_m0: qos@fe1a8080 { 5614e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5624e50d217SPeter Geis reg = <0x0 0xfe1a8080 0x0 0x20>; 5634e50d217SPeter Geis }; 5644e50d217SPeter Geis 5654e50d217SPeter Geis qos_vop_m1: qos@fe1a8100 { 5664e50d217SPeter Geis compatible = "rockchip,rk3568-qos", "syscon"; 5674e50d217SPeter Geis reg = <0x0 0xfe1a8100 0x0 0x20>; 5684e50d217SPeter Geis }; 5694e50d217SPeter Geis 5704e50d217SPeter Geis sdmmc0: mmc@fe2b0000 { 5714e50d217SPeter Geis compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 5724e50d217SPeter Geis reg = <0x0 0xfe2b0000 0x0 0x4000>; 5734e50d217SPeter Geis interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 5744e50d217SPeter Geis clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 5754e50d217SPeter Geis <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 5764e50d217SPeter Geis clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 5774e50d217SPeter Geis fifo-depth = <0x100>; 5784e50d217SPeter Geis max-frequency = <150000000>; 5794e50d217SPeter Geis resets = <&cru SRST_SDMMC0>; 5804e50d217SPeter Geis reset-names = "reset"; 5814e50d217SPeter Geis status = "disabled"; 5824e50d217SPeter Geis }; 5834e50d217SPeter Geis 5844e50d217SPeter Geis sdmmc1: mmc@fe2c0000 { 5854e50d217SPeter Geis compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 5864e50d217SPeter Geis reg = <0x0 0xfe2c0000 0x0 0x4000>; 5874e50d217SPeter Geis interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 5884e50d217SPeter Geis clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 5894e50d217SPeter Geis <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 5904e50d217SPeter Geis clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 5914e50d217SPeter Geis fifo-depth = <0x100>; 5924e50d217SPeter Geis max-frequency = <150000000>; 5934e50d217SPeter Geis resets = <&cru SRST_SDMMC1>; 5944e50d217SPeter Geis reset-names = "reset"; 5954e50d217SPeter Geis status = "disabled"; 5964e50d217SPeter Geis }; 5974e50d217SPeter Geis 5984e50d217SPeter Geis sdhci: mmc@fe310000 { 5994e50d217SPeter Geis compatible = "rockchip,rk3568-dwcmshc"; 6004e50d217SPeter Geis reg = <0x0 0xfe310000 0x0 0x10000>; 6014e50d217SPeter Geis interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6024e50d217SPeter Geis assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 6034e50d217SPeter Geis assigned-clock-rates = <200000000>, <24000000>; 6044e50d217SPeter Geis clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 6054e50d217SPeter Geis <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 6064e50d217SPeter Geis <&cru TCLK_EMMC>; 6074e50d217SPeter Geis clock-names = "core", "bus", "axi", "block", "timer"; 6084e50d217SPeter Geis status = "disabled"; 6094e50d217SPeter Geis }; 6104e50d217SPeter Geis 611*a65e6523SPeter Geis spdif: spdif@fe460000 { 612*a65e6523SPeter Geis compatible = "rockchip,rk3568-spdif"; 613*a65e6523SPeter Geis reg = <0x0 0xfe460000 0x0 0x1000>; 614*a65e6523SPeter Geis interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 615*a65e6523SPeter Geis clock-names = "mclk", "hclk"; 616*a65e6523SPeter Geis clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 617*a65e6523SPeter Geis dmas = <&dmac1 1>; 618*a65e6523SPeter Geis dma-names = "tx"; 619*a65e6523SPeter Geis pinctrl-names = "default"; 620*a65e6523SPeter Geis pinctrl-0 = <&spdifm0_tx>; 621*a65e6523SPeter Geis #sound-dai-cells = <0>; 622*a65e6523SPeter Geis status = "disabled"; 623*a65e6523SPeter Geis }; 624*a65e6523SPeter Geis 6254e50d217SPeter Geis dmac0: dmac@fe530000 { 6264e50d217SPeter Geis compatible = "arm,pl330", "arm,primecell"; 6274e50d217SPeter Geis reg = <0x0 0xfe530000 0x0 0x4000>; 6284e50d217SPeter Geis interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 6294e50d217SPeter Geis <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6304e50d217SPeter Geis arm,pl330-periph-burst; 6314e50d217SPeter Geis clocks = <&cru ACLK_BUS>; 6324e50d217SPeter Geis clock-names = "apb_pclk"; 6334e50d217SPeter Geis #dma-cells = <1>; 6344e50d217SPeter Geis }; 6354e50d217SPeter Geis 6364e50d217SPeter Geis dmac1: dmac@fe550000 { 6374e50d217SPeter Geis compatible = "arm,pl330", "arm,primecell"; 6384e50d217SPeter Geis reg = <0x0 0xfe550000 0x0 0x4000>; 6394e50d217SPeter Geis interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 6404e50d217SPeter Geis <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 6414e50d217SPeter Geis arm,pl330-periph-burst; 6424e50d217SPeter Geis clocks = <&cru ACLK_BUS>; 6434e50d217SPeter Geis clock-names = "apb_pclk"; 6444e50d217SPeter Geis #dma-cells = <1>; 6454e50d217SPeter Geis }; 6464e50d217SPeter Geis 6474e50d217SPeter Geis i2c1: i2c@fe5a0000 { 6484e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 6494e50d217SPeter Geis reg = <0x0 0xfe5a0000 0x0 0x1000>; 6504e50d217SPeter Geis interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 6514e50d217SPeter Geis clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 6524e50d217SPeter Geis clock-names = "i2c", "pclk"; 6534e50d217SPeter Geis pinctrl-0 = <&i2c1_xfer>; 6544e50d217SPeter Geis pinctrl-names = "default"; 6554e50d217SPeter Geis #address-cells = <1>; 6564e50d217SPeter Geis #size-cells = <0>; 6574e50d217SPeter Geis status = "disabled"; 6584e50d217SPeter Geis }; 6594e50d217SPeter Geis 6604e50d217SPeter Geis i2c2: i2c@fe5b0000 { 6614e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 6624e50d217SPeter Geis reg = <0x0 0xfe5b0000 0x0 0x1000>; 6634e50d217SPeter Geis interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 6644e50d217SPeter Geis clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 6654e50d217SPeter Geis clock-names = "i2c", "pclk"; 6664e50d217SPeter Geis pinctrl-0 = <&i2c2m0_xfer>; 6674e50d217SPeter Geis pinctrl-names = "default"; 6684e50d217SPeter Geis #address-cells = <1>; 6694e50d217SPeter Geis #size-cells = <0>; 6704e50d217SPeter Geis status = "disabled"; 6714e50d217SPeter Geis }; 6724e50d217SPeter Geis 6734e50d217SPeter Geis i2c3: i2c@fe5c0000 { 6744e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 6754e50d217SPeter Geis reg = <0x0 0xfe5c0000 0x0 0x1000>; 6764e50d217SPeter Geis interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 6774e50d217SPeter Geis clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 6784e50d217SPeter Geis clock-names = "i2c", "pclk"; 6794e50d217SPeter Geis pinctrl-0 = <&i2c3m0_xfer>; 6804e50d217SPeter Geis pinctrl-names = "default"; 6814e50d217SPeter Geis #address-cells = <1>; 6824e50d217SPeter Geis #size-cells = <0>; 6834e50d217SPeter Geis status = "disabled"; 6844e50d217SPeter Geis }; 6854e50d217SPeter Geis 6864e50d217SPeter Geis i2c4: i2c@fe5d0000 { 6874e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 6884e50d217SPeter Geis reg = <0x0 0xfe5d0000 0x0 0x1000>; 6894e50d217SPeter Geis interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 6904e50d217SPeter Geis clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 6914e50d217SPeter Geis clock-names = "i2c", "pclk"; 6924e50d217SPeter Geis pinctrl-0 = <&i2c4m0_xfer>; 6934e50d217SPeter Geis pinctrl-names = "default"; 6944e50d217SPeter Geis #address-cells = <1>; 6954e50d217SPeter Geis #size-cells = <0>; 6964e50d217SPeter Geis status = "disabled"; 6974e50d217SPeter Geis }; 6984e50d217SPeter Geis 6994e50d217SPeter Geis i2c5: i2c@fe5e0000 { 7004e50d217SPeter Geis compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 7014e50d217SPeter Geis reg = <0x0 0xfe5e0000 0x0 0x1000>; 7024e50d217SPeter Geis interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 7034e50d217SPeter Geis clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 7044e50d217SPeter Geis clock-names = "i2c", "pclk"; 7054e50d217SPeter Geis pinctrl-0 = <&i2c5m0_xfer>; 7064e50d217SPeter Geis pinctrl-names = "default"; 7074e50d217SPeter Geis #address-cells = <1>; 7084e50d217SPeter Geis #size-cells = <0>; 7094e50d217SPeter Geis status = "disabled"; 7104e50d217SPeter Geis }; 7114e50d217SPeter Geis 7120edcfec3SLiang Chen wdt: watchdog@fe600000 { 7130edcfec3SLiang Chen compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 7140edcfec3SLiang Chen reg = <0x0 0xfe600000 0x0 0x100>; 7150edcfec3SLiang Chen interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 7160edcfec3SLiang Chen clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 7170edcfec3SLiang Chen clock-names = "tclk", "pclk"; 7180edcfec3SLiang Chen }; 7190edcfec3SLiang Chen 7204e50d217SPeter Geis uart1: serial@fe650000 { 7214e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7224e50d217SPeter Geis reg = <0x0 0xfe650000 0x0 0x100>; 7234e50d217SPeter Geis interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 7244e50d217SPeter Geis clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 7254e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7264e50d217SPeter Geis dmas = <&dmac0 2>, <&dmac0 3>; 7274e50d217SPeter Geis pinctrl-0 = <&uart1m0_xfer>; 7284e50d217SPeter Geis pinctrl-names = "default"; 7294e50d217SPeter Geis reg-io-width = <4>; 7304e50d217SPeter Geis reg-shift = <2>; 7314e50d217SPeter Geis status = "disabled"; 7324e50d217SPeter Geis }; 7334e50d217SPeter Geis 7344e50d217SPeter Geis uart2: serial@fe660000 { 7354e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7364e50d217SPeter Geis reg = <0x0 0xfe660000 0x0 0x100>; 7374e50d217SPeter Geis interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 7384e50d217SPeter Geis clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 7394e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7404e50d217SPeter Geis dmas = <&dmac0 4>, <&dmac0 5>; 7414e50d217SPeter Geis pinctrl-0 = <&uart2m0_xfer>; 7424e50d217SPeter Geis pinctrl-names = "default"; 7434e50d217SPeter Geis reg-io-width = <4>; 7444e50d217SPeter Geis reg-shift = <2>; 7454e50d217SPeter Geis status = "disabled"; 7464e50d217SPeter Geis }; 7474e50d217SPeter Geis 7484e50d217SPeter Geis uart3: serial@fe670000 { 7494e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7504e50d217SPeter Geis reg = <0x0 0xfe670000 0x0 0x100>; 7514e50d217SPeter Geis interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 7524e50d217SPeter Geis clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 7534e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7544e50d217SPeter Geis dmas = <&dmac0 6>, <&dmac0 7>; 7554e50d217SPeter Geis pinctrl-0 = <&uart3m0_xfer>; 7564e50d217SPeter Geis pinctrl-names = "default"; 7574e50d217SPeter Geis reg-io-width = <4>; 7584e50d217SPeter Geis reg-shift = <2>; 7594e50d217SPeter Geis status = "disabled"; 7604e50d217SPeter Geis }; 7614e50d217SPeter Geis 7624e50d217SPeter Geis uart4: serial@fe680000 { 7634e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7644e50d217SPeter Geis reg = <0x0 0xfe680000 0x0 0x100>; 7654e50d217SPeter Geis interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 7664e50d217SPeter Geis clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 7674e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7684e50d217SPeter Geis dmas = <&dmac0 8>, <&dmac0 9>; 7694e50d217SPeter Geis pinctrl-0 = <&uart4m0_xfer>; 7704e50d217SPeter Geis pinctrl-names = "default"; 7714e50d217SPeter Geis reg-io-width = <4>; 7724e50d217SPeter Geis reg-shift = <2>; 7734e50d217SPeter Geis status = "disabled"; 7744e50d217SPeter Geis }; 7754e50d217SPeter Geis 7764e50d217SPeter Geis uart5: serial@fe690000 { 7774e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7784e50d217SPeter Geis reg = <0x0 0xfe690000 0x0 0x100>; 7794e50d217SPeter Geis interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 7804e50d217SPeter Geis clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 7814e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7824e50d217SPeter Geis dmas = <&dmac0 10>, <&dmac0 11>; 7834e50d217SPeter Geis pinctrl-0 = <&uart5m0_xfer>; 7844e50d217SPeter Geis pinctrl-names = "default"; 7854e50d217SPeter Geis reg-io-width = <4>; 7864e50d217SPeter Geis reg-shift = <2>; 7874e50d217SPeter Geis status = "disabled"; 7884e50d217SPeter Geis }; 7894e50d217SPeter Geis 7904e50d217SPeter Geis uart6: serial@fe6a0000 { 7914e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 7924e50d217SPeter Geis reg = <0x0 0xfe6a0000 0x0 0x100>; 7934e50d217SPeter Geis interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 7944e50d217SPeter Geis clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 7954e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 7964e50d217SPeter Geis dmas = <&dmac0 12>, <&dmac0 13>; 7974e50d217SPeter Geis pinctrl-0 = <&uart6m0_xfer>; 7984e50d217SPeter Geis pinctrl-names = "default"; 7994e50d217SPeter Geis reg-io-width = <4>; 8004e50d217SPeter Geis reg-shift = <2>; 8014e50d217SPeter Geis status = "disabled"; 8024e50d217SPeter Geis }; 8034e50d217SPeter Geis 8044e50d217SPeter Geis uart7: serial@fe6b0000 { 8054e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 8064e50d217SPeter Geis reg = <0x0 0xfe6b0000 0x0 0x100>; 8074e50d217SPeter Geis interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 8084e50d217SPeter Geis clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 8094e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 8104e50d217SPeter Geis dmas = <&dmac0 14>, <&dmac0 15>; 8114e50d217SPeter Geis pinctrl-0 = <&uart7m0_xfer>; 8124e50d217SPeter Geis pinctrl-names = "default"; 8134e50d217SPeter Geis reg-io-width = <4>; 8144e50d217SPeter Geis reg-shift = <2>; 8154e50d217SPeter Geis status = "disabled"; 8164e50d217SPeter Geis }; 8174e50d217SPeter Geis 8184e50d217SPeter Geis uart8: serial@fe6c0000 { 8194e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 8204e50d217SPeter Geis reg = <0x0 0xfe6c0000 0x0 0x100>; 8214e50d217SPeter Geis interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 8224e50d217SPeter Geis clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 8234e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 8244e50d217SPeter Geis dmas = <&dmac0 16>, <&dmac0 17>; 8254e50d217SPeter Geis pinctrl-0 = <&uart8m0_xfer>; 8264e50d217SPeter Geis pinctrl-names = "default"; 8274e50d217SPeter Geis reg-io-width = <4>; 8284e50d217SPeter Geis reg-shift = <2>; 8294e50d217SPeter Geis status = "disabled"; 8304e50d217SPeter Geis }; 8314e50d217SPeter Geis 8324e50d217SPeter Geis uart9: serial@fe6d0000 { 8334e50d217SPeter Geis compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 8344e50d217SPeter Geis reg = <0x0 0xfe6d0000 0x0 0x100>; 8354e50d217SPeter Geis interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 8364e50d217SPeter Geis clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 8374e50d217SPeter Geis clock-names = "baudclk", "apb_pclk"; 8384e50d217SPeter Geis dmas = <&dmac0 18>, <&dmac0 19>; 8394e50d217SPeter Geis pinctrl-0 = <&uart9m0_xfer>; 8404e50d217SPeter Geis pinctrl-names = "default"; 8414e50d217SPeter Geis reg-io-width = <4>; 8424e50d217SPeter Geis reg-shift = <2>; 8434e50d217SPeter Geis status = "disabled"; 8444e50d217SPeter Geis }; 8454e50d217SPeter Geis 8461330875dSPeter Geis thermal_zones: thermal-zones { 8471330875dSPeter Geis cpu_thermal: cpu-thermal { 8481330875dSPeter Geis polling-delay-passive = <100>; 8491330875dSPeter Geis polling-delay = <1000>; 8501330875dSPeter Geis 8511330875dSPeter Geis thermal-sensors = <&tsadc 0>; 8521330875dSPeter Geis 8531330875dSPeter Geis trips { 8541330875dSPeter Geis cpu_alert0: cpu_alert0 { 8551330875dSPeter Geis temperature = <70000>; 8561330875dSPeter Geis hysteresis = <2000>; 8571330875dSPeter Geis type = "passive"; 8581330875dSPeter Geis }; 8591330875dSPeter Geis cpu_alert1: cpu_alert1 { 8601330875dSPeter Geis temperature = <75000>; 8611330875dSPeter Geis hysteresis = <2000>; 8621330875dSPeter Geis type = "passive"; 8631330875dSPeter Geis }; 8641330875dSPeter Geis cpu_crit: cpu_crit { 8651330875dSPeter Geis temperature = <95000>; 8661330875dSPeter Geis hysteresis = <2000>; 8671330875dSPeter Geis type = "critical"; 8681330875dSPeter Geis }; 8691330875dSPeter Geis }; 8701330875dSPeter Geis 8711330875dSPeter Geis cooling-maps { 8721330875dSPeter Geis map0 { 8731330875dSPeter Geis trip = <&cpu_alert0>; 8741330875dSPeter Geis cooling-device = 8751330875dSPeter Geis <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 8761330875dSPeter Geis <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 8771330875dSPeter Geis <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 8781330875dSPeter Geis <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8791330875dSPeter Geis }; 8801330875dSPeter Geis }; 8811330875dSPeter Geis }; 8821330875dSPeter Geis 8831330875dSPeter Geis gpu_thermal: gpu-thermal { 8841330875dSPeter Geis polling-delay-passive = <20>; /* milliseconds */ 8851330875dSPeter Geis polling-delay = <1000>; /* milliseconds */ 8861330875dSPeter Geis 8871330875dSPeter Geis thermal-sensors = <&tsadc 1>; 8881330875dSPeter Geis }; 8891330875dSPeter Geis }; 8901330875dSPeter Geis 8911330875dSPeter Geis tsadc: tsadc@fe710000 { 8921330875dSPeter Geis compatible = "rockchip,rk3568-tsadc"; 8931330875dSPeter Geis reg = <0x0 0xfe710000 0x0 0x100>; 8941330875dSPeter Geis interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 8951330875dSPeter Geis assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 8961330875dSPeter Geis assigned-clock-rates = <17000000>, <700000>; 8971330875dSPeter Geis clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 8981330875dSPeter Geis clock-names = "tsadc", "apb_pclk"; 8991330875dSPeter Geis resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, 9001330875dSPeter Geis <&cru SRST_TSADCPHY>; 9011330875dSPeter Geis reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; 9021330875dSPeter Geis rockchip,grf = <&grf>; 9031330875dSPeter Geis rockchip,hw-tshut-temp = <95000>; 9041330875dSPeter Geis pinctrl-names = "init", "default", "sleep"; 9051330875dSPeter Geis pinctrl-0 = <&tsadc_pin>; 9061330875dSPeter Geis pinctrl-1 = <&tsadc_shutorg>; 9071330875dSPeter Geis pinctrl-2 = <&tsadc_pin>; 9081330875dSPeter Geis #thermal-sensor-cells = <1>; 9091330875dSPeter Geis status = "disabled"; 9101330875dSPeter Geis }; 9111330875dSPeter Geis 9124e50d217SPeter Geis saradc: saradc@fe720000 { 9134e50d217SPeter Geis compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 9144e50d217SPeter Geis reg = <0x0 0xfe720000 0x0 0x100>; 9154e50d217SPeter Geis interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 9164e50d217SPeter Geis clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 9174e50d217SPeter Geis clock-names = "saradc", "apb_pclk"; 9184e50d217SPeter Geis resets = <&cru SRST_P_SARADC>; 9194e50d217SPeter Geis reset-names = "saradc-apb"; 9204e50d217SPeter Geis #io-channel-cells = <1>; 9214e50d217SPeter Geis status = "disabled"; 9224e50d217SPeter Geis }; 9234e50d217SPeter Geis 92498419a39SLiang Chen pwm4: pwm@fe6e0000 { 92598419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 92698419a39SLiang Chen reg = <0x0 0xfe6e0000 0x0 0x10>; 92798419a39SLiang Chen clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 92898419a39SLiang Chen clock-names = "pwm", "pclk"; 92998419a39SLiang Chen pinctrl-0 = <&pwm4_pins>; 93098419a39SLiang Chen pinctrl-names = "active"; 93198419a39SLiang Chen #pwm-cells = <3>; 93298419a39SLiang Chen status = "disabled"; 93398419a39SLiang Chen }; 93498419a39SLiang Chen 93598419a39SLiang Chen pwm5: pwm@fe6e0010 { 93698419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 93798419a39SLiang Chen reg = <0x0 0xfe6e0010 0x0 0x10>; 93898419a39SLiang Chen clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 93998419a39SLiang Chen clock-names = "pwm", "pclk"; 94098419a39SLiang Chen pinctrl-0 = <&pwm5_pins>; 94198419a39SLiang Chen pinctrl-names = "active"; 94298419a39SLiang Chen #pwm-cells = <3>; 94398419a39SLiang Chen status = "disabled"; 94498419a39SLiang Chen }; 94598419a39SLiang Chen 94698419a39SLiang Chen pwm6: pwm@fe6e0020 { 94798419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 94898419a39SLiang Chen reg = <0x0 0xfe6e0020 0x0 0x10>; 94998419a39SLiang Chen clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 95098419a39SLiang Chen clock-names = "pwm", "pclk"; 95198419a39SLiang Chen pinctrl-0 = <&pwm6_pins>; 95298419a39SLiang Chen pinctrl-names = "active"; 95398419a39SLiang Chen #pwm-cells = <3>; 95498419a39SLiang Chen status = "disabled"; 95598419a39SLiang Chen }; 95698419a39SLiang Chen 95798419a39SLiang Chen pwm7: pwm@fe6e0030 { 95898419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 95998419a39SLiang Chen reg = <0x0 0xfe6e0030 0x0 0x10>; 96098419a39SLiang Chen clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 96198419a39SLiang Chen clock-names = "pwm", "pclk"; 96298419a39SLiang Chen pinctrl-0 = <&pwm7_pins>; 96398419a39SLiang Chen pinctrl-names = "active"; 96498419a39SLiang Chen #pwm-cells = <3>; 96598419a39SLiang Chen status = "disabled"; 96698419a39SLiang Chen }; 96798419a39SLiang Chen 96898419a39SLiang Chen pwm8: pwm@fe6f0000 { 96998419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 97098419a39SLiang Chen reg = <0x0 0xfe6f0000 0x0 0x10>; 97198419a39SLiang Chen clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 97298419a39SLiang Chen clock-names = "pwm", "pclk"; 97398419a39SLiang Chen pinctrl-0 = <&pwm8m0_pins>; 97498419a39SLiang Chen pinctrl-names = "active"; 97598419a39SLiang Chen #pwm-cells = <3>; 97698419a39SLiang Chen status = "disabled"; 97798419a39SLiang Chen }; 97898419a39SLiang Chen 97998419a39SLiang Chen pwm9: pwm@fe6f0010 { 98098419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 98198419a39SLiang Chen reg = <0x0 0xfe6f0010 0x0 0x10>; 98298419a39SLiang Chen clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 98398419a39SLiang Chen clock-names = "pwm", "pclk"; 98498419a39SLiang Chen pinctrl-0 = <&pwm9m0_pins>; 98598419a39SLiang Chen pinctrl-names = "active"; 98698419a39SLiang Chen #pwm-cells = <3>; 98798419a39SLiang Chen status = "disabled"; 98898419a39SLiang Chen }; 98998419a39SLiang Chen 99098419a39SLiang Chen pwm10: pwm@fe6f0020 { 99198419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 99298419a39SLiang Chen reg = <0x0 0xfe6f0020 0x0 0x10>; 99398419a39SLiang Chen clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 99498419a39SLiang Chen clock-names = "pwm", "pclk"; 99598419a39SLiang Chen pinctrl-0 = <&pwm10m0_pins>; 99698419a39SLiang Chen pinctrl-names = "active"; 99798419a39SLiang Chen #pwm-cells = <3>; 99898419a39SLiang Chen status = "disabled"; 99998419a39SLiang Chen }; 100098419a39SLiang Chen 100198419a39SLiang Chen pwm11: pwm@fe6f0030 { 100298419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 100398419a39SLiang Chen reg = <0x0 0xfe6f0030 0x0 0x10>; 100498419a39SLiang Chen clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 100598419a39SLiang Chen clock-names = "pwm", "pclk"; 100698419a39SLiang Chen pinctrl-0 = <&pwm11m0_pins>; 100798419a39SLiang Chen pinctrl-names = "active"; 100898419a39SLiang Chen #pwm-cells = <3>; 100998419a39SLiang Chen status = "disabled"; 101098419a39SLiang Chen }; 101198419a39SLiang Chen 101298419a39SLiang Chen pwm12: pwm@fe700000 { 101398419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 101498419a39SLiang Chen reg = <0x0 0xfe700000 0x0 0x10>; 101598419a39SLiang Chen clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 101698419a39SLiang Chen clock-names = "pwm", "pclk"; 101798419a39SLiang Chen pinctrl-0 = <&pwm12m0_pins>; 101898419a39SLiang Chen pinctrl-names = "active"; 101998419a39SLiang Chen #pwm-cells = <3>; 102098419a39SLiang Chen status = "disabled"; 102198419a39SLiang Chen }; 102298419a39SLiang Chen 102398419a39SLiang Chen pwm13: pwm@fe700010 { 102498419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 102598419a39SLiang Chen reg = <0x0 0xfe700010 0x0 0x10>; 102698419a39SLiang Chen clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 102798419a39SLiang Chen clock-names = "pwm", "pclk"; 102898419a39SLiang Chen pinctrl-0 = <&pwm13m0_pins>; 102998419a39SLiang Chen pinctrl-names = "active"; 103098419a39SLiang Chen #pwm-cells = <3>; 103198419a39SLiang Chen status = "disabled"; 103298419a39SLiang Chen }; 103398419a39SLiang Chen 103498419a39SLiang Chen pwm14: pwm@fe700020 { 103598419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 103698419a39SLiang Chen reg = <0x0 0xfe700020 0x0 0x10>; 103798419a39SLiang Chen clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 103898419a39SLiang Chen clock-names = "pwm", "pclk"; 103998419a39SLiang Chen pinctrl-0 = <&pwm14m0_pins>; 104098419a39SLiang Chen pinctrl-names = "active"; 104198419a39SLiang Chen #pwm-cells = <3>; 104298419a39SLiang Chen status = "disabled"; 104398419a39SLiang Chen }; 104498419a39SLiang Chen 104598419a39SLiang Chen pwm15: pwm@fe700030 { 104698419a39SLiang Chen compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 104798419a39SLiang Chen reg = <0x0 0xfe700030 0x0 0x10>; 104898419a39SLiang Chen clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 104998419a39SLiang Chen clock-names = "pwm", "pclk"; 105098419a39SLiang Chen pinctrl-0 = <&pwm15m0_pins>; 105198419a39SLiang Chen pinctrl-names = "active"; 105298419a39SLiang Chen #pwm-cells = <3>; 105398419a39SLiang Chen status = "disabled"; 105498419a39SLiang Chen }; 105598419a39SLiang Chen 10564e50d217SPeter Geis pinctrl: pinctrl { 10574e50d217SPeter Geis compatible = "rockchip,rk3568-pinctrl"; 10584e50d217SPeter Geis rockchip,grf = <&grf>; 10594e50d217SPeter Geis rockchip,pmu = <&pmugrf>; 10604e50d217SPeter Geis #address-cells = <2>; 10614e50d217SPeter Geis #size-cells = <2>; 10624e50d217SPeter Geis ranges; 10634e50d217SPeter Geis 10644e50d217SPeter Geis gpio0: gpio@fdd60000 { 10654e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 10664e50d217SPeter Geis reg = <0x0 0xfdd60000 0x0 0x100>; 10674e50d217SPeter Geis interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 10683d9170c3SPeter Geis clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 10694e50d217SPeter Geis gpio-controller; 10704e50d217SPeter Geis #gpio-cells = <2>; 10714e50d217SPeter Geis interrupt-controller; 10724e50d217SPeter Geis #interrupt-cells = <2>; 10734e50d217SPeter Geis }; 10744e50d217SPeter Geis 10754e50d217SPeter Geis gpio1: gpio@fe740000 { 10764e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 10774e50d217SPeter Geis reg = <0x0 0xfe740000 0x0 0x100>; 10784e50d217SPeter Geis interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 10793d9170c3SPeter Geis clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 10804e50d217SPeter Geis gpio-controller; 10814e50d217SPeter Geis #gpio-cells = <2>; 10824e50d217SPeter Geis interrupt-controller; 10834e50d217SPeter Geis #interrupt-cells = <2>; 10844e50d217SPeter Geis }; 10854e50d217SPeter Geis 10864e50d217SPeter Geis gpio2: gpio@fe750000 { 10874e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 10884e50d217SPeter Geis reg = <0x0 0xfe750000 0x0 0x100>; 10894e50d217SPeter Geis interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 10903d9170c3SPeter Geis clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 10914e50d217SPeter Geis gpio-controller; 10924e50d217SPeter Geis #gpio-cells = <2>; 10934e50d217SPeter Geis interrupt-controller; 10944e50d217SPeter Geis #interrupt-cells = <2>; 10954e50d217SPeter Geis }; 10964e50d217SPeter Geis 10974e50d217SPeter Geis gpio3: gpio@fe760000 { 10984e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 10994e50d217SPeter Geis reg = <0x0 0xfe760000 0x0 0x100>; 11004e50d217SPeter Geis interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 11013d9170c3SPeter Geis clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 11024e50d217SPeter Geis gpio-controller; 11034e50d217SPeter Geis #gpio-cells = <2>; 11044e50d217SPeter Geis interrupt-controller; 11054e50d217SPeter Geis #interrupt-cells = <2>; 11064e50d217SPeter Geis }; 11074e50d217SPeter Geis 11084e50d217SPeter Geis gpio4: gpio@fe770000 { 11094e50d217SPeter Geis compatible = "rockchip,gpio-bank"; 11104e50d217SPeter Geis reg = <0x0 0xfe770000 0x0 0x100>; 11114e50d217SPeter Geis interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 11123d9170c3SPeter Geis clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 11134e50d217SPeter Geis gpio-controller; 11144e50d217SPeter Geis #gpio-cells = <2>; 11154e50d217SPeter Geis interrupt-controller; 11164e50d217SPeter Geis #interrupt-cells = <2>; 11174e50d217SPeter Geis }; 11184e50d217SPeter Geis }; 11194e50d217SPeter Geis}; 11204e50d217SPeter Geis 11214e50d217SPeter Geis#include "rk3568-pinctrl.dtsi" 1122