1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3568"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 i2c4 = &i2c4; 33 i2c5 = &i2c5; 34 serial0 = &uart0; 35 serial1 = &uart1; 36 serial2 = &uart2; 37 serial3 = &uart3; 38 serial4 = &uart4; 39 serial5 = &uart5; 40 serial6 = &uart6; 41 serial7 = &uart7; 42 serial8 = &uart8; 43 serial9 = &uart9; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a55"; 53 reg = <0x0 0x0>; 54 clocks = <&scmi_clk 0>; 55 enable-method = "psci"; 56 operating-points-v2 = <&cpu0_opp_table>; 57 }; 58 59 cpu1: cpu@100 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x0 0x100>; 63 enable-method = "psci"; 64 operating-points-v2 = <&cpu0_opp_table>; 65 }; 66 67 cpu2: cpu@200 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a55"; 70 reg = <0x0 0x200>; 71 enable-method = "psci"; 72 operating-points-v2 = <&cpu0_opp_table>; 73 }; 74 75 cpu3: cpu@300 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x0 0x300>; 79 enable-method = "psci"; 80 operating-points-v2 = <&cpu0_opp_table>; 81 }; 82 }; 83 84 cpu0_opp_table: cpu0-opp-table { 85 compatible = "operating-points-v2"; 86 opp-shared; 87 88 opp-408000000 { 89 opp-hz = /bits/ 64 <408000000>; 90 opp-microvolt = <900000 900000 1150000>; 91 clock-latency-ns = <40000>; 92 }; 93 94 opp-600000000 { 95 opp-hz = /bits/ 64 <600000000>; 96 opp-microvolt = <900000 900000 1150000>; 97 }; 98 99 opp-816000000 { 100 opp-hz = /bits/ 64 <816000000>; 101 opp-microvolt = <900000 900000 1150000>; 102 opp-suspend; 103 }; 104 105 opp-1104000000 { 106 opp-hz = /bits/ 64 <1104000000>; 107 opp-microvolt = <900000 900000 1150000>; 108 }; 109 110 opp-1416000000 { 111 opp-hz = /bits/ 64 <1416000000>; 112 opp-microvolt = <900000 900000 1150000>; 113 }; 114 115 opp-1608000000 { 116 opp-hz = /bits/ 64 <1608000000>; 117 opp-microvolt = <975000 975000 1150000>; 118 }; 119 120 opp-1800000000 { 121 opp-hz = /bits/ 64 <1800000000>; 122 opp-microvolt = <1050000 1050000 1150000>; 123 }; 124 125 opp-1992000000 { 126 opp-hz = /bits/ 64 <1992000000>; 127 opp-microvolt = <1150000 1150000 1150000>; 128 }; 129 }; 130 131 firmware { 132 scmi: scmi { 133 compatible = "arm,scmi-smc"; 134 arm,smc-id = <0x82000010>; 135 shmem = <&scmi_shmem>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 scmi_clk: protocol@14 { 140 reg = <0x14>; 141 #clock-cells = <1>; 142 }; 143 }; 144 }; 145 146 pmu { 147 compatible = "arm,cortex-a55-pmu"; 148 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 152 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 153 }; 154 155 psci { 156 compatible = "arm,psci-1.0"; 157 method = "smc"; 158 }; 159 160 timer { 161 compatible = "arm,armv8-timer"; 162 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 166 arm,no-tick-in-suspend; 167 }; 168 169 xin24m: xin24m { 170 compatible = "fixed-clock"; 171 clock-frequency = <24000000>; 172 clock-output-names = "xin24m"; 173 #clock-cells = <0>; 174 }; 175 176 xin32k: xin32k { 177 compatible = "fixed-clock"; 178 clock-frequency = <32768>; 179 clock-output-names = "xin32k"; 180 pinctrl-0 = <&clk32k_out0>; 181 pinctrl-names = "default"; 182 #clock-cells = <0>; 183 }; 184 185 sram@10f000 { 186 compatible = "mmio-sram"; 187 reg = <0x0 0x0010f000 0x0 0x100>; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges = <0 0x0 0x0010f000 0x100>; 191 192 scmi_shmem: sram@0 { 193 compatible = "arm,scmi-shmem"; 194 reg = <0x0 0x100>; 195 }; 196 }; 197 198 gic: interrupt-controller@fd400000 { 199 compatible = "arm,gic-v3"; 200 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 201 <0x0 0xfd460000 0 0x80000>; /* GICR */ 202 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 203 interrupt-controller; 204 #interrupt-cells = <3>; 205 mbi-alias = <0x0 0xfd100000>; 206 mbi-ranges = <296 24>; 207 msi-controller; 208 }; 209 210 pmugrf: syscon@fdc20000 { 211 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 212 reg = <0x0 0xfdc20000 0x0 0x10000>; 213 }; 214 215 grf: syscon@fdc60000 { 216 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 217 reg = <0x0 0xfdc60000 0x0 0x10000>; 218 }; 219 220 pmucru: clock-controller@fdd00000 { 221 compatible = "rockchip,rk3568-pmucru"; 222 reg = <0x0 0xfdd00000 0x0 0x1000>; 223 #clock-cells = <1>; 224 #reset-cells = <1>; 225 }; 226 227 cru: clock-controller@fdd20000 { 228 compatible = "rockchip,rk3568-cru"; 229 reg = <0x0 0xfdd20000 0x0 0x1000>; 230 #clock-cells = <1>; 231 #reset-cells = <1>; 232 }; 233 234 i2c0: i2c@fdd40000 { 235 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 236 reg = <0x0 0xfdd40000 0x0 0x1000>; 237 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 239 clock-names = "i2c", "pclk"; 240 pinctrl-0 = <&i2c0_xfer>; 241 pinctrl-names = "default"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 status = "disabled"; 245 }; 246 247 uart0: serial@fdd50000 { 248 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 249 reg = <0x0 0xfdd50000 0x0 0x100>; 250 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 252 clock-names = "baudclk", "apb_pclk"; 253 dmas = <&dmac0 0>, <&dmac0 1>; 254 pinctrl-0 = <&uart0_xfer>; 255 pinctrl-names = "default"; 256 reg-io-width = <4>; 257 reg-shift = <2>; 258 status = "disabled"; 259 }; 260 261 pmu: power-management@fdd90000 { 262 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 263 reg = <0x0 0xfdd90000 0x0 0x1000>; 264 265 power: power-controller { 266 compatible = "rockchip,rk3568-power-controller"; 267 #power-domain-cells = <1>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 /* These power domains are grouped by VD_GPU */ 272 power-domain@RK3568_PD_GPU { 273 reg = <RK3568_PD_GPU>; 274 clocks = <&cru ACLK_GPU_PRE>, 275 <&cru PCLK_GPU_PRE>; 276 pm_qos = <&qos_gpu>; 277 #power-domain-cells = <0>; 278 }; 279 280 /* These power domains are grouped by VD_LOGIC */ 281 power-domain@RK3568_PD_VI { 282 reg = <RK3568_PD_VI>; 283 clocks = <&cru HCLK_VI>, 284 <&cru PCLK_VI>; 285 pm_qos = <&qos_isp>, 286 <&qos_vicap0>, 287 <&qos_vicap1>; 288 #power-domain-cells = <0>; 289 }; 290 291 power-domain@RK3568_PD_VO { 292 reg = <RK3568_PD_VO>; 293 clocks = <&cru HCLK_VO>, 294 <&cru PCLK_VO>, 295 <&cru ACLK_VOP_PRE>; 296 pm_qos = <&qos_hdcp>, 297 <&qos_vop_m0>, 298 <&qos_vop_m1>; 299 #power-domain-cells = <0>; 300 }; 301 302 power-domain@RK3568_PD_RGA { 303 reg = <RK3568_PD_RGA>; 304 clocks = <&cru HCLK_RGA_PRE>, 305 <&cru PCLK_RGA_PRE>; 306 pm_qos = <&qos_ebc>, 307 <&qos_iep>, 308 <&qos_jpeg_dec>, 309 <&qos_jpeg_enc>, 310 <&qos_rga_rd>, 311 <&qos_rga_wr>; 312 #power-domain-cells = <0>; 313 }; 314 315 power-domain@RK3568_PD_VPU { 316 reg = <RK3568_PD_VPU>; 317 clocks = <&cru HCLK_VPU_PRE>; 318 pm_qos = <&qos_vpu>; 319 #power-domain-cells = <0>; 320 }; 321 322 power-domain@RK3568_PD_RKVDEC { 323 clocks = <&cru HCLK_RKVDEC_PRE>; 324 reg = <RK3568_PD_RKVDEC>; 325 pm_qos = <&qos_rkvdec>; 326 #power-domain-cells = <0>; 327 }; 328 329 power-domain@RK3568_PD_RKVENC { 330 reg = <RK3568_PD_RKVENC>; 331 clocks = <&cru HCLK_RKVENC_PRE>; 332 pm_qos = <&qos_rkvenc_rd_m0>, 333 <&qos_rkvenc_rd_m1>, 334 <&qos_rkvenc_wr_m0>; 335 #power-domain-cells = <0>; 336 }; 337 338 power-domain@RK3568_PD_PIPE { 339 reg = <RK3568_PD_PIPE>; 340 clocks = <&cru PCLK_PIPE>; 341 pm_qos = <&qos_pcie2x1>, 342 <&qos_pcie3x1>, 343 <&qos_pcie3x2>, 344 <&qos_sata0>, 345 <&qos_sata1>, 346 <&qos_sata2>, 347 <&qos_usb3_0>, 348 <&qos_usb3_1>; 349 #power-domain-cells = <0>; 350 }; 351 }; 352 }; 353 354 sdmmc2: mmc@fe000000 { 355 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 356 reg = <0x0 0xfe000000 0x0 0x4000>; 357 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 359 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 360 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 361 fifo-depth = <0x100>; 362 max-frequency = <150000000>; 363 resets = <&cru SRST_SDMMC2>; 364 reset-names = "reset"; 365 status = "disabled"; 366 }; 367 368 qos_gpu: qos@fe128000 { 369 compatible = "rockchip,rk3568-qos", "syscon"; 370 reg = <0x0 0xfe128000 0x0 0x20>; 371 }; 372 373 qos_rkvenc_rd_m0: qos@fe138080 { 374 compatible = "rockchip,rk3568-qos", "syscon"; 375 reg = <0x0 0xfe138080 0x0 0x20>; 376 }; 377 378 qos_rkvenc_rd_m1: qos@fe138100 { 379 compatible = "rockchip,rk3568-qos", "syscon"; 380 reg = <0x0 0xfe138100 0x0 0x20>; 381 }; 382 383 qos_rkvenc_wr_m0: qos@fe138180 { 384 compatible = "rockchip,rk3568-qos", "syscon"; 385 reg = <0x0 0xfe138180 0x0 0x20>; 386 }; 387 388 qos_isp: qos@fe148000 { 389 compatible = "rockchip,rk3568-qos", "syscon"; 390 reg = <0x0 0xfe148000 0x0 0x20>; 391 }; 392 393 qos_vicap0: qos@fe148080 { 394 compatible = "rockchip,rk3568-qos", "syscon"; 395 reg = <0x0 0xfe148080 0x0 0x20>; 396 }; 397 398 qos_vicap1: qos@fe148100 { 399 compatible = "rockchip,rk3568-qos", "syscon"; 400 reg = <0x0 0xfe148100 0x0 0x20>; 401 }; 402 403 qos_vpu: qos@fe150000 { 404 compatible = "rockchip,rk3568-qos", "syscon"; 405 reg = <0x0 0xfe150000 0x0 0x20>; 406 }; 407 408 qos_ebc: qos@fe158000 { 409 compatible = "rockchip,rk3568-qos", "syscon"; 410 reg = <0x0 0xfe158000 0x0 0x20>; 411 }; 412 413 qos_iep: qos@fe158100 { 414 compatible = "rockchip,rk3568-qos", "syscon"; 415 reg = <0x0 0xfe158100 0x0 0x20>; 416 }; 417 418 qos_jpeg_dec: qos@fe158180 { 419 compatible = "rockchip,rk3568-qos", "syscon"; 420 reg = <0x0 0xfe158180 0x0 0x20>; 421 }; 422 423 qos_jpeg_enc: qos@fe158200 { 424 compatible = "rockchip,rk3568-qos", "syscon"; 425 reg = <0x0 0xfe158200 0x0 0x20>; 426 }; 427 428 qos_rga_rd: qos@fe158280 { 429 compatible = "rockchip,rk3568-qos", "syscon"; 430 reg = <0x0 0xfe158280 0x0 0x20>; 431 }; 432 433 qos_rga_wr: qos@fe158300 { 434 compatible = "rockchip,rk3568-qos", "syscon"; 435 reg = <0x0 0xfe158300 0x0 0x20>; 436 }; 437 438 qos_npu: qos@fe180000 { 439 compatible = "rockchip,rk3568-qos", "syscon"; 440 reg = <0x0 0xfe180000 0x0 0x20>; 441 }; 442 443 qos_pcie2x1: qos@fe190000 { 444 compatible = "rockchip,rk3568-qos", "syscon"; 445 reg = <0x0 0xfe190000 0x0 0x20>; 446 }; 447 448 qos_pcie3x1: qos@fe190080 { 449 compatible = "rockchip,rk3568-qos", "syscon"; 450 reg = <0x0 0xfe190080 0x0 0x20>; 451 }; 452 453 qos_pcie3x2: qos@fe190100 { 454 compatible = "rockchip,rk3568-qos", "syscon"; 455 reg = <0x0 0xfe190100 0x0 0x20>; 456 }; 457 458 qos_sata0: qos@fe190200 { 459 compatible = "rockchip,rk3568-qos", "syscon"; 460 reg = <0x0 0xfe190200 0x0 0x20>; 461 }; 462 463 qos_sata1: qos@fe190280 { 464 compatible = "rockchip,rk3568-qos", "syscon"; 465 reg = <0x0 0xfe190280 0x0 0x20>; 466 }; 467 468 qos_sata2: qos@fe190300 { 469 compatible = "rockchip,rk3568-qos", "syscon"; 470 reg = <0x0 0xfe190300 0x0 0x20>; 471 }; 472 473 qos_usb3_0: qos@fe190380 { 474 compatible = "rockchip,rk3568-qos", "syscon"; 475 reg = <0x0 0xfe190380 0x0 0x20>; 476 }; 477 478 qos_usb3_1: qos@fe190400 { 479 compatible = "rockchip,rk3568-qos", "syscon"; 480 reg = <0x0 0xfe190400 0x0 0x20>; 481 }; 482 483 qos_rkvdec: qos@fe198000 { 484 compatible = "rockchip,rk3568-qos", "syscon"; 485 reg = <0x0 0xfe198000 0x0 0x20>; 486 }; 487 488 qos_hdcp: qos@fe1a8000 { 489 compatible = "rockchip,rk3568-qos", "syscon"; 490 reg = <0x0 0xfe1a8000 0x0 0x20>; 491 }; 492 493 qos_vop_m0: qos@fe1a8080 { 494 compatible = "rockchip,rk3568-qos", "syscon"; 495 reg = <0x0 0xfe1a8080 0x0 0x20>; 496 }; 497 498 qos_vop_m1: qos@fe1a8100 { 499 compatible = "rockchip,rk3568-qos", "syscon"; 500 reg = <0x0 0xfe1a8100 0x0 0x20>; 501 }; 502 503 sdmmc0: mmc@fe2b0000 { 504 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 505 reg = <0x0 0xfe2b0000 0x0 0x4000>; 506 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 508 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 509 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 510 fifo-depth = <0x100>; 511 max-frequency = <150000000>; 512 resets = <&cru SRST_SDMMC0>; 513 reset-names = "reset"; 514 status = "disabled"; 515 }; 516 517 sdmmc1: mmc@fe2c0000 { 518 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 519 reg = <0x0 0xfe2c0000 0x0 0x4000>; 520 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 522 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 523 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 524 fifo-depth = <0x100>; 525 max-frequency = <150000000>; 526 resets = <&cru SRST_SDMMC1>; 527 reset-names = "reset"; 528 status = "disabled"; 529 }; 530 531 sdhci: mmc@fe310000 { 532 compatible = "rockchip,rk3568-dwcmshc"; 533 reg = <0x0 0xfe310000 0x0 0x10000>; 534 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 535 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 536 assigned-clock-rates = <200000000>, <24000000>; 537 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 538 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 539 <&cru TCLK_EMMC>; 540 clock-names = "core", "bus", "axi", "block", "timer"; 541 status = "disabled"; 542 }; 543 544 dmac0: dmac@fe530000 { 545 compatible = "arm,pl330", "arm,primecell"; 546 reg = <0x0 0xfe530000 0x0 0x4000>; 547 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 549 arm,pl330-periph-burst; 550 clocks = <&cru ACLK_BUS>; 551 clock-names = "apb_pclk"; 552 #dma-cells = <1>; 553 }; 554 555 dmac1: dmac@fe550000 { 556 compatible = "arm,pl330", "arm,primecell"; 557 reg = <0x0 0xfe550000 0x0 0x4000>; 558 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 560 arm,pl330-periph-burst; 561 clocks = <&cru ACLK_BUS>; 562 clock-names = "apb_pclk"; 563 #dma-cells = <1>; 564 }; 565 566 i2c1: i2c@fe5a0000 { 567 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 568 reg = <0x0 0xfe5a0000 0x0 0x1000>; 569 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 571 clock-names = "i2c", "pclk"; 572 pinctrl-0 = <&i2c1_xfer>; 573 pinctrl-names = "default"; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 }; 578 579 i2c2: i2c@fe5b0000 { 580 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 581 reg = <0x0 0xfe5b0000 0x0 0x1000>; 582 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 584 clock-names = "i2c", "pclk"; 585 pinctrl-0 = <&i2c2m0_xfer>; 586 pinctrl-names = "default"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 i2c3: i2c@fe5c0000 { 593 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 594 reg = <0x0 0xfe5c0000 0x0 0x1000>; 595 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 597 clock-names = "i2c", "pclk"; 598 pinctrl-0 = <&i2c3m0_xfer>; 599 pinctrl-names = "default"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 status = "disabled"; 603 }; 604 605 i2c4: i2c@fe5d0000 { 606 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 607 reg = <0x0 0xfe5d0000 0x0 0x1000>; 608 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 610 clock-names = "i2c", "pclk"; 611 pinctrl-0 = <&i2c4m0_xfer>; 612 pinctrl-names = "default"; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 status = "disabled"; 616 }; 617 618 i2c5: i2c@fe5e0000 { 619 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 620 reg = <0x0 0xfe5e0000 0x0 0x1000>; 621 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 623 clock-names = "i2c", "pclk"; 624 pinctrl-0 = <&i2c5m0_xfer>; 625 pinctrl-names = "default"; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 uart1: serial@fe650000 { 632 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 633 reg = <0x0 0xfe650000 0x0 0x100>; 634 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 636 clock-names = "baudclk", "apb_pclk"; 637 dmas = <&dmac0 2>, <&dmac0 3>; 638 pinctrl-0 = <&uart1m0_xfer>; 639 pinctrl-names = "default"; 640 reg-io-width = <4>; 641 reg-shift = <2>; 642 status = "disabled"; 643 }; 644 645 uart2: serial@fe660000 { 646 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 647 reg = <0x0 0xfe660000 0x0 0x100>; 648 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 650 clock-names = "baudclk", "apb_pclk"; 651 dmas = <&dmac0 4>, <&dmac0 5>; 652 pinctrl-0 = <&uart2m0_xfer>; 653 pinctrl-names = "default"; 654 reg-io-width = <4>; 655 reg-shift = <2>; 656 status = "disabled"; 657 }; 658 659 uart3: serial@fe670000 { 660 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 661 reg = <0x0 0xfe670000 0x0 0x100>; 662 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 664 clock-names = "baudclk", "apb_pclk"; 665 dmas = <&dmac0 6>, <&dmac0 7>; 666 pinctrl-0 = <&uart3m0_xfer>; 667 pinctrl-names = "default"; 668 reg-io-width = <4>; 669 reg-shift = <2>; 670 status = "disabled"; 671 }; 672 673 uart4: serial@fe680000 { 674 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 675 reg = <0x0 0xfe680000 0x0 0x100>; 676 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 678 clock-names = "baudclk", "apb_pclk"; 679 dmas = <&dmac0 8>, <&dmac0 9>; 680 pinctrl-0 = <&uart4m0_xfer>; 681 pinctrl-names = "default"; 682 reg-io-width = <4>; 683 reg-shift = <2>; 684 status = "disabled"; 685 }; 686 687 uart5: serial@fe690000 { 688 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 689 reg = <0x0 0xfe690000 0x0 0x100>; 690 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 692 clock-names = "baudclk", "apb_pclk"; 693 dmas = <&dmac0 10>, <&dmac0 11>; 694 pinctrl-0 = <&uart5m0_xfer>; 695 pinctrl-names = "default"; 696 reg-io-width = <4>; 697 reg-shift = <2>; 698 status = "disabled"; 699 }; 700 701 uart6: serial@fe6a0000 { 702 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 703 reg = <0x0 0xfe6a0000 0x0 0x100>; 704 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 705 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 706 clock-names = "baudclk", "apb_pclk"; 707 dmas = <&dmac0 12>, <&dmac0 13>; 708 pinctrl-0 = <&uart6m0_xfer>; 709 pinctrl-names = "default"; 710 reg-io-width = <4>; 711 reg-shift = <2>; 712 status = "disabled"; 713 }; 714 715 uart7: serial@fe6b0000 { 716 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 717 reg = <0x0 0xfe6b0000 0x0 0x100>; 718 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 720 clock-names = "baudclk", "apb_pclk"; 721 dmas = <&dmac0 14>, <&dmac0 15>; 722 pinctrl-0 = <&uart7m0_xfer>; 723 pinctrl-names = "default"; 724 reg-io-width = <4>; 725 reg-shift = <2>; 726 status = "disabled"; 727 }; 728 729 uart8: serial@fe6c0000 { 730 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 731 reg = <0x0 0xfe6c0000 0x0 0x100>; 732 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 734 clock-names = "baudclk", "apb_pclk"; 735 dmas = <&dmac0 16>, <&dmac0 17>; 736 pinctrl-0 = <&uart8m0_xfer>; 737 pinctrl-names = "default"; 738 reg-io-width = <4>; 739 reg-shift = <2>; 740 status = "disabled"; 741 }; 742 743 uart9: serial@fe6d0000 { 744 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 745 reg = <0x0 0xfe6d0000 0x0 0x100>; 746 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 748 clock-names = "baudclk", "apb_pclk"; 749 dmas = <&dmac0 18>, <&dmac0 19>; 750 pinctrl-0 = <&uart9m0_xfer>; 751 pinctrl-names = "default"; 752 reg-io-width = <4>; 753 reg-shift = <2>; 754 status = "disabled"; 755 }; 756 757 saradc: saradc@fe720000 { 758 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 759 reg = <0x0 0xfe720000 0x0 0x100>; 760 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 762 clock-names = "saradc", "apb_pclk"; 763 resets = <&cru SRST_P_SARADC>; 764 reset-names = "saradc-apb"; 765 #io-channel-cells = <1>; 766 status = "disabled"; 767 }; 768 769 pinctrl: pinctrl { 770 compatible = "rockchip,rk3568-pinctrl"; 771 rockchip,grf = <&grf>; 772 rockchip,pmu = <&pmugrf>; 773 #address-cells = <2>; 774 #size-cells = <2>; 775 ranges; 776 777 gpio0: gpio@fdd60000 { 778 compatible = "rockchip,gpio-bank"; 779 reg = <0x0 0xfdd60000 0x0 0x100>; 780 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&pmucru PCLK_GPIO0>; 782 gpio-controller; 783 #gpio-cells = <2>; 784 interrupt-controller; 785 #interrupt-cells = <2>; 786 }; 787 788 gpio1: gpio@fe740000 { 789 compatible = "rockchip,gpio-bank"; 790 reg = <0x0 0xfe740000 0x0 0x100>; 791 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&cru PCLK_GPIO1>; 793 gpio-controller; 794 #gpio-cells = <2>; 795 interrupt-controller; 796 #interrupt-cells = <2>; 797 }; 798 799 gpio2: gpio@fe750000 { 800 compatible = "rockchip,gpio-bank"; 801 reg = <0x0 0xfe750000 0x0 0x100>; 802 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&cru PCLK_GPIO2>; 804 gpio-controller; 805 #gpio-cells = <2>; 806 interrupt-controller; 807 #interrupt-cells = <2>; 808 }; 809 810 gpio3: gpio@fe760000 { 811 compatible = "rockchip,gpio-bank"; 812 reg = <0x0 0xfe760000 0x0 0x100>; 813 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&cru PCLK_GPIO3>; 815 gpio-controller; 816 #gpio-cells = <2>; 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 }; 820 821 gpio4: gpio@fe770000 { 822 compatible = "rockchip,gpio-bank"; 823 reg = <0x0 0xfe770000 0x0 0x100>; 824 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&cru PCLK_GPIO4>; 826 gpio-controller; 827 #gpio-cells = <2>; 828 interrupt-controller; 829 #interrupt-cells = <2>; 830 }; 831 }; 832}; 833 834#include "rk3568-pinctrl.dtsi" 835