1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 *
5 */
6
7/dts-v1/;
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rockchip.h>
10#include "rk3568.dtsi"
11
12/ {
13	model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
14	compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
15
16	aliases {
17		ethernet0 = &gmac0;
18		ethernet1 = &gmac1;
19	};
20
21	chosen: chosen {
22		stdout-path = "serial2:1500000n8";
23	};
24
25	dc_12v: dc-12v {
26		compatible = "regulator-fixed";
27		regulator-name = "dc_12v";
28		regulator-always-on;
29		regulator-boot-on;
30		regulator-min-microvolt = <12000000>;
31		regulator-max-microvolt = <12000000>;
32	};
33
34	vcc3v3_sys: vcc3v3-sys {
35		compatible = "regulator-fixed";
36		regulator-name = "vcc3v3_sys";
37		regulator-always-on;
38		regulator-boot-on;
39		regulator-min-microvolt = <3300000>;
40		regulator-max-microvolt = <3300000>;
41		vin-supply = <&dc_12v>;
42	};
43
44	vcc5v0_sys: vcc5v0-sys {
45		compatible = "regulator-fixed";
46		regulator-name = "vcc5v0_sys";
47		regulator-always-on;
48		regulator-boot-on;
49		regulator-min-microvolt = <5000000>;
50		regulator-max-microvolt = <5000000>;
51		vin-supply = <&dc_12v>;
52	};
53
54	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
55		compatible = "regulator-fixed";
56		regulator-name = "vcc3v3_lcd0_n";
57		regulator-boot-on;
58
59		regulator-state-mem {
60			regulator-off-in-suspend;
61		};
62	};
63
64	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
65		compatible = "regulator-fixed";
66		regulator-name = "vcc3v3_lcd1_n";
67		regulator-boot-on;
68
69		regulator-state-mem {
70			regulator-off-in-suspend;
71		};
72	};
73};
74
75&gmac0 {
76	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
77	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
78	assigned-clock-rates = <0>, <125000000>;
79	clock_in_out = "output";
80	phy-handle = <&rgmii_phy0>;
81	phy-mode = "rgmii-id";
82	pinctrl-names = "default";
83	pinctrl-0 = <&gmac0_miim
84		     &gmac0_tx_bus2
85		     &gmac0_rx_bus2
86		     &gmac0_rgmii_clk
87		     &gmac0_rgmii_bus>;
88	status = "okay";
89};
90
91&gmac1 {
92	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
93	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
94	assigned-clock-rates = <0>, <125000000>;
95	clock_in_out = "output";
96	phy-handle = <&rgmii_phy1>;
97	phy-mode = "rgmii-id";
98	pinctrl-names = "default";
99	pinctrl-0 = <&gmac1m1_miim
100		     &gmac1m1_tx_bus2
101		     &gmac1m1_rx_bus2
102		     &gmac1m1_rgmii_clk
103		     &gmac1m1_rgmii_bus>;
104	status = "okay";
105};
106
107&mdio0 {
108	rgmii_phy0: ethernet-phy@0 {
109		compatible = "ethernet-phy-ieee802.3-c22";
110		reg = <0x0>;
111		reset-assert-us = <20000>;
112		reset-deassert-us = <100000>;
113		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
114	};
115};
116
117&mdio1 {
118	rgmii_phy1: ethernet-phy@0 {
119		compatible = "ethernet-phy-ieee802.3-c22";
120		reg = <0x0>;
121		reset-assert-us = <20000>;
122		reset-deassert-us = <100000>;
123		reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
124	};
125};
126
127&sdhci {
128	bus-width = <8>;
129	max-frequency = <200000000>;
130	non-removable;
131	status = "okay";
132};
133
134&uart2 {
135	status = "okay";
136};
137