1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Gru-scarlet board device tree source
4 *
5 * Copyright 2018 Google, Inc
6 */
7
8#include "rk3399-gru.dtsi"
9
10/{
11	/* Power tree */
12
13	/* ppvar_sys children, sorted by name */
14	pp1250_s3: pp1250-s3 {
15		compatible = "regulator-fixed";
16		regulator-name = "pp1250_s3";
17
18		/* EC turns on w/ pp1250_s3_en; always on for AP */
19		regulator-always-on;
20		regulator-boot-on;
21		regulator-min-microvolt = <1250000>;
22		regulator-max-microvolt = <1250000>;
23
24		vin-supply = <&ppvar_sys>;
25	};
26
27	pp1250_cam: pp1250-dvdd {
28		compatible = "regulator-fixed";
29		regulator-name = "pp1250_dvdd";
30		pinctrl-names = "default";
31		pinctrl-0 = <&pp1250_cam_en>;
32
33		enable-active-high;
34		gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;
35
36		/* 740us delay from gpio output high to pp1250 stable,
37		 * rounding up to 1ms for safety.
38		 */
39		startup-delay-us = <1000>;
40		vin-supply = <&pp1250_s3>;
41	};
42
43	pp900_s0: pp900-s0 {
44		compatible = "regulator-fixed";
45		regulator-name = "pp900_s0";
46
47		/* EC turns on w/ pp900_s0_en; always on for AP */
48		regulator-always-on;
49		regulator-boot-on;
50		regulator-min-microvolt = <900000>;
51		regulator-max-microvolt = <900000>;
52
53		vin-supply = <&ppvar_sys>;
54	};
55
56	ppvarn_lcd: ppvarn-lcd {
57		compatible = "regulator-fixed";
58		regulator-name = "ppvarn_lcd";
59		pinctrl-names = "default";
60		pinctrl-0 = <&ppvarn_lcd_en>;
61
62		enable-active-high;
63		gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
64		vin-supply = <&ppvar_sys>;
65	};
66
67	ppvarp_lcd: ppvarp-lcd {
68		compatible = "regulator-fixed";
69		regulator-name = "ppvarp_lcd";
70		pinctrl-names = "default";
71		pinctrl-0 = <&ppvarp_lcd_en>;
72
73		enable-active-high;
74		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
75		vin-supply = <&ppvar_sys>;
76	};
77
78	/* pp1800 children, sorted by name */
79	pp900_s3: pp900-s3 {
80		compatible = "regulator-fixed";
81		regulator-name = "pp900_s3";
82
83		/* EC turns on w/ pp900_s3_en; always on for AP */
84		regulator-always-on;
85		regulator-boot-on;
86		regulator-min-microvolt = <900000>;
87		regulator-max-microvolt = <900000>;
88
89		vin-supply = <&pp1800>;
90	};
91
92	/* EC turns on pp1800_s3_en */
93	pp1800_s3: pp1800 {
94	};
95
96	/* pp3300 children, sorted by name */
97	pp2800_cam: pp2800-avdd {
98		compatible = "regulator-fixed";
99		regulator-name = "pp2800_avdd";
100		pinctrl-names = "default";
101		pinctrl-0 = <&pp2800_cam_en>;
102
103		enable-active-high;
104		gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
105		startup-delay-us = <100>;
106		vin-supply = <&pp3300>;
107	};
108
109	/* EC turns on pp3300_s0_en */
110	pp3300_s0: pp3300 {
111	};
112
113	/* EC turns on pp3300_s3_en */
114	pp3300_s3: pp3300 {
115	};
116
117	/*
118	 * See b/66922012
119	 *
120	 * This is a hack to make sure the Bluetooth part of the QCA6174A
121	 * is reset at boot by toggling BT_EN. At boot BT_EN is first set
122	 * to low when the bt_3v3 regulator is registered (in disabled
123	 * state). The fake regulator is configured as a supply of the
124	 * wlan_3v3 regulator below. When wlan_3v3 is enabled early in
125	 * the boot process it also enables its supply regulator bt_3v3,
126	 * which changes BT_EN to high.
127	 */
128	bt_3v3: bt-3v3 {
129		compatible = "regulator-fixed";
130		regulator-name = "bt_3v3";
131		pinctrl-names = "default";
132		pinctrl-0 = <&bt_en_1v8_l>;
133
134		enable-active-high;
135		gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
136		vin-supply = <&pp3300_s3>;
137	};
138
139	wlan_3v3: wlan-3v3 {
140		compatible = "regulator-fixed";
141		regulator-name = "wlan_3v3";
142		pinctrl-names = "default";
143		pinctrl-0 = <&wlan_pd_1v8_l>;
144
145		/*
146		 * The WL_EN pin is driven low when the regulator is
147		 * registered, and transitions to high when the PCIe bus
148		 * is powered up.
149		 */
150		enable-active-high;
151		gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
152
153		/*
154		 * Require minimum 10ms from power-on (e.g., PD#) to init PCIe.
155		 * TODO (b/64444991): how long to assert PD#?
156		 */
157		regulator-enable-ramp-delay = <10000>;
158		/* See bt_3v3 hack above */
159		vin-supply = <&bt_3v3>;
160	};
161
162	backlight: backlight {
163		compatible = "pwm-backlight";
164		enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
165		pinctrl-names = "default";
166		pinctrl-0 = <&bl_en>;
167		pwms = <&pwm1 0 1000000 0>;
168		pwm-delay-us = <10000>;
169	};
170
171	dmic: dmic {
172		compatible = "dmic-codec";
173		dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
174		pinctrl-names = "default";
175		pinctrl-0 = <&dmic_en>;
176		wakeup-delay-ms = <250>;
177	};
178};
179
180/* pp900_s0 aliases */
181pp900_ddrpll_ap: &pp900_s0 {
182};
183pp900_pcie: &pp900_s0 {
184};
185pp900_usb: &pp900_s0 {
186};
187
188/* pp900_s3 aliases */
189pp900_emmcpll: &pp900_s3 {
190};
191
192/* EC turns on; alias for pp1800_s0 */
193pp1800_pcie: &pp1800_s0 {
194};
195
196/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */
197&ppvar_bigcpu {
198	ctrl-voltage-range = <800074 1299226>;
199	regulator-min-microvolt = <800074>;
200	regulator-max-microvolt = <1299226>;
201};
202
203&ppvar_bigcpu_pwm {
204	/* On scarlet ppvar big cpu use pwm3 */
205	pwms = <&pwm3 0 3337 0>;
206	regulator-min-microvolt = <800074>;
207	regulator-max-microvolt = <1299226>;
208};
209
210&ppvar_litcpu {
211	ctrl-voltage-range = <802122 1199620>;
212	regulator-min-microvolt = <802122>;
213	regulator-max-microvolt = <1199620>;
214};
215
216&ppvar_litcpu_pwm {
217	regulator-min-microvolt = <802122>;
218	regulator-max-microvolt = <1199620>;
219};
220
221&ppvar_gpu {
222	ctrl-voltage-range = <799600 1099600>;
223	regulator-min-microvolt = <799600>;
224	regulator-max-microvolt = <1099600>;
225};
226
227&ppvar_gpu_pwm {
228	regulator-min-microvolt = <799600>;
229	regulator-max-microvolt = <1099600>;
230};
231
232&ppvar_sd_card_io {
233	states = <1800000 0x0 3300000 0x1>;
234	regulator-max-microvolt = <3300000>;
235};
236
237&pp3000_sd_slot {
238	vin-supply = <&pp3300>;
239};
240
241ap_i2c_dig: &i2c2 {
242	status = "okay";
243
244	clock-frequency = <400000>;
245
246	/* These are relatively safe rise/fall times. */
247	i2c-scl-falling-time-ns = <50>;
248	i2c-scl-rising-time-ns = <300>;
249
250	digitizer: digitizer@9 {
251		compatible = "hid-over-i2c";
252		reg = <0x9>;
253		interrupt-parent = <&gpio1>;
254		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
255		hid-descr-addr = <0x1>;
256		pinctrl-names = "default";
257		pinctrl-0 = <&pen_int_odl &pen_reset_l>;
258	};
259};
260
261&ap_i2c_ts {
262	touchscreen: touchscreen@10 {
263		compatible = "elan,ekth3500";
264		reg = <0x10>;
265		interrupt-parent = <&gpio1>;
266		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
267		pinctrl-names = "default";
268		pinctrl-0 = <&touch_int_l &touch_reset_l>;
269		reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
270	};
271};
272
273camera: &i2c7 {
274	status = "okay";
275
276	clock-frequency = <400000>;
277
278	/* These are relatively safe rise/fall times; TODO: measure */
279	i2c-scl-falling-time-ns = <50>;
280	i2c-scl-rising-time-ns = <300>;
281
282	/* 24M mclk is shared between world and user cameras */
283	pinctrl-0 = <&i2c7_xfer &test_clkout1>;
284};
285
286&cdn_dp {
287	extcon = <&usbc_extcon0>;
288	phys = <&tcphy0_dp>;
289};
290
291&cpu_alert0 {
292	temperature = <66000>;
293};
294
295&cpu_alert1 {
296	temperature = <71000>;
297};
298
299&cros_ec {
300	interrupt-parent = <&gpio1>;
301	interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
302};
303
304&cru {
305	assigned-clocks =
306		<&cru PLL_GPLL>, <&cru PLL_CPLL>,
307		<&cru PLL_NPLL>,
308		<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
309		<&cru PCLK_PERIHP>,
310		<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
311		<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
312		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
313		<&cru ACLK_VIO>,
314		<&cru ACLK_GIC_PRE>,
315		<&cru PCLK_DDR>,
316		<&cru ACLK_HDCP>;
317	assigned-clock-rates =
318		<600000000>, <1600000000>,
319		<1000000000>,
320		<150000000>, <75000000>,
321		<37500000>,
322		<100000000>, <100000000>,
323		<50000000>, <800000000>,
324		<100000000>, <50000000>,
325		<400000000>,
326		<200000000>,
327		<200000000>,
328		<400000000>;
329};
330
331&gpio_keys {
332	pinctrl-names = "default";
333	pinctrl-0 = <&bt_host_wake_l>, <&pen_eject_odl>;
334
335	pen-insert {
336		label = "Pen Insert";
337		/* Insert = low, eject = high */
338		gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
339		linux,code = <SW_PEN_INSERTED>;
340		linux,input-type = <EV_SW>;
341		wakeup-source;
342	};
343};
344
345&i2c_tunnel {
346	google,remote-bus = <0>;
347};
348
349&io_domains {
350	bt656-supply = <&pp1800_s0>;		/* APIO2_VDD;  2a 2b */
351	audio-supply = <&pp1800_s0>;		/* APIO5_VDD;  3d 4a */
352	gpio1830-supply = <&pp1800_s0>;		/* APIO4_VDD;  4c 4d */
353};
354
355&max98357a {
356	sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
357};
358
359&mipi_dsi {
360	status = "okay";
361	clock-master;
362
363	ports {
364		mipi_out: port@1 {
365			reg = <1>;
366
367			mipi_out_panel: endpoint {
368				remote-endpoint = <&mipi_in_panel>;
369			};
370		};
371	};
372
373	mipi_panel: panel@0 {
374		/* 2 different panels are used, compatibles are in dts files */
375		reg = <0>;
376		backlight = <&backlight>;
377		enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
378		pinctrl-names = "default";
379		pinctrl-0 = <&display_rst_l>;
380
381		ports {
382			#address-cells = <1>;
383			#size-cells = <0>;
384
385			port@0 {
386				reg = <0>;
387
388				mipi_in_panel: endpoint {
389					remote-endpoint = <&mipi_out_panel>;
390				};
391			};
392
393			port@1 {
394				reg = <1>;
395
396				mipi1_in_panel: endpoint@1 {
397					remote-endpoint = <&mipi1_out_panel>;
398				};
399			};
400		};
401	};
402};
403
404&mipi_dsi1 {
405	status = "okay";
406
407	ports {
408		mipi1_out: port@1 {
409			reg = <1>;
410
411			mipi1_out_panel: endpoint {
412				remote-endpoint = <&mipi1_in_panel>;
413			};
414		};
415	};
416};
417
418&pcie0 {
419	ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
420
421	/* PERST# asserted in S3 */
422	pcie-reset-suspend = <1>;
423
424	vpcie3v3-supply = <&wlan_3v3>;
425	vpcie1v8-supply = <&pp1800_pcie>;
426};
427
428&sdmmc {
429	cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
430};
431
432&sound {
433	rockchip,codec = <&max98357a &dmic &codec &cdn_dp>;
434};
435
436&spi2 {
437	status = "okay";
438};
439
440&wake_on_bt {
441	gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
442};
443
444/* PINCTRL OVERRIDES */
445&ec_ap_int_l {
446	rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
447};
448
449&ap_fw_wp {
450	rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>;
451};
452
453&bl_en {
454	rockchip,pins = <4 21 RK_FUNC_GPIO &pcfg_pull_none>;
455};
456
457&bt_host_wake_l {
458	rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
459};
460
461&ec_ap_int_l {
462	rockchip,pins = <1 18 RK_FUNC_GPIO &pcfg_pull_up>;
463};
464
465&headset_int_l {
466	rockchip,pins = <1 23 RK_FUNC_GPIO &pcfg_pull_up>;
467};
468
469&i2s0_8ch_bus {
470	rockchip,pins =
471		<3 24 RK_FUNC_1 &pcfg_pull_none_6ma>,
472		<3 25 RK_FUNC_1 &pcfg_pull_none_6ma>,
473		<3 26 RK_FUNC_1 &pcfg_pull_none_6ma>,
474		<3 27 RK_FUNC_1 &pcfg_pull_none_6ma>,
475		<3 31 RK_FUNC_1 &pcfg_pull_none_6ma>,
476		<4 0 RK_FUNC_1 &pcfg_pull_none_6ma>;
477};
478
479/* there is no external pull up, so need to set this pin pull up */
480&sdmmc_cd_gpio {
481	rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_up>;
482};
483
484&sd_pwr_1800_sel {
485	rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_up>;
486};
487
488&sdmode_en {
489	rockchip,pins = <0 2 RK_FUNC_GPIO &pcfg_pull_down>;
490};
491
492&touch_reset_l {
493	rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_down>;
494};
495
496&touch_int_l {
497	rockchip,pins = <1 4 RK_FUNC_GPIO &pcfg_pull_down>;
498};
499
500&pinctrl {
501	pinctrl-0 = <
502		&ap_pwroff	/* AP will auto-assert this when in S3 */
503		&clk_32k	/* This pin is always 32k on gru boards */
504		&wlan_rf_kill_1v8_l
505	>;
506
507	pcfg_pull_none_6ma: pcfg-pull-none-6ma {
508		bias-disable;
509		drive-strength = <6>;
510	};
511
512	camera {
513		pp1250_cam_en: pp1250-dvdd {
514			rockchip,pins = <2 4 RK_FUNC_GPIO &pcfg_pull_none>;
515		};
516
517		pp2800_cam_en: pp2800-avdd {
518			rockchip,pins = <2 24 RK_FUNC_GPIO &pcfg_pull_none>;
519		};
520
521		ucam_rst: ucam_rst {
522			rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
523		};
524
525		wcam_rst: wcam_rst {
526			rockchip,pins = <2 5 RK_FUNC_GPIO &pcfg_pull_none>;
527		};
528	};
529
530	digitizer {
531		pen_int_odl: pen-int-odl {
532			rockchip,pins = <1 0 RK_FUNC_GPIO &pcfg_pull_up>;
533		};
534
535		pen_reset_l: pen-reset-l {
536			rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
537		};
538	};
539
540	discrete-regulators {
541		display_rst_l: display-rst-l {
542			rockchip,pins = <4 25 RK_FUNC_GPIO &pcfg_pull_down>;
543		};
544
545		ppvarp_lcd_en: ppvarp-lcd-en {
546			rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
547		};
548
549		ppvarn_lcd_en: ppvarn-lcd-en {
550			rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
551		};
552	};
553
554	dmic {
555		dmic_en: dmic-en {
556			rockchip,pins = <4 3 RK_FUNC_GPIO &pcfg_pull_none>;
557		};
558	};
559
560	pen {
561		pen_eject_odl: pen-eject-odl {
562			rockchip,pins = <1 1 RK_FUNC_GPIO &pcfg_pull_up>;
563		};
564	};
565
566	tpm {
567		h1_int_od_l: h1-int-od-l {
568			rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_up>;
569		};
570	};
571};
572
573&wifi {
574	bt_en_1v8_l: bt-en-1v8-l {
575		rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>;
576	};
577
578	wlan_pd_1v8_l: wlan-pd-1v8-l {
579		rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
580	};
581
582	/* Default pull-up, but just to be clear */
583	wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l {
584		rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
585	};
586
587	wifi_perst_l: wifi-perst-l {
588		rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
589	};
590
591	wlan_host_wake_l: wlan-host-wake-l {
592		rockchip,pins = <1 3 RK_FUNC_GPIO &pcfg_pull_up>;
593	};
594};
595