1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6/dts-v1/;
7#include <dt-bindings/pwm/pwm.h>
8#include "rk3399.dtsi"
9
10/ {
11	model = "Rockchip RK3399 Evaluation Board";
12	compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
13		     "google,rk3399evb-rev2";
14
15	backlight: backlight {
16		compatible = "pwm-backlight";
17		brightness-levels = <
18			  0   1   2   3   4   5   6   7
19			  8   9  10  11  12  13  14  15
20			 16  17  18  19  20  21  22  23
21			 24  25  26  27  28  29  30  31
22			 32  33  34  35  36  37  38  39
23			 40  41  42  43  44  45  46  47
24			 48  49  50  51  52  53  54  55
25			 56  57  58  59  60  61  62  63
26			 64  65  66  67  68  69  70  71
27			 72  73  74  75  76  77  78  79
28			 80  81  82  83  84  85  86  87
29			 88  89  90  91  92  93  94  95
30			 96  97  98  99 100 101 102 103
31			104 105 106 107 108 109 110 111
32			112 113 114 115 116 117 118 119
33			120 121 122 123 124 125 126 127
34			128 129 130 131 132 133 134 135
35			136 137 138 139 140 141 142 143
36			144 145 146 147 148 149 150 151
37			152 153 154 155 156 157 158 159
38			160 161 162 163 164 165 166 167
39			168 169 170 171 172 173 174 175
40			176 177 178 179 180 181 182 183
41			184 185 186 187 188 189 190 191
42			192 193 194 195 196 197 198 199
43			200 201 202 203 204 205 206 207
44			208 209 210 211 212 213 214 215
45			216 217 218 219 220 221 222 223
46			224 225 226 227 228 229 230 231
47			232 233 234 235 236 237 238 239
48			240 241 242 243 244 245 246 247
49			248 249 250 251 252 253 254 255>;
50		default-brightness-level = <200>;
51		enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
52		pwms = <&pwm0 0 25000 0>;
53	};
54
55	clkin_gmac: external-gmac-clock {
56		compatible = "fixed-clock";
57		clock-frequency = <125000000>;
58		clock-output-names = "clkin_gmac";
59		#clock-cells = <0>;
60	};
61
62	vdd_center: vdd-center {
63		compatible = "pwm-regulator";
64		pwms = <&pwm3 0 25000 0>;
65		regulator-name = "vdd_center";
66		regulator-min-microvolt = <800000>;
67		regulator-max-microvolt = <1400000>;
68		regulator-always-on;
69		regulator-boot-on;
70		status = "okay";
71	};
72
73	vcc3v3_sys: vcc3v3-sys {
74		compatible = "regulator-fixed";
75		regulator-name = "vcc3v3_sys";
76		regulator-always-on;
77		regulator-boot-on;
78		regulator-min-microvolt = <3300000>;
79		regulator-max-microvolt = <3300000>;
80	};
81
82	vcc5v0_sys: vcc5v0-sys {
83		compatible = "regulator-fixed";
84		regulator-name = "vcc5v0_sys";
85		regulator-always-on;
86		regulator-boot-on;
87		regulator-min-microvolt = <5000000>;
88		regulator-max-microvolt = <5000000>;
89	};
90
91	vcc5v0_host: vcc5v0-host-regulator {
92		compatible = "regulator-fixed";
93		enable-active-high;
94		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
95		pinctrl-names = "default";
96		pinctrl-0 = <&vcc5v0_host_en>;
97		regulator-name = "vcc5v0_host";
98		vin-supply = <&vcc5v0_sys>;
99	};
100
101	vcc_phy: vcc-phy-regulator {
102		compatible = "regulator-fixed";
103		regulator-name = "vcc_phy";
104		regulator-always-on;
105		regulator-boot-on;
106	};
107
108	vcc_phy: vcc-phy-regulator {
109		compatible = "regulator-fixed";
110		regulator-name = "vcc_phy";
111		regulator-always-on;
112		regulator-boot-on;
113	};
114
115};
116
117&emmc_phy {
118	status = "okay";
119};
120
121&gmac {
122	assigned-clocks = <&cru SCLK_RMII_SRC>;
123	assigned-clock-parents = <&clkin_gmac>;
124	clock_in_out = "input";
125	phy-supply = <&vcc_phy>;
126	phy-mode = "rgmii";
127	pinctrl-names = "default";
128	pinctrl-0 = <&rgmii_pins>;
129	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
130	snps,reset-active-low;
131	snps,reset-delays-us = <0 10000 50000>;
132	tx_delay = <0x28>;
133	rx_delay = <0x11>;
134	status = "okay";
135};
136
137&pwm0 {
138	status = "okay";
139};
140
141&pwm2 {
142	status = "okay";
143};
144
145&pwm3 {
146	status = "okay";
147};
148
149&sdhci {
150	bus-width = <8>;
151	mmc-hs400-1_8v;
152	mmc-hs400-enhanced-strobe;
153	non-removable;
154	status = "okay";
155};
156
157&pcie_phy {
158	status = "disabled";
159};
160
161&pcie0 {
162	ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
163	num-lanes = <4>;
164	pinctrl-names = "default";
165	pinctrl-0 = <&pcie_clkreqn_cpm>;
166	status = "disabled";
167};
168
169&u2phy0 {
170	status = "okay";
171};
172
173&u2phy0_host {
174	phy-supply = <&vcc5v0_host>;
175	status = "okay";
176};
177
178&u2phy1 {
179	status = "okay";
180};
181
182&u2phy1_host {
183	phy-supply = <&vcc5v0_host>;
184	status = "okay";
185};
186
187&uart2 {
188	status = "okay";
189};
190
191&usb_host0_ehci {
192	status = "okay";
193};
194
195&usb_host0_ohci {
196	status = "okay";
197};
198
199&usb_host1_ehci {
200	status = "okay";
201};
202
203&usb_host1_ohci {
204	status = "okay";
205};
206
207&pinctrl {
208	pmic {
209		pmic_int_l: pmic-int-l {
210			rockchip,pins =
211				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
212		};
213	};
214
215	usb2 {
216		vcc5v0_host_en: vcc5v0-host-en {
217			rockchip,pins =
218				<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
219		};
220	};
221};
222