17053e06bSLiang Chen// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 27053e06bSLiang Chen/* 37053e06bSLiang Chen * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 47053e06bSLiang Chen */ 57053e06bSLiang Chen 67053e06bSLiang Chen#include <dt-bindings/clock/px30-cru.h> 77053e06bSLiang Chen#include <dt-bindings/gpio/gpio.h> 87053e06bSLiang Chen#include <dt-bindings/interrupt-controller/arm-gic.h> 97053e06bSLiang Chen#include <dt-bindings/interrupt-controller/irq.h> 107053e06bSLiang Chen#include <dt-bindings/pinctrl/rockchip.h> 117053e06bSLiang Chen#include <dt-bindings/power/px30-power.h> 127053e06bSLiang Chen#include <dt-bindings/soc/rockchip,boot-mode.h> 13023115cdSHeiko Stuebner#include <dt-bindings/thermal/thermal.h> 147053e06bSLiang Chen 157053e06bSLiang Chen/ { 167053e06bSLiang Chen compatible = "rockchip,px30"; 177053e06bSLiang Chen 187053e06bSLiang Chen interrupt-parent = <&gic>; 197053e06bSLiang Chen #address-cells = <2>; 207053e06bSLiang Chen #size-cells = <2>; 217053e06bSLiang Chen 227053e06bSLiang Chen aliases { 237053e06bSLiang Chen ethernet0 = &gmac; 247053e06bSLiang Chen i2c0 = &i2c0; 257053e06bSLiang Chen i2c1 = &i2c1; 267053e06bSLiang Chen i2c2 = &i2c2; 277053e06bSLiang Chen i2c3 = &i2c3; 287053e06bSLiang Chen serial0 = &uart0; 297053e06bSLiang Chen serial1 = &uart1; 307053e06bSLiang Chen serial2 = &uart2; 317053e06bSLiang Chen serial3 = &uart3; 327053e06bSLiang Chen serial4 = &uart4; 337053e06bSLiang Chen serial5 = &uart5; 347053e06bSLiang Chen spi0 = &spi0; 357053e06bSLiang Chen spi1 = &spi1; 367053e06bSLiang Chen }; 377053e06bSLiang Chen 387053e06bSLiang Chen cpus { 397053e06bSLiang Chen #address-cells = <2>; 407053e06bSLiang Chen #size-cells = <0>; 417053e06bSLiang Chen 427053e06bSLiang Chen cpu0: cpu@0 { 437053e06bSLiang Chen device_type = "cpu"; 4431af04cdSRob Herring compatible = "arm,cortex-a35"; 457053e06bSLiang Chen reg = <0x0 0x0>; 467053e06bSLiang Chen enable-method = "psci"; 477053e06bSLiang Chen clocks = <&cru ARMCLK>; 487053e06bSLiang Chen #cooling-cells = <2>; 497053e06bSLiang Chen cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 507053e06bSLiang Chen dynamic-power-coefficient = <90>; 517053e06bSLiang Chen operating-points-v2 = <&cpu0_opp_table>; 527053e06bSLiang Chen }; 537053e06bSLiang Chen 547053e06bSLiang Chen cpu1: cpu@1 { 557053e06bSLiang Chen device_type = "cpu"; 5631af04cdSRob Herring compatible = "arm,cortex-a35"; 577053e06bSLiang Chen reg = <0x0 0x1>; 587053e06bSLiang Chen enable-method = "psci"; 597053e06bSLiang Chen clocks = <&cru ARMCLK>; 607053e06bSLiang Chen #cooling-cells = <2>; 617053e06bSLiang Chen cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 627053e06bSLiang Chen dynamic-power-coefficient = <90>; 637053e06bSLiang Chen operating-points-v2 = <&cpu0_opp_table>; 647053e06bSLiang Chen }; 657053e06bSLiang Chen 667053e06bSLiang Chen cpu2: cpu@2 { 677053e06bSLiang Chen device_type = "cpu"; 6831af04cdSRob Herring compatible = "arm,cortex-a35"; 697053e06bSLiang Chen reg = <0x0 0x2>; 707053e06bSLiang Chen enable-method = "psci"; 717053e06bSLiang Chen clocks = <&cru ARMCLK>; 727053e06bSLiang Chen #cooling-cells = <2>; 737053e06bSLiang Chen cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 747053e06bSLiang Chen dynamic-power-coefficient = <90>; 757053e06bSLiang Chen operating-points-v2 = <&cpu0_opp_table>; 767053e06bSLiang Chen }; 777053e06bSLiang Chen 787053e06bSLiang Chen cpu3: cpu@3 { 797053e06bSLiang Chen device_type = "cpu"; 8031af04cdSRob Herring compatible = "arm,cortex-a35"; 817053e06bSLiang Chen reg = <0x0 0x3>; 827053e06bSLiang Chen enable-method = "psci"; 837053e06bSLiang Chen clocks = <&cru ARMCLK>; 847053e06bSLiang Chen #cooling-cells = <2>; 857053e06bSLiang Chen cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 867053e06bSLiang Chen dynamic-power-coefficient = <90>; 877053e06bSLiang Chen operating-points-v2 = <&cpu0_opp_table>; 887053e06bSLiang Chen }; 897053e06bSLiang Chen 907053e06bSLiang Chen idle-states { 917053e06bSLiang Chen entry-method = "psci"; 927053e06bSLiang Chen 937053e06bSLiang Chen CPU_SLEEP: cpu-sleep { 947053e06bSLiang Chen compatible = "arm,idle-state"; 957053e06bSLiang Chen local-timer-stop; 967053e06bSLiang Chen arm,psci-suspend-param = <0x0010000>; 977053e06bSLiang Chen entry-latency-us = <120>; 987053e06bSLiang Chen exit-latency-us = <250>; 997053e06bSLiang Chen min-residency-us = <900>; 1007053e06bSLiang Chen }; 1017053e06bSLiang Chen 1027053e06bSLiang Chen CLUSTER_SLEEP: cluster-sleep { 1037053e06bSLiang Chen compatible = "arm,idle-state"; 1047053e06bSLiang Chen local-timer-stop; 1057053e06bSLiang Chen arm,psci-suspend-param = <0x1010000>; 1067053e06bSLiang Chen entry-latency-us = <400>; 1077053e06bSLiang Chen exit-latency-us = <500>; 1087053e06bSLiang Chen min-residency-us = <2000>; 1097053e06bSLiang Chen }; 1107053e06bSLiang Chen }; 1117053e06bSLiang Chen }; 1127053e06bSLiang Chen 1137053e06bSLiang Chen cpu0_opp_table: cpu0-opp-table { 1147053e06bSLiang Chen compatible = "operating-points-v2"; 1157053e06bSLiang Chen opp-shared; 1167053e06bSLiang Chen 1177053e06bSLiang Chen opp-600000000 { 1187053e06bSLiang Chen opp-hz = /bits/ 64 <600000000>; 1197053e06bSLiang Chen opp-microvolt = <950000 950000 1350000>; 1207053e06bSLiang Chen clock-latency-ns = <40000>; 1218554723eSHeiko Stuebner opp-suspend; 1227053e06bSLiang Chen }; 1237053e06bSLiang Chen opp-816000000 { 1247053e06bSLiang Chen opp-hz = /bits/ 64 <816000000>; 1257053e06bSLiang Chen opp-microvolt = <1050000 1050000 1350000>; 1267053e06bSLiang Chen clock-latency-ns = <40000>; 1277053e06bSLiang Chen }; 1287053e06bSLiang Chen opp-1008000000 { 1297053e06bSLiang Chen opp-hz = /bits/ 64 <1008000000>; 1307053e06bSLiang Chen opp-microvolt = <1175000 1175000 1350000>; 1317053e06bSLiang Chen clock-latency-ns = <40000>; 1327053e06bSLiang Chen }; 1337053e06bSLiang Chen opp-1200000000 { 1347053e06bSLiang Chen opp-hz = /bits/ 64 <1200000000>; 1357053e06bSLiang Chen opp-microvolt = <1300000 1300000 1350000>; 1367053e06bSLiang Chen clock-latency-ns = <40000>; 1377053e06bSLiang Chen }; 1387053e06bSLiang Chen opp-1296000000 { 1397053e06bSLiang Chen opp-hz = /bits/ 64 <1296000000>; 1407053e06bSLiang Chen opp-microvolt = <1350000 1350000 1350000>; 1417053e06bSLiang Chen clock-latency-ns = <40000>; 1427053e06bSLiang Chen }; 1437053e06bSLiang Chen }; 1447053e06bSLiang Chen 1457053e06bSLiang Chen arm-pmu { 1467053e06bSLiang Chen compatible = "arm,cortex-a53-pmu"; 1477053e06bSLiang Chen interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1487053e06bSLiang Chen <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1497053e06bSLiang Chen <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1507053e06bSLiang Chen <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1517053e06bSLiang Chen interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1527053e06bSLiang Chen }; 1537053e06bSLiang Chen 1547053e06bSLiang Chen display_subsystem: display-subsystem { 1557053e06bSLiang Chen compatible = "rockchip,display-subsystem"; 156967c1464SSandy Huang ports = <&vopb_out>, <&vopl_out>; 1577053e06bSLiang Chen status = "disabled"; 1587053e06bSLiang Chen }; 1597053e06bSLiang Chen 1607053e06bSLiang Chen gmac_clkin: external-gmac-clock { 1617053e06bSLiang Chen compatible = "fixed-clock"; 1627053e06bSLiang Chen clock-frequency = <50000000>; 1637053e06bSLiang Chen clock-output-names = "gmac_clkin"; 1647053e06bSLiang Chen #clock-cells = <0>; 1657053e06bSLiang Chen }; 1667053e06bSLiang Chen 1677053e06bSLiang Chen psci { 1687053e06bSLiang Chen compatible = "arm,psci-1.0"; 1697053e06bSLiang Chen method = "smc"; 1707053e06bSLiang Chen }; 1717053e06bSLiang Chen 1727053e06bSLiang Chen timer { 1737053e06bSLiang Chen compatible = "arm,armv8-timer"; 1747053e06bSLiang Chen interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1757053e06bSLiang Chen <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1767053e06bSLiang Chen <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1777053e06bSLiang Chen <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1787053e06bSLiang Chen }; 1797053e06bSLiang Chen 180023115cdSHeiko Stuebner thermal_zones: thermal-zones { 181023115cdSHeiko Stuebner soc_thermal: soc-thermal { 182023115cdSHeiko Stuebner polling-delay-passive = <20>; 183023115cdSHeiko Stuebner polling-delay = <1000>; 184023115cdSHeiko Stuebner sustainable-power = <750>; 185023115cdSHeiko Stuebner thermal-sensors = <&tsadc 0>; 186023115cdSHeiko Stuebner 187023115cdSHeiko Stuebner trips { 188023115cdSHeiko Stuebner threshold: trip-point-0 { 189023115cdSHeiko Stuebner temperature = <70000>; 190023115cdSHeiko Stuebner hysteresis = <2000>; 191023115cdSHeiko Stuebner type = "passive"; 192023115cdSHeiko Stuebner }; 193023115cdSHeiko Stuebner 194023115cdSHeiko Stuebner target: trip-point-1 { 195023115cdSHeiko Stuebner temperature = <85000>; 196023115cdSHeiko Stuebner hysteresis = <2000>; 197023115cdSHeiko Stuebner type = "passive"; 198023115cdSHeiko Stuebner }; 199023115cdSHeiko Stuebner 200023115cdSHeiko Stuebner soc_crit: soc-crit { 201023115cdSHeiko Stuebner temperature = <115000>; 202023115cdSHeiko Stuebner hysteresis = <2000>; 203023115cdSHeiko Stuebner type = "critical"; 204023115cdSHeiko Stuebner }; 205023115cdSHeiko Stuebner }; 206023115cdSHeiko Stuebner 207023115cdSHeiko Stuebner cooling-maps { 208023115cdSHeiko Stuebner map0 { 209023115cdSHeiko Stuebner trip = <&target>; 210023115cdSHeiko Stuebner cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211023115cdSHeiko Stuebner contribution = <4096>; 212023115cdSHeiko Stuebner }; 213a07f34a0SHeiko Stuebner 214a07f34a0SHeiko Stuebner map1 { 215a07f34a0SHeiko Stuebner trip = <&target>; 216a07f34a0SHeiko Stuebner cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217a07f34a0SHeiko Stuebner contribution = <4096>; 218a07f34a0SHeiko Stuebner }; 219023115cdSHeiko Stuebner }; 220023115cdSHeiko Stuebner }; 221023115cdSHeiko Stuebner 222023115cdSHeiko Stuebner gpu_thermal: gpu-thermal { 223023115cdSHeiko Stuebner polling-delay-passive = <100>; /* milliseconds */ 224023115cdSHeiko Stuebner polling-delay = <1000>; /* milliseconds */ 225023115cdSHeiko Stuebner thermal-sensors = <&tsadc 1>; 226023115cdSHeiko Stuebner }; 227023115cdSHeiko Stuebner }; 228023115cdSHeiko Stuebner 2297053e06bSLiang Chen xin24m: xin24m { 2307053e06bSLiang Chen compatible = "fixed-clock"; 2317053e06bSLiang Chen #clock-cells = <0>; 2327053e06bSLiang Chen clock-frequency = <24000000>; 2337053e06bSLiang Chen clock-output-names = "xin24m"; 2347053e06bSLiang Chen }; 2357053e06bSLiang Chen 2367053e06bSLiang Chen pmu: power-management@ff000000 { 2377053e06bSLiang Chen compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 2387053e06bSLiang Chen reg = <0x0 0xff000000 0x0 0x1000>; 2397053e06bSLiang Chen 2407053e06bSLiang Chen power: power-controller { 2417053e06bSLiang Chen compatible = "rockchip,px30-power-controller"; 2427053e06bSLiang Chen #power-domain-cells = <1>; 2437053e06bSLiang Chen #address-cells = <1>; 2447053e06bSLiang Chen #size-cells = <0>; 2457053e06bSLiang Chen 2467053e06bSLiang Chen /* These power domains are grouped by VD_LOGIC */ 2477053e06bSLiang Chen pd_usb@PX30_PD_USB { 2487053e06bSLiang Chen reg = <PX30_PD_USB>; 2497053e06bSLiang Chen clocks = <&cru HCLK_HOST>, 2507053e06bSLiang Chen <&cru HCLK_OTG>, 2517053e06bSLiang Chen <&cru SCLK_OTG_ADP>; 2527053e06bSLiang Chen pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 2537053e06bSLiang Chen }; 2547053e06bSLiang Chen pd_sdcard@PX30_PD_SDCARD { 2557053e06bSLiang Chen reg = <PX30_PD_SDCARD>; 2567053e06bSLiang Chen clocks = <&cru HCLK_SDMMC>, 2577053e06bSLiang Chen <&cru SCLK_SDMMC>; 2587053e06bSLiang Chen pm_qos = <&qos_sdmmc>; 2597053e06bSLiang Chen }; 2607053e06bSLiang Chen pd_gmac@PX30_PD_GMAC { 2617053e06bSLiang Chen reg = <PX30_PD_GMAC>; 2627053e06bSLiang Chen clocks = <&cru ACLK_GMAC>, 2637053e06bSLiang Chen <&cru PCLK_GMAC>, 2647053e06bSLiang Chen <&cru SCLK_MAC_REF>, 2657053e06bSLiang Chen <&cru SCLK_GMAC_RX_TX>; 2667053e06bSLiang Chen pm_qos = <&qos_gmac>; 2677053e06bSLiang Chen }; 2687053e06bSLiang Chen pd_mmc_nand@PX30_PD_MMC_NAND { 2697053e06bSLiang Chen reg = <PX30_PD_MMC_NAND>; 2707053e06bSLiang Chen clocks = <&cru HCLK_NANDC>, 2717053e06bSLiang Chen <&cru HCLK_EMMC>, 2727053e06bSLiang Chen <&cru HCLK_SDIO>, 2737053e06bSLiang Chen <&cru HCLK_SFC>, 2747053e06bSLiang Chen <&cru SCLK_EMMC>, 2757053e06bSLiang Chen <&cru SCLK_NANDC>, 2767053e06bSLiang Chen <&cru SCLK_SDIO>, 2777053e06bSLiang Chen <&cru SCLK_SFC>; 2787053e06bSLiang Chen pm_qos = <&qos_emmc>, <&qos_nand>, 2797053e06bSLiang Chen <&qos_sdio>, <&qos_sfc>; 2807053e06bSLiang Chen }; 2817053e06bSLiang Chen pd_vpu@PX30_PD_VPU { 2827053e06bSLiang Chen reg = <PX30_PD_VPU>; 2837053e06bSLiang Chen clocks = <&cru ACLK_VPU>, 2847053e06bSLiang Chen <&cru HCLK_VPU>, 2857053e06bSLiang Chen <&cru SCLK_CORE_VPU>; 2867053e06bSLiang Chen pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 2877053e06bSLiang Chen }; 2887053e06bSLiang Chen pd_vo@PX30_PD_VO { 2897053e06bSLiang Chen reg = <PX30_PD_VO>; 2907053e06bSLiang Chen clocks = <&cru ACLK_RGA>, 2917053e06bSLiang Chen <&cru ACLK_VOPB>, 2927053e06bSLiang Chen <&cru ACLK_VOPL>, 2937053e06bSLiang Chen <&cru DCLK_VOPB>, 2947053e06bSLiang Chen <&cru DCLK_VOPL>, 2957053e06bSLiang Chen <&cru HCLK_RGA>, 2967053e06bSLiang Chen <&cru HCLK_VOPB>, 2977053e06bSLiang Chen <&cru HCLK_VOPL>, 2987053e06bSLiang Chen <&cru PCLK_MIPI_DSI>, 2997053e06bSLiang Chen <&cru SCLK_RGA_CORE>, 3007053e06bSLiang Chen <&cru SCLK_VOPB_PWM>; 3017053e06bSLiang Chen pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 3027053e06bSLiang Chen <&qos_vop_m0>, <&qos_vop_m1>; 3037053e06bSLiang Chen }; 3047053e06bSLiang Chen pd_vi@PX30_PD_VI { 3057053e06bSLiang Chen reg = <PX30_PD_VI>; 3067053e06bSLiang Chen clocks = <&cru ACLK_CIF>, 3077053e06bSLiang Chen <&cru ACLK_ISP>, 3087053e06bSLiang Chen <&cru HCLK_CIF>, 3097053e06bSLiang Chen <&cru HCLK_ISP>, 3107053e06bSLiang Chen <&cru SCLK_ISP>; 3117053e06bSLiang Chen pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 3127053e06bSLiang Chen <&qos_isp_wr>, <&qos_isp_m1>, 3137053e06bSLiang Chen <&qos_vip>; 3147053e06bSLiang Chen }; 3157053e06bSLiang Chen pd_gpu@PX30_PD_GPU { 3167053e06bSLiang Chen reg = <PX30_PD_GPU>; 3177053e06bSLiang Chen clocks = <&cru SCLK_GPU>; 3187053e06bSLiang Chen pm_qos = <&qos_gpu>; 3197053e06bSLiang Chen }; 3207053e06bSLiang Chen }; 3217053e06bSLiang Chen }; 3227053e06bSLiang Chen 3237053e06bSLiang Chen pmugrf: syscon@ff010000 { 3247053e06bSLiang Chen compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 3257053e06bSLiang Chen reg = <0x0 0xff010000 0x0 0x1000>; 3267053e06bSLiang Chen #address-cells = <1>; 3277053e06bSLiang Chen #size-cells = <1>; 3287053e06bSLiang Chen 3297053e06bSLiang Chen pmu_io_domains: io-domains { 3307053e06bSLiang Chen compatible = "rockchip,px30-pmu-io-voltage-domain"; 3317053e06bSLiang Chen status = "disabled"; 3327053e06bSLiang Chen }; 3337053e06bSLiang Chen 3347053e06bSLiang Chen reboot-mode { 3357053e06bSLiang Chen compatible = "syscon-reboot-mode"; 3367053e06bSLiang Chen offset = <0x200>; 3377053e06bSLiang Chen mode-bootloader = <BOOT_BL_DOWNLOAD>; 3387053e06bSLiang Chen mode-fastboot = <BOOT_FASTBOOT>; 3397053e06bSLiang Chen mode-loader = <BOOT_BL_DOWNLOAD>; 3407053e06bSLiang Chen mode-normal = <BOOT_NORMAL>; 3417053e06bSLiang Chen mode-recovery = <BOOT_RECOVERY>; 3427053e06bSLiang Chen }; 3437053e06bSLiang Chen }; 3447053e06bSLiang Chen 3457053e06bSLiang Chen uart0: serial@ff030000 { 3467053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 3477053e06bSLiang Chen reg = <0x0 0xff030000 0x0 0x100>; 3487053e06bSLiang Chen interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 3497053e06bSLiang Chen clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 3507053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 3517053e06bSLiang Chen dmas = <&dmac 0>, <&dmac 1>; 3527053e06bSLiang Chen dma-names = "tx", "rx"; 3537053e06bSLiang Chen reg-shift = <2>; 3547053e06bSLiang Chen reg-io-width = <4>; 3557053e06bSLiang Chen pinctrl-names = "default"; 3567053e06bSLiang Chen pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 3577053e06bSLiang Chen status = "disabled"; 3587053e06bSLiang Chen }; 3597053e06bSLiang Chen 3607053e06bSLiang Chen i2s1_2ch: i2s@ff070000 { 3617053e06bSLiang Chen compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 3627053e06bSLiang Chen reg = <0x0 0xff070000 0x0 0x1000>; 3637053e06bSLiang Chen interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3647053e06bSLiang Chen clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 3657053e06bSLiang Chen clock-names = "i2s_clk", "i2s_hclk"; 3667053e06bSLiang Chen dmas = <&dmac 18>, <&dmac 19>; 3677053e06bSLiang Chen dma-names = "tx", "rx"; 3687053e06bSLiang Chen pinctrl-names = "default"; 3697053e06bSLiang Chen pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 3707053e06bSLiang Chen &i2s1_2ch_sdi &i2s1_2ch_sdo>; 3717053e06bSLiang Chen #sound-dai-cells = <0>; 3727053e06bSLiang Chen status = "disabled"; 3737053e06bSLiang Chen }; 3747053e06bSLiang Chen 3757053e06bSLiang Chen i2s2_2ch: i2s@ff080000 { 3767053e06bSLiang Chen compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 3777053e06bSLiang Chen reg = <0x0 0xff080000 0x0 0x1000>; 3787053e06bSLiang Chen interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3797053e06bSLiang Chen clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 3807053e06bSLiang Chen clock-names = "i2s_clk", "i2s_hclk"; 3817053e06bSLiang Chen dmas = <&dmac 20>, <&dmac 21>; 3827053e06bSLiang Chen dma-names = "tx", "rx"; 3837053e06bSLiang Chen pinctrl-names = "default"; 3847053e06bSLiang Chen pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 3857053e06bSLiang Chen &i2s2_2ch_sdi &i2s2_2ch_sdo>; 3867053e06bSLiang Chen #sound-dai-cells = <0>; 3877053e06bSLiang Chen status = "disabled"; 3887053e06bSLiang Chen }; 3897053e06bSLiang Chen 3907053e06bSLiang Chen gic: interrupt-controller@ff131000 { 3917053e06bSLiang Chen compatible = "arm,gic-400"; 3927053e06bSLiang Chen #interrupt-cells = <3>; 3937053e06bSLiang Chen #address-cells = <0>; 3947053e06bSLiang Chen interrupt-controller; 3957053e06bSLiang Chen reg = <0x0 0xff131000 0 0x1000>, 3967053e06bSLiang Chen <0x0 0xff132000 0 0x2000>, 3977053e06bSLiang Chen <0x0 0xff134000 0 0x2000>, 3987053e06bSLiang Chen <0x0 0xff136000 0 0x2000>; 3997053e06bSLiang Chen interrupts = <GIC_PPI 9 4007053e06bSLiang Chen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 4017053e06bSLiang Chen }; 4027053e06bSLiang Chen 4037053e06bSLiang Chen grf: syscon@ff140000 { 4047053e06bSLiang Chen compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 4057053e06bSLiang Chen reg = <0x0 0xff140000 0x0 0x1000>; 4067053e06bSLiang Chen #address-cells = <1>; 4077053e06bSLiang Chen #size-cells = <1>; 4087053e06bSLiang Chen 4097053e06bSLiang Chen io_domains: io-domains { 4107053e06bSLiang Chen compatible = "rockchip,px30-io-voltage-domain"; 4117053e06bSLiang Chen status = "disabled"; 4127053e06bSLiang Chen }; 413dbb6f778SMiquel Raynal 414dbb6f778SMiquel Raynal lvds: lvds { 415dbb6f778SMiquel Raynal compatible = "rockchip,px30-lvds"; 416dbb6f778SMiquel Raynal phys = <&dsi_dphy>; 417dbb6f778SMiquel Raynal phy-names = "dphy"; 418dbb6f778SMiquel Raynal rockchip,grf = <&grf>; 419dbb6f778SMiquel Raynal rockchip,output = "lvds"; 420dbb6f778SMiquel Raynal status = "disabled"; 421dbb6f778SMiquel Raynal 422186444c1SHeiko Stuebner ports { 423186444c1SHeiko Stuebner #address-cells = <1>; 424186444c1SHeiko Stuebner #size-cells = <0>; 425186444c1SHeiko Stuebner 426dbb6f778SMiquel Raynal port@0 { 427dbb6f778SMiquel Raynal reg = <0>; 428dbb6f778SMiquel Raynal #address-cells = <1>; 429dbb6f778SMiquel Raynal #size-cells = <0>; 430dbb6f778SMiquel Raynal 431dbb6f778SMiquel Raynal lvds_vopb_in: endpoint@0 { 432dbb6f778SMiquel Raynal reg = <0>; 433dbb6f778SMiquel Raynal remote-endpoint = <&vopb_out_lvds>; 434dbb6f778SMiquel Raynal }; 435dbb6f778SMiquel Raynal 436dbb6f778SMiquel Raynal lvds_vopl_in: endpoint@1 { 437dbb6f778SMiquel Raynal reg = <1>; 438dbb6f778SMiquel Raynal remote-endpoint = <&vopl_out_lvds>; 439dbb6f778SMiquel Raynal }; 440dbb6f778SMiquel Raynal }; 441dbb6f778SMiquel Raynal }; 4427053e06bSLiang Chen }; 443186444c1SHeiko Stuebner }; 4447053e06bSLiang Chen 4457053e06bSLiang Chen uart1: serial@ff158000 { 4467053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 4477053e06bSLiang Chen reg = <0x0 0xff158000 0x0 0x100>; 4487053e06bSLiang Chen interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 4497053e06bSLiang Chen clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 4507053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 4517053e06bSLiang Chen dmas = <&dmac 2>, <&dmac 3>; 4527053e06bSLiang Chen dma-names = "tx", "rx"; 4537053e06bSLiang Chen reg-shift = <2>; 4547053e06bSLiang Chen reg-io-width = <4>; 4557053e06bSLiang Chen pinctrl-names = "default"; 4567053e06bSLiang Chen pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 4577053e06bSLiang Chen status = "disabled"; 4587053e06bSLiang Chen }; 4597053e06bSLiang Chen 4607053e06bSLiang Chen uart2: serial@ff160000 { 4617053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 4627053e06bSLiang Chen reg = <0x0 0xff160000 0x0 0x100>; 4637053e06bSLiang Chen interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 4647053e06bSLiang Chen clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 4657053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 4667053e06bSLiang Chen dmas = <&dmac 4>, <&dmac 5>; 4677053e06bSLiang Chen dma-names = "tx", "rx"; 4687053e06bSLiang Chen reg-shift = <2>; 4697053e06bSLiang Chen reg-io-width = <4>; 4707053e06bSLiang Chen pinctrl-names = "default"; 4717053e06bSLiang Chen pinctrl-0 = <&uart2m0_xfer>; 4727053e06bSLiang Chen status = "disabled"; 4737053e06bSLiang Chen }; 4747053e06bSLiang Chen 4757053e06bSLiang Chen uart3: serial@ff168000 { 4767053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 4777053e06bSLiang Chen reg = <0x0 0xff168000 0x0 0x100>; 4787053e06bSLiang Chen interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 4797053e06bSLiang Chen clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 4807053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 4817053e06bSLiang Chen dmas = <&dmac 6>, <&dmac 7>; 4827053e06bSLiang Chen dma-names = "tx", "rx"; 4837053e06bSLiang Chen reg-shift = <2>; 4847053e06bSLiang Chen reg-io-width = <4>; 4857053e06bSLiang Chen pinctrl-names = "default"; 4867053e06bSLiang Chen pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 4877053e06bSLiang Chen status = "disabled"; 4887053e06bSLiang Chen }; 4897053e06bSLiang Chen 4907053e06bSLiang Chen uart4: serial@ff170000 { 4917053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 4927053e06bSLiang Chen reg = <0x0 0xff170000 0x0 0x100>; 4937053e06bSLiang Chen interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4947053e06bSLiang Chen clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 4957053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 4967053e06bSLiang Chen dmas = <&dmac 8>, <&dmac 9>; 4977053e06bSLiang Chen dma-names = "tx", "rx"; 4987053e06bSLiang Chen reg-shift = <2>; 4997053e06bSLiang Chen reg-io-width = <4>; 5007053e06bSLiang Chen pinctrl-names = "default"; 5017053e06bSLiang Chen pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 5027053e06bSLiang Chen status = "disabled"; 5037053e06bSLiang Chen }; 5047053e06bSLiang Chen 5057053e06bSLiang Chen uart5: serial@ff178000 { 5067053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 5077053e06bSLiang Chen reg = <0x0 0xff178000 0x0 0x100>; 5087053e06bSLiang Chen interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 5097053e06bSLiang Chen clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 5107053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 5117053e06bSLiang Chen dmas = <&dmac 10>, <&dmac 11>; 5127053e06bSLiang Chen dma-names = "tx", "rx"; 5137053e06bSLiang Chen reg-shift = <2>; 5147053e06bSLiang Chen reg-io-width = <4>; 5157053e06bSLiang Chen pinctrl-names = "default"; 5167053e06bSLiang Chen pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 5177053e06bSLiang Chen status = "disabled"; 5187053e06bSLiang Chen }; 5197053e06bSLiang Chen 5207053e06bSLiang Chen i2c0: i2c@ff180000 { 5217053e06bSLiang Chen compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 5227053e06bSLiang Chen reg = <0x0 0xff180000 0x0 0x1000>; 5237053e06bSLiang Chen clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 5247053e06bSLiang Chen clock-names = "i2c", "pclk"; 5257053e06bSLiang Chen interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 5267053e06bSLiang Chen pinctrl-names = "default"; 5277053e06bSLiang Chen pinctrl-0 = <&i2c0_xfer>; 5287053e06bSLiang Chen #address-cells = <1>; 5297053e06bSLiang Chen #size-cells = <0>; 5307053e06bSLiang Chen status = "disabled"; 5317053e06bSLiang Chen }; 5327053e06bSLiang Chen 5337053e06bSLiang Chen i2c1: i2c@ff190000 { 5347053e06bSLiang Chen compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 5357053e06bSLiang Chen reg = <0x0 0xff190000 0x0 0x1000>; 5367053e06bSLiang Chen clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 5377053e06bSLiang Chen clock-names = "i2c", "pclk"; 5387053e06bSLiang Chen interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5397053e06bSLiang Chen pinctrl-names = "default"; 5407053e06bSLiang Chen pinctrl-0 = <&i2c1_xfer>; 5417053e06bSLiang Chen #address-cells = <1>; 5427053e06bSLiang Chen #size-cells = <0>; 5437053e06bSLiang Chen status = "disabled"; 5447053e06bSLiang Chen }; 5457053e06bSLiang Chen 5467053e06bSLiang Chen i2c2: i2c@ff1a0000 { 5477053e06bSLiang Chen compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 5487053e06bSLiang Chen reg = <0x0 0xff1a0000 0x0 0x1000>; 5497053e06bSLiang Chen clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 5507053e06bSLiang Chen clock-names = "i2c", "pclk"; 5517053e06bSLiang Chen interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5527053e06bSLiang Chen pinctrl-names = "default"; 5537053e06bSLiang Chen pinctrl-0 = <&i2c2_xfer>; 5547053e06bSLiang Chen #address-cells = <1>; 5557053e06bSLiang Chen #size-cells = <0>; 5567053e06bSLiang Chen status = "disabled"; 5577053e06bSLiang Chen }; 5587053e06bSLiang Chen 5597053e06bSLiang Chen i2c3: i2c@ff1b0000 { 5607053e06bSLiang Chen compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 5617053e06bSLiang Chen reg = <0x0 0xff1b0000 0x0 0x1000>; 5627053e06bSLiang Chen clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 5637053e06bSLiang Chen clock-names = "i2c", "pclk"; 5647053e06bSLiang Chen interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5657053e06bSLiang Chen pinctrl-names = "default"; 5667053e06bSLiang Chen pinctrl-0 = <&i2c3_xfer>; 5677053e06bSLiang Chen #address-cells = <1>; 5687053e06bSLiang Chen #size-cells = <0>; 5697053e06bSLiang Chen status = "disabled"; 5707053e06bSLiang Chen }; 5717053e06bSLiang Chen 5727053e06bSLiang Chen spi0: spi@ff1d0000 { 5737053e06bSLiang Chen compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 5747053e06bSLiang Chen reg = <0x0 0xff1d0000 0x0 0x1000>; 5757053e06bSLiang Chen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 5767053e06bSLiang Chen clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 5777053e06bSLiang Chen clock-names = "spiclk", "apb_pclk"; 5787053e06bSLiang Chen dmas = <&dmac 12>, <&dmac 13>; 5797053e06bSLiang Chen dma-names = "tx", "rx"; 5807053e06bSLiang Chen pinctrl-names = "default"; 5817053e06bSLiang Chen pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 5827053e06bSLiang Chen #address-cells = <1>; 5837053e06bSLiang Chen #size-cells = <0>; 5847053e06bSLiang Chen status = "disabled"; 5857053e06bSLiang Chen }; 5867053e06bSLiang Chen 5877053e06bSLiang Chen spi1: spi@ff1d8000 { 5887053e06bSLiang Chen compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 5897053e06bSLiang Chen reg = <0x0 0xff1d8000 0x0 0x1000>; 5907053e06bSLiang Chen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 5917053e06bSLiang Chen clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 5927053e06bSLiang Chen clock-names = "spiclk", "apb_pclk"; 5937053e06bSLiang Chen dmas = <&dmac 14>, <&dmac 15>; 5947053e06bSLiang Chen dma-names = "tx", "rx"; 5957053e06bSLiang Chen pinctrl-names = "default"; 5967053e06bSLiang Chen pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 5977053e06bSLiang Chen #address-cells = <1>; 5987053e06bSLiang Chen #size-cells = <0>; 5997053e06bSLiang Chen status = "disabled"; 6007053e06bSLiang Chen }; 6017053e06bSLiang Chen 6027053e06bSLiang Chen wdt: watchdog@ff1e0000 { 6037053e06bSLiang Chen compatible = "snps,dw-wdt"; 6047053e06bSLiang Chen reg = <0x0 0xff1e0000 0x0 0x100>; 6057053e06bSLiang Chen clocks = <&cru PCLK_WDT_NS>; 6067053e06bSLiang Chen interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 6077053e06bSLiang Chen status = "disabled"; 6087053e06bSLiang Chen }; 6097053e06bSLiang Chen 6107053e06bSLiang Chen pwm0: pwm@ff200000 { 6117053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6127053e06bSLiang Chen reg = <0x0 0xff200000 0x0 0x10>; 6137053e06bSLiang Chen clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 6147053e06bSLiang Chen clock-names = "pwm", "pclk"; 6157053e06bSLiang Chen pinctrl-names = "default"; 6167053e06bSLiang Chen pinctrl-0 = <&pwm0_pin>; 6177053e06bSLiang Chen #pwm-cells = <3>; 6187053e06bSLiang Chen status = "disabled"; 6197053e06bSLiang Chen }; 6207053e06bSLiang Chen 6217053e06bSLiang Chen pwm1: pwm@ff200010 { 6227053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6237053e06bSLiang Chen reg = <0x0 0xff200010 0x0 0x10>; 6247053e06bSLiang Chen clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 6257053e06bSLiang Chen clock-names = "pwm", "pclk"; 6267053e06bSLiang Chen pinctrl-names = "default"; 6277053e06bSLiang Chen pinctrl-0 = <&pwm1_pin>; 6287053e06bSLiang Chen #pwm-cells = <3>; 6297053e06bSLiang Chen status = "disabled"; 6307053e06bSLiang Chen }; 6317053e06bSLiang Chen 6327053e06bSLiang Chen pwm2: pwm@ff200020 { 6337053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6347053e06bSLiang Chen reg = <0x0 0xff200020 0x0 0x10>; 6357053e06bSLiang Chen clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 6367053e06bSLiang Chen clock-names = "pwm", "pclk"; 6377053e06bSLiang Chen pinctrl-names = "default"; 6387053e06bSLiang Chen pinctrl-0 = <&pwm2_pin>; 6397053e06bSLiang Chen #pwm-cells = <3>; 6407053e06bSLiang Chen status = "disabled"; 6417053e06bSLiang Chen }; 6427053e06bSLiang Chen 6437053e06bSLiang Chen pwm3: pwm@ff200030 { 6447053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6457053e06bSLiang Chen reg = <0x0 0xff200030 0x0 0x10>; 6467053e06bSLiang Chen clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 6477053e06bSLiang Chen clock-names = "pwm", "pclk"; 6487053e06bSLiang Chen pinctrl-names = "default"; 6497053e06bSLiang Chen pinctrl-0 = <&pwm3_pin>; 6507053e06bSLiang Chen #pwm-cells = <3>; 6517053e06bSLiang Chen status = "disabled"; 6527053e06bSLiang Chen }; 6537053e06bSLiang Chen 6547053e06bSLiang Chen pwm4: pwm@ff208000 { 6557053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6567053e06bSLiang Chen reg = <0x0 0xff208000 0x0 0x10>; 6577053e06bSLiang Chen clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 6587053e06bSLiang Chen clock-names = "pwm", "pclk"; 6597053e06bSLiang Chen pinctrl-names = "default"; 6607053e06bSLiang Chen pinctrl-0 = <&pwm4_pin>; 6617053e06bSLiang Chen #pwm-cells = <3>; 6627053e06bSLiang Chen status = "disabled"; 6637053e06bSLiang Chen }; 6647053e06bSLiang Chen 6657053e06bSLiang Chen pwm5: pwm@ff208010 { 6667053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6677053e06bSLiang Chen reg = <0x0 0xff208010 0x0 0x10>; 6687053e06bSLiang Chen clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 6697053e06bSLiang Chen clock-names = "pwm", "pclk"; 6707053e06bSLiang Chen pinctrl-names = "default"; 6717053e06bSLiang Chen pinctrl-0 = <&pwm5_pin>; 6727053e06bSLiang Chen #pwm-cells = <3>; 6737053e06bSLiang Chen status = "disabled"; 6747053e06bSLiang Chen }; 6757053e06bSLiang Chen 6767053e06bSLiang Chen pwm6: pwm@ff208020 { 6777053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6787053e06bSLiang Chen reg = <0x0 0xff208020 0x0 0x10>; 6797053e06bSLiang Chen clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 6807053e06bSLiang Chen clock-names = "pwm", "pclk"; 6817053e06bSLiang Chen pinctrl-names = "default"; 6827053e06bSLiang Chen pinctrl-0 = <&pwm6_pin>; 6837053e06bSLiang Chen #pwm-cells = <3>; 6847053e06bSLiang Chen status = "disabled"; 6857053e06bSLiang Chen }; 6867053e06bSLiang Chen 6877053e06bSLiang Chen pwm7: pwm@ff208030 { 6887053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6897053e06bSLiang Chen reg = <0x0 0xff208030 0x0 0x10>; 6907053e06bSLiang Chen clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 6917053e06bSLiang Chen clock-names = "pwm", "pclk"; 6927053e06bSLiang Chen pinctrl-names = "default"; 6937053e06bSLiang Chen pinctrl-0 = <&pwm7_pin>; 6947053e06bSLiang Chen #pwm-cells = <3>; 6957053e06bSLiang Chen status = "disabled"; 6967053e06bSLiang Chen }; 6977053e06bSLiang Chen 6987053e06bSLiang Chen rktimer: timer@ff210000 { 6997053e06bSLiang Chen compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 7007053e06bSLiang Chen reg = <0x0 0xff210000 0x0 0x1000>; 7017053e06bSLiang Chen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 7027053e06bSLiang Chen clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 7037053e06bSLiang Chen clock-names = "pclk", "timer"; 7047053e06bSLiang Chen }; 7057053e06bSLiang Chen 706b2411befSJohan Jonker amba: bus { 7077053e06bSLiang Chen compatible = "simple-bus"; 7087053e06bSLiang Chen #address-cells = <2>; 7097053e06bSLiang Chen #size-cells = <2>; 7107053e06bSLiang Chen ranges; 7117053e06bSLiang Chen 7127053e06bSLiang Chen dmac: dmac@ff240000 { 7137053e06bSLiang Chen compatible = "arm,pl330", "arm,primecell"; 7147053e06bSLiang Chen reg = <0x0 0xff240000 0x0 0x4000>; 7157053e06bSLiang Chen interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7167053e06bSLiang Chen <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 7177053e06bSLiang Chen clocks = <&cru ACLK_DMAC>; 7187053e06bSLiang Chen clock-names = "apb_pclk"; 7197053e06bSLiang Chen #dma-cells = <1>; 7207053e06bSLiang Chen }; 7217053e06bSLiang Chen }; 7227053e06bSLiang Chen 723023115cdSHeiko Stuebner tsadc: tsadc@ff280000 { 724023115cdSHeiko Stuebner compatible = "rockchip,px30-tsadc"; 725023115cdSHeiko Stuebner reg = <0x0 0xff280000 0x0 0x100>; 726023115cdSHeiko Stuebner interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 727023115cdSHeiko Stuebner assigned-clocks = <&cru SCLK_TSADC>; 728023115cdSHeiko Stuebner assigned-clock-rates = <50000>; 729023115cdSHeiko Stuebner clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 730023115cdSHeiko Stuebner clock-names = "tsadc", "apb_pclk"; 731023115cdSHeiko Stuebner resets = <&cru SRST_TSADC>; 732023115cdSHeiko Stuebner reset-names = "tsadc-apb"; 733023115cdSHeiko Stuebner rockchip,grf = <&grf>; 734023115cdSHeiko Stuebner rockchip,hw-tshut-temp = <120000>; 735023115cdSHeiko Stuebner pinctrl-names = "init", "default", "sleep"; 736023115cdSHeiko Stuebner pinctrl-0 = <&tsadc_otp_gpio>; 737023115cdSHeiko Stuebner pinctrl-1 = <&tsadc_otp_out>; 738023115cdSHeiko Stuebner pinctrl-2 = <&tsadc_otp_gpio>; 739023115cdSHeiko Stuebner #thermal-sensor-cells = <1>; 740023115cdSHeiko Stuebner status = "disabled"; 741023115cdSHeiko Stuebner }; 742023115cdSHeiko Stuebner 7437053e06bSLiang Chen saradc: saradc@ff288000 { 7447053e06bSLiang Chen compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 7457053e06bSLiang Chen reg = <0x0 0xff288000 0x0 0x100>; 7467053e06bSLiang Chen interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 7477053e06bSLiang Chen #io-channel-cells = <1>; 7487053e06bSLiang Chen clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 7497053e06bSLiang Chen clock-names = "saradc", "apb_pclk"; 7507053e06bSLiang Chen resets = <&cru SRST_SARADC_P>; 7517053e06bSLiang Chen reset-names = "saradc-apb"; 7527053e06bSLiang Chen status = "disabled"; 7537053e06bSLiang Chen }; 7547053e06bSLiang Chen 755fbb78418SHeiko Stuebner otp: nvmem@ff290000 { 756fbb78418SHeiko Stuebner compatible = "rockchip,px30-otp"; 757fbb78418SHeiko Stuebner reg = <0x0 0xff290000 0x0 0x4000>; 758fbb78418SHeiko Stuebner clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 759fbb78418SHeiko Stuebner <&cru PCLK_OTP_PHY>; 760fbb78418SHeiko Stuebner clock-names = "otp", "apb_pclk", "phy"; 761fbb78418SHeiko Stuebner resets = <&cru SRST_OTP_PHY>; 762fbb78418SHeiko Stuebner reset-names = "phy"; 763fbb78418SHeiko Stuebner #address-cells = <1>; 764fbb78418SHeiko Stuebner #size-cells = <1>; 765fbb78418SHeiko Stuebner 766fbb78418SHeiko Stuebner /* Data cells */ 767fbb78418SHeiko Stuebner cpu_id: id@7 { 768fbb78418SHeiko Stuebner reg = <0x07 0x10>; 769fbb78418SHeiko Stuebner }; 770fbb78418SHeiko Stuebner cpu_leakage: cpu-leakage@17 { 771fbb78418SHeiko Stuebner reg = <0x17 0x1>; 772fbb78418SHeiko Stuebner }; 773fbb78418SHeiko Stuebner performance: performance@1e { 774fbb78418SHeiko Stuebner reg = <0x1e 0x1>; 775fbb78418SHeiko Stuebner bits = <4 3>; 776fbb78418SHeiko Stuebner }; 777fbb78418SHeiko Stuebner }; 778fbb78418SHeiko Stuebner 7797053e06bSLiang Chen cru: clock-controller@ff2b0000 { 7807053e06bSLiang Chen compatible = "rockchip,px30-cru"; 7817053e06bSLiang Chen reg = <0x0 0xff2b0000 0x0 0x1000>; 78245cb61b4SHeiko Stuebner clocks = <&xin24m>, <&pmucru PLL_GPLL>; 78345cb61b4SHeiko Stuebner clock-names = "xin24m", "gpll"; 7847053e06bSLiang Chen rockchip,grf = <&grf>; 7857053e06bSLiang Chen #clock-cells = <1>; 7867053e06bSLiang Chen #reset-cells = <1>; 7877053e06bSLiang Chen 78845cb61b4SHeiko Stuebner assigned-clocks = <&cru PLL_NPLL>, 78945cb61b4SHeiko Stuebner <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 79045cb61b4SHeiko Stuebner <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 79145cb61b4SHeiko Stuebner <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 79245cb61b4SHeiko Stuebner 79345cb61b4SHeiko Stuebner assigned-clock-rates = <1188000000>, 79445cb61b4SHeiko Stuebner <200000000>, <200000000>, 79545cb61b4SHeiko Stuebner <150000000>, <150000000>, 79645cb61b4SHeiko Stuebner <100000000>, <200000000>; 7977053e06bSLiang Chen }; 7987053e06bSLiang Chen 7997053e06bSLiang Chen pmucru: clock-controller@ff2bc000 { 8007053e06bSLiang Chen compatible = "rockchip,px30-pmucru"; 8017053e06bSLiang Chen reg = <0x0 0xff2bc000 0x0 0x1000>; 80245cb61b4SHeiko Stuebner clocks = <&xin24m>; 80345cb61b4SHeiko Stuebner clock-names = "xin24m"; 8047053e06bSLiang Chen rockchip,grf = <&grf>; 8057053e06bSLiang Chen #clock-cells = <1>; 8067053e06bSLiang Chen #reset-cells = <1>; 8077053e06bSLiang Chen 8087053e06bSLiang Chen assigned-clocks = 8097053e06bSLiang Chen <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 81045cb61b4SHeiko Stuebner <&pmucru SCLK_WIFI_PMU>; 8117053e06bSLiang Chen assigned-clock-rates = 8127053e06bSLiang Chen <1200000000>, <100000000>, 81345cb61b4SHeiko Stuebner <26000000>; 8147053e06bSLiang Chen }; 8157053e06bSLiang Chen 816f952b45bSHeiko Stuebner usb2phy_grf: syscon@ff2c0000 { 817f952b45bSHeiko Stuebner compatible = "rockchip,px30-usb2phy-grf", "syscon", 818f952b45bSHeiko Stuebner "simple-mfd"; 819f952b45bSHeiko Stuebner reg = <0x0 0xff2c0000 0x0 0x10000>; 820f952b45bSHeiko Stuebner #address-cells = <1>; 821f952b45bSHeiko Stuebner #size-cells = <1>; 822f952b45bSHeiko Stuebner 823f952b45bSHeiko Stuebner u2phy: usb2-phy@100 { 824f952b45bSHeiko Stuebner compatible = "rockchip,px30-usb2phy"; 825f952b45bSHeiko Stuebner reg = <0x100 0x20>; 826f952b45bSHeiko Stuebner clocks = <&pmucru SCLK_USBPHY_REF>; 827f952b45bSHeiko Stuebner clock-names = "phyclk"; 828f952b45bSHeiko Stuebner #clock-cells = <0>; 829f952b45bSHeiko Stuebner assigned-clocks = <&cru USB480M>; 830f952b45bSHeiko Stuebner assigned-clock-parents = <&u2phy>; 831f952b45bSHeiko Stuebner clock-output-names = "usb480m_phy"; 832f952b45bSHeiko Stuebner status = "disabled"; 833f952b45bSHeiko Stuebner 834f952b45bSHeiko Stuebner u2phy_host: host-port { 835f952b45bSHeiko Stuebner #phy-cells = <0>; 836f952b45bSHeiko Stuebner interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 837f952b45bSHeiko Stuebner interrupt-names = "linestate"; 838f952b45bSHeiko Stuebner status = "disabled"; 839f952b45bSHeiko Stuebner }; 840f952b45bSHeiko Stuebner 841f952b45bSHeiko Stuebner u2phy_otg: otg-port { 842f952b45bSHeiko Stuebner #phy-cells = <0>; 843f952b45bSHeiko Stuebner interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 844f952b45bSHeiko Stuebner <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 845f952b45bSHeiko Stuebner <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 846f952b45bSHeiko Stuebner interrupt-names = "otg-bvalid", "otg-id", 847f952b45bSHeiko Stuebner "linestate"; 848f952b45bSHeiko Stuebner status = "disabled"; 849f952b45bSHeiko Stuebner }; 850f952b45bSHeiko Stuebner }; 851f952b45bSHeiko Stuebner }; 852f952b45bSHeiko Stuebner 8537e90ccecSMiquel Raynal dsi_dphy: phy@ff2e0000 { 8547e90ccecSMiquel Raynal compatible = "rockchip,px30-dsi-dphy"; 8557e90ccecSMiquel Raynal reg = <0x0 0xff2e0000 0x0 0x10000>; 8567e90ccecSMiquel Raynal clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 8577e90ccecSMiquel Raynal clock-names = "ref", "pclk"; 8587e90ccecSMiquel Raynal resets = <&cru SRST_MIPIDSIPHY_P>; 8597e90ccecSMiquel Raynal reset-names = "apb"; 8607e90ccecSMiquel Raynal #phy-cells = <0>; 8617e90ccecSMiquel Raynal power-domains = <&power PX30_PD_VO>; 8627e90ccecSMiquel Raynal status = "disabled"; 8637e90ccecSMiquel Raynal }; 8647e90ccecSMiquel Raynal 865bb598133SHeiko Stuebner usb20_otg: usb@ff300000 { 866bb598133SHeiko Stuebner compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 867bb598133SHeiko Stuebner "snps,dwc2"; 868bb598133SHeiko Stuebner reg = <0x0 0xff300000 0x0 0x40000>; 869bb598133SHeiko Stuebner interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 870bb598133SHeiko Stuebner clocks = <&cru HCLK_OTG>; 871bb598133SHeiko Stuebner clock-names = "otg"; 872bb598133SHeiko Stuebner dr_mode = "otg"; 873bb598133SHeiko Stuebner g-np-tx-fifo-size = <16>; 874bb598133SHeiko Stuebner g-rx-fifo-size = <280>; 875bb598133SHeiko Stuebner g-tx-fifo-size = <256 128 128 64 32 16>; 876f952b45bSHeiko Stuebner phys = <&u2phy_otg>; 877f952b45bSHeiko Stuebner phy-names = "usb2-phy"; 878bb598133SHeiko Stuebner power-domains = <&power PX30_PD_USB>; 879bb598133SHeiko Stuebner status = "disabled"; 880bb598133SHeiko Stuebner }; 881bb598133SHeiko Stuebner 8827053e06bSLiang Chen usb_host0_ehci: usb@ff340000 { 8837053e06bSLiang Chen compatible = "generic-ehci"; 8847053e06bSLiang Chen reg = <0x0 0xff340000 0x0 0x10000>; 8857053e06bSLiang Chen interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 8867053e06bSLiang Chen clocks = <&cru HCLK_HOST>; 8877053e06bSLiang Chen clock-names = "usbhost"; 888f952b45bSHeiko Stuebner phys = <&u2phy_host>; 889f952b45bSHeiko Stuebner phy-names = "usb"; 8907053e06bSLiang Chen power-domains = <&power PX30_PD_USB>; 8917053e06bSLiang Chen status = "disabled"; 8927053e06bSLiang Chen }; 8937053e06bSLiang Chen 8947053e06bSLiang Chen usb_host0_ohci: usb@ff350000 { 8957053e06bSLiang Chen compatible = "generic-ohci"; 8967053e06bSLiang Chen reg = <0x0 0xff350000 0x0 0x10000>; 8977053e06bSLiang Chen interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 8987053e06bSLiang Chen clocks = <&cru HCLK_HOST>; 8997053e06bSLiang Chen clock-names = "usbhost"; 900f952b45bSHeiko Stuebner phys = <&u2phy_host>; 901f952b45bSHeiko Stuebner phy-names = "usb"; 9027053e06bSLiang Chen power-domains = <&power PX30_PD_USB>; 9037053e06bSLiang Chen status = "disabled"; 9047053e06bSLiang Chen }; 9057053e06bSLiang Chen 9067053e06bSLiang Chen gmac: ethernet@ff360000 { 9077053e06bSLiang Chen compatible = "rockchip,px30-gmac"; 9087053e06bSLiang Chen reg = <0x0 0xff360000 0x0 0x10000>; 9097053e06bSLiang Chen interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 9107053e06bSLiang Chen interrupt-names = "macirq"; 9117053e06bSLiang Chen clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 9127053e06bSLiang Chen <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 9137053e06bSLiang Chen <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 9147053e06bSLiang Chen <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 9157053e06bSLiang Chen clock-names = "stmmaceth", "mac_clk_rx", 9167053e06bSLiang Chen "mac_clk_tx", "clk_mac_ref", 9177053e06bSLiang Chen "clk_mac_refout", "aclk_mac", 9187053e06bSLiang Chen "pclk_mac", "clk_mac_speed"; 9197053e06bSLiang Chen rockchip,grf = <&grf>; 9207053e06bSLiang Chen phy-mode = "rmii"; 9217053e06bSLiang Chen pinctrl-names = "default"; 9227053e06bSLiang Chen pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 9237053e06bSLiang Chen power-domains = <&power PX30_PD_GMAC>; 9247053e06bSLiang Chen resets = <&cru SRST_GMAC_A>; 9257053e06bSLiang Chen reset-names = "stmmaceth"; 9267053e06bSLiang Chen status = "disabled"; 9277053e06bSLiang Chen }; 9287053e06bSLiang Chen 9293ef7c255SJohan Jonker sdmmc: mmc@ff370000 { 9307053e06bSLiang Chen compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 9317053e06bSLiang Chen reg = <0x0 0xff370000 0x0 0x4000>; 9327053e06bSLiang Chen interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 9337053e06bSLiang Chen clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 9347053e06bSLiang Chen <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 9357f214735SJohan Jonker clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 9367053e06bSLiang Chen fifo-depth = <0x100>; 9377053e06bSLiang Chen max-frequency = <150000000>; 9387053e06bSLiang Chen pinctrl-names = "default"; 9397053e06bSLiang Chen pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 9407053e06bSLiang Chen power-domains = <&power PX30_PD_SDCARD>; 9417053e06bSLiang Chen status = "disabled"; 9427053e06bSLiang Chen }; 9437053e06bSLiang Chen 9443ef7c255SJohan Jonker sdio: mmc@ff380000 { 9457053e06bSLiang Chen compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 9467053e06bSLiang Chen reg = <0x0 0xff380000 0x0 0x4000>; 9477053e06bSLiang Chen interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 9487053e06bSLiang Chen clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 9497053e06bSLiang Chen <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 9507f214735SJohan Jonker clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 9517053e06bSLiang Chen fifo-depth = <0x100>; 9527053e06bSLiang Chen max-frequency = <150000000>; 9537053e06bSLiang Chen pinctrl-names = "default"; 9547053e06bSLiang Chen pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 9557053e06bSLiang Chen power-domains = <&power PX30_PD_MMC_NAND>; 9567053e06bSLiang Chen status = "disabled"; 9577053e06bSLiang Chen }; 9587053e06bSLiang Chen 9593ef7c255SJohan Jonker emmc: mmc@ff390000 { 9607053e06bSLiang Chen compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 9617053e06bSLiang Chen reg = <0x0 0xff390000 0x0 0x4000>; 9627053e06bSLiang Chen interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 9637053e06bSLiang Chen clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 9647053e06bSLiang Chen <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 9657f214735SJohan Jonker clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 9667053e06bSLiang Chen fifo-depth = <0x100>; 9677053e06bSLiang Chen max-frequency = <150000000>; 968cdfebb27SHeiko Stuebner pinctrl-names = "default"; 969cdfebb27SHeiko Stuebner pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 9707053e06bSLiang Chen power-domains = <&power PX30_PD_MMC_NAND>; 9717053e06bSLiang Chen status = "disabled"; 9727053e06bSLiang Chen }; 9737053e06bSLiang Chen 974a07f34a0SHeiko Stuebner gpu: gpu@ff400000 { 975a07f34a0SHeiko Stuebner compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 976a07f34a0SHeiko Stuebner reg = <0x0 0xff400000 0x0 0x4000>; 977a07f34a0SHeiko Stuebner interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 978a07f34a0SHeiko Stuebner <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 979a07f34a0SHeiko Stuebner <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 980a07f34a0SHeiko Stuebner interrupt-names = "job", "mmu", "gpu"; 981a07f34a0SHeiko Stuebner clocks = <&cru SCLK_GPU>; 982a07f34a0SHeiko Stuebner #cooling-cells = <2>; 983a07f34a0SHeiko Stuebner power-domains = <&power PX30_PD_GPU>; 984a07f34a0SHeiko Stuebner status = "disabled"; 985a07f34a0SHeiko Stuebner }; 986a07f34a0SHeiko Stuebner 987cc5912abSHeiko Stuebner dsi: dsi@ff450000 { 988cc5912abSHeiko Stuebner compatible = "rockchip,px30-mipi-dsi"; 989cc5912abSHeiko Stuebner reg = <0x0 0xff450000 0x0 0x10000>; 990cc5912abSHeiko Stuebner interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 991cc5912abSHeiko Stuebner clocks = <&cru PCLK_MIPI_DSI>; 992cc5912abSHeiko Stuebner clock-names = "pclk"; 993cc5912abSHeiko Stuebner phys = <&dsi_dphy>; 994cc5912abSHeiko Stuebner phy-names = "dphy"; 995cc5912abSHeiko Stuebner power-domains = <&power PX30_PD_VO>; 996cc5912abSHeiko Stuebner resets = <&cru SRST_MIPIDSI_HOST_P>; 997cc5912abSHeiko Stuebner reset-names = "apb"; 998cc5912abSHeiko Stuebner rockchip,grf = <&grf>; 999cc5912abSHeiko Stuebner #address-cells = <1>; 1000cc5912abSHeiko Stuebner #size-cells = <0>; 1001cc5912abSHeiko Stuebner status = "disabled"; 1002cc5912abSHeiko Stuebner 1003cc5912abSHeiko Stuebner ports { 1004cc5912abSHeiko Stuebner #address-cells = <1>; 1005cc5912abSHeiko Stuebner #size-cells = <0>; 1006cc5912abSHeiko Stuebner 1007cc5912abSHeiko Stuebner port@0 { 1008cc5912abSHeiko Stuebner reg = <0>; 1009cc5912abSHeiko Stuebner #address-cells = <1>; 1010cc5912abSHeiko Stuebner #size-cells = <0>; 1011cc5912abSHeiko Stuebner 1012cc5912abSHeiko Stuebner dsi_in_vopb: endpoint@0 { 1013cc5912abSHeiko Stuebner reg = <0>; 1014cc5912abSHeiko Stuebner remote-endpoint = <&vopb_out_dsi>; 1015cc5912abSHeiko Stuebner }; 1016cc5912abSHeiko Stuebner 1017cc5912abSHeiko Stuebner dsi_in_vopl: endpoint@1 { 1018cc5912abSHeiko Stuebner reg = <1>; 1019cc5912abSHeiko Stuebner remote-endpoint = <&vopl_out_dsi>; 1020cc5912abSHeiko Stuebner }; 1021cc5912abSHeiko Stuebner }; 1022cc5912abSHeiko Stuebner }; 1023cc5912abSHeiko Stuebner }; 1024cc5912abSHeiko Stuebner 10257053e06bSLiang Chen vopb: vop@ff460000 { 10267053e06bSLiang Chen compatible = "rockchip,px30-vop-big"; 10277053e06bSLiang Chen reg = <0x0 0xff460000 0x0 0xefc>; 10287053e06bSLiang Chen interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 10297053e06bSLiang Chen clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 10307053e06bSLiang Chen <&cru HCLK_VOPB>; 10317053e06bSLiang Chen clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1032967c1464SSandy Huang resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1033967c1464SSandy Huang reset-names = "axi", "ahb", "dclk"; 10347053e06bSLiang Chen iommus = <&vopb_mmu>; 10357053e06bSLiang Chen power-domains = <&power PX30_PD_VO>; 10367053e06bSLiang Chen status = "disabled"; 1037967c1464SSandy Huang 1038967c1464SSandy Huang vopb_out: port { 1039967c1464SSandy Huang #address-cells = <1>; 1040967c1464SSandy Huang #size-cells = <0>; 1041cc5912abSHeiko Stuebner 1042cc5912abSHeiko Stuebner vopb_out_dsi: endpoint@0 { 1043cc5912abSHeiko Stuebner reg = <0>; 1044cc5912abSHeiko Stuebner remote-endpoint = <&dsi_in_vopb>; 1045cc5912abSHeiko Stuebner }; 1046dbb6f778SMiquel Raynal 1047dbb6f778SMiquel Raynal vopb_out_lvds: endpoint@1 { 1048dbb6f778SMiquel Raynal reg = <1>; 1049dbb6f778SMiquel Raynal remote-endpoint = <&lvds_vopb_in>; 1050dbb6f778SMiquel Raynal }; 1051967c1464SSandy Huang }; 10527053e06bSLiang Chen }; 10537053e06bSLiang Chen 10547053e06bSLiang Chen vopb_mmu: iommu@ff460f00 { 10557053e06bSLiang Chen compatible = "rockchip,iommu"; 10567053e06bSLiang Chen reg = <0x0 0xff460f00 0x0 0x100>; 10577053e06bSLiang Chen interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 10587053e06bSLiang Chen interrupt-names = "vopb_mmu"; 10597053e06bSLiang Chen clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 10608e57eed2SHeiko Stuebner clock-names = "aclk", "iface"; 10617053e06bSLiang Chen power-domains = <&power PX30_PD_VO>; 10627053e06bSLiang Chen #iommu-cells = <0>; 10637053e06bSLiang Chen status = "disabled"; 10647053e06bSLiang Chen }; 10657053e06bSLiang Chen 10667053e06bSLiang Chen vopl: vop@ff470000 { 10677053e06bSLiang Chen compatible = "rockchip,px30-vop-lit"; 10687053e06bSLiang Chen reg = <0x0 0xff470000 0x0 0xefc>; 10697053e06bSLiang Chen interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 10707053e06bSLiang Chen clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 10717053e06bSLiang Chen <&cru HCLK_VOPL>; 10727053e06bSLiang Chen clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1073967c1464SSandy Huang resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1074967c1464SSandy Huang reset-names = "axi", "ahb", "dclk"; 10757053e06bSLiang Chen iommus = <&vopl_mmu>; 10767053e06bSLiang Chen power-domains = <&power PX30_PD_VO>; 10777053e06bSLiang Chen status = "disabled"; 1078967c1464SSandy Huang 1079967c1464SSandy Huang vopl_out: port { 1080967c1464SSandy Huang #address-cells = <1>; 1081967c1464SSandy Huang #size-cells = <0>; 1082cc5912abSHeiko Stuebner 1083cc5912abSHeiko Stuebner vopl_out_dsi: endpoint@0 { 1084cc5912abSHeiko Stuebner reg = <0>; 1085cc5912abSHeiko Stuebner remote-endpoint = <&dsi_in_vopl>; 1086cc5912abSHeiko Stuebner }; 1087dbb6f778SMiquel Raynal 1088dbb6f778SMiquel Raynal vopl_out_lvds: endpoint@1 { 1089dbb6f778SMiquel Raynal reg = <1>; 1090dbb6f778SMiquel Raynal remote-endpoint = <&lvds_vopl_in>; 1091dbb6f778SMiquel Raynal }; 1092967c1464SSandy Huang }; 10937053e06bSLiang Chen }; 10947053e06bSLiang Chen 10957053e06bSLiang Chen vopl_mmu: iommu@ff470f00 { 10967053e06bSLiang Chen compatible = "rockchip,iommu"; 10977053e06bSLiang Chen reg = <0x0 0xff470f00 0x0 0x100>; 10987053e06bSLiang Chen interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 10997053e06bSLiang Chen interrupt-names = "vopl_mmu"; 11007053e06bSLiang Chen clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 11018e57eed2SHeiko Stuebner clock-names = "aclk", "iface"; 11027053e06bSLiang Chen power-domains = <&power PX30_PD_VO>; 11037053e06bSLiang Chen #iommu-cells = <0>; 11047053e06bSLiang Chen status = "disabled"; 11057053e06bSLiang Chen }; 11067053e06bSLiang Chen 11077053e06bSLiang Chen qos_gmac: qos@ff518000 { 11087053e06bSLiang Chen compatible = "syscon"; 11097053e06bSLiang Chen reg = <0x0 0xff518000 0x0 0x20>; 11107053e06bSLiang Chen }; 11117053e06bSLiang Chen 11127053e06bSLiang Chen qos_gpu: qos@ff520000 { 11137053e06bSLiang Chen compatible = "syscon"; 11147053e06bSLiang Chen reg = <0x0 0xff520000 0x0 0x20>; 11157053e06bSLiang Chen }; 11167053e06bSLiang Chen 11177053e06bSLiang Chen qos_sdmmc: qos@ff52c000 { 11187053e06bSLiang Chen compatible = "syscon"; 11197053e06bSLiang Chen reg = <0x0 0xff52c000 0x0 0x20>; 11207053e06bSLiang Chen }; 11217053e06bSLiang Chen 11227053e06bSLiang Chen qos_emmc: qos@ff538000 { 11237053e06bSLiang Chen compatible = "syscon"; 11247053e06bSLiang Chen reg = <0x0 0xff538000 0x0 0x20>; 11257053e06bSLiang Chen }; 11267053e06bSLiang Chen 11277053e06bSLiang Chen qos_nand: qos@ff538080 { 11287053e06bSLiang Chen compatible = "syscon"; 11297053e06bSLiang Chen reg = <0x0 0xff538080 0x0 0x20>; 11307053e06bSLiang Chen }; 11317053e06bSLiang Chen 11327053e06bSLiang Chen qos_sdio: qos@ff538100 { 11337053e06bSLiang Chen compatible = "syscon"; 11347053e06bSLiang Chen reg = <0x0 0xff538100 0x0 0x20>; 11357053e06bSLiang Chen }; 11367053e06bSLiang Chen 11377053e06bSLiang Chen qos_sfc: qos@ff538180 { 11387053e06bSLiang Chen compatible = "syscon"; 11397053e06bSLiang Chen reg = <0x0 0xff538180 0x0 0x20>; 11407053e06bSLiang Chen }; 11417053e06bSLiang Chen 11427053e06bSLiang Chen qos_usb_host: qos@ff540000 { 11437053e06bSLiang Chen compatible = "syscon"; 11447053e06bSLiang Chen reg = <0x0 0xff540000 0x0 0x20>; 11457053e06bSLiang Chen }; 11467053e06bSLiang Chen 11477053e06bSLiang Chen qos_usb_otg: qos@ff540080 { 11487053e06bSLiang Chen compatible = "syscon"; 11497053e06bSLiang Chen reg = <0x0 0xff540080 0x0 0x20>; 11507053e06bSLiang Chen }; 11517053e06bSLiang Chen 11527053e06bSLiang Chen qos_isp_128: qos@ff548000 { 11537053e06bSLiang Chen compatible = "syscon"; 11547053e06bSLiang Chen reg = <0x0 0xff548000 0x0 0x20>; 11557053e06bSLiang Chen }; 11567053e06bSLiang Chen 11577053e06bSLiang Chen qos_isp_rd: qos@ff548080 { 11587053e06bSLiang Chen compatible = "syscon"; 11597053e06bSLiang Chen reg = <0x0 0xff548080 0x0 0x20>; 11607053e06bSLiang Chen }; 11617053e06bSLiang Chen 11627053e06bSLiang Chen qos_isp_wr: qos@ff548100 { 11637053e06bSLiang Chen compatible = "syscon"; 11647053e06bSLiang Chen reg = <0x0 0xff548100 0x0 0x20>; 11657053e06bSLiang Chen }; 11667053e06bSLiang Chen 11677053e06bSLiang Chen qos_isp_m1: qos@ff548180 { 11687053e06bSLiang Chen compatible = "syscon"; 11697053e06bSLiang Chen reg = <0x0 0xff548180 0x0 0x20>; 11707053e06bSLiang Chen }; 11717053e06bSLiang Chen 11727053e06bSLiang Chen qos_vip: qos@ff548200 { 11737053e06bSLiang Chen compatible = "syscon"; 11747053e06bSLiang Chen reg = <0x0 0xff548200 0x0 0x20>; 11757053e06bSLiang Chen }; 11767053e06bSLiang Chen 11777053e06bSLiang Chen qos_rga_rd: qos@ff550000 { 11787053e06bSLiang Chen compatible = "syscon"; 11797053e06bSLiang Chen reg = <0x0 0xff550000 0x0 0x20>; 11807053e06bSLiang Chen }; 11817053e06bSLiang Chen 11827053e06bSLiang Chen qos_rga_wr: qos@ff550080 { 11837053e06bSLiang Chen compatible = "syscon"; 11847053e06bSLiang Chen reg = <0x0 0xff550080 0x0 0x20>; 11857053e06bSLiang Chen }; 11867053e06bSLiang Chen 11877053e06bSLiang Chen qos_vop_m0: qos@ff550100 { 11887053e06bSLiang Chen compatible = "syscon"; 11897053e06bSLiang Chen reg = <0x0 0xff550100 0x0 0x20>; 11907053e06bSLiang Chen }; 11917053e06bSLiang Chen 11927053e06bSLiang Chen qos_vop_m1: qos@ff550180 { 11937053e06bSLiang Chen compatible = "syscon"; 11947053e06bSLiang Chen reg = <0x0 0xff550180 0x0 0x20>; 11957053e06bSLiang Chen }; 11967053e06bSLiang Chen 11977053e06bSLiang Chen qos_vpu: qos@ff558000 { 11987053e06bSLiang Chen compatible = "syscon"; 11997053e06bSLiang Chen reg = <0x0 0xff558000 0x0 0x20>; 12007053e06bSLiang Chen }; 12017053e06bSLiang Chen 12027053e06bSLiang Chen qos_vpu_r128: qos@ff558080 { 12037053e06bSLiang Chen compatible = "syscon"; 12047053e06bSLiang Chen reg = <0x0 0xff558080 0x0 0x20>; 12057053e06bSLiang Chen }; 12067053e06bSLiang Chen 12077053e06bSLiang Chen pinctrl: pinctrl { 12087053e06bSLiang Chen compatible = "rockchip,px30-pinctrl"; 12097053e06bSLiang Chen rockchip,grf = <&grf>; 12107053e06bSLiang Chen rockchip,pmu = <&pmugrf>; 12117053e06bSLiang Chen #address-cells = <2>; 12127053e06bSLiang Chen #size-cells = <2>; 12137053e06bSLiang Chen ranges; 12147053e06bSLiang Chen 12157053e06bSLiang Chen gpio0: gpio0@ff040000 { 12167053e06bSLiang Chen compatible = "rockchip,gpio-bank"; 12177053e06bSLiang Chen reg = <0x0 0xff040000 0x0 0x100>; 12187053e06bSLiang Chen interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 12197053e06bSLiang Chen clocks = <&pmucru PCLK_GPIO0_PMU>; 12207053e06bSLiang Chen gpio-controller; 12217053e06bSLiang Chen #gpio-cells = <2>; 12227053e06bSLiang Chen 12237053e06bSLiang Chen interrupt-controller; 12247053e06bSLiang Chen #interrupt-cells = <2>; 12257053e06bSLiang Chen }; 12267053e06bSLiang Chen 12277053e06bSLiang Chen gpio1: gpio1@ff250000 { 12287053e06bSLiang Chen compatible = "rockchip,gpio-bank"; 12297053e06bSLiang Chen reg = <0x0 0xff250000 0x0 0x100>; 12307053e06bSLiang Chen interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 12317053e06bSLiang Chen clocks = <&cru PCLK_GPIO1>; 12327053e06bSLiang Chen gpio-controller; 12337053e06bSLiang Chen #gpio-cells = <2>; 12347053e06bSLiang Chen 12357053e06bSLiang Chen interrupt-controller; 12367053e06bSLiang Chen #interrupt-cells = <2>; 12377053e06bSLiang Chen }; 12387053e06bSLiang Chen 12397053e06bSLiang Chen gpio2: gpio2@ff260000 { 12407053e06bSLiang Chen compatible = "rockchip,gpio-bank"; 12417053e06bSLiang Chen reg = <0x0 0xff260000 0x0 0x100>; 12427053e06bSLiang Chen interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 12437053e06bSLiang Chen clocks = <&cru PCLK_GPIO2>; 12447053e06bSLiang Chen gpio-controller; 12457053e06bSLiang Chen #gpio-cells = <2>; 12467053e06bSLiang Chen 12477053e06bSLiang Chen interrupt-controller; 12487053e06bSLiang Chen #interrupt-cells = <2>; 12497053e06bSLiang Chen }; 12507053e06bSLiang Chen 12517053e06bSLiang Chen gpio3: gpio3@ff270000 { 12527053e06bSLiang Chen compatible = "rockchip,gpio-bank"; 12537053e06bSLiang Chen reg = <0x0 0xff270000 0x0 0x100>; 12547053e06bSLiang Chen interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 12557053e06bSLiang Chen clocks = <&cru PCLK_GPIO3>; 12567053e06bSLiang Chen gpio-controller; 12577053e06bSLiang Chen #gpio-cells = <2>; 12587053e06bSLiang Chen 12597053e06bSLiang Chen interrupt-controller; 12607053e06bSLiang Chen #interrupt-cells = <2>; 12617053e06bSLiang Chen }; 12627053e06bSLiang Chen 12637053e06bSLiang Chen pcfg_pull_up: pcfg-pull-up { 12647053e06bSLiang Chen bias-pull-up; 12657053e06bSLiang Chen }; 12667053e06bSLiang Chen 12677053e06bSLiang Chen pcfg_pull_down: pcfg-pull-down { 12687053e06bSLiang Chen bias-pull-down; 12697053e06bSLiang Chen }; 12707053e06bSLiang Chen 12717053e06bSLiang Chen pcfg_pull_none: pcfg-pull-none { 12727053e06bSLiang Chen bias-disable; 12737053e06bSLiang Chen }; 12747053e06bSLiang Chen 12757053e06bSLiang Chen pcfg_pull_none_2ma: pcfg-pull-none-2ma { 12767053e06bSLiang Chen bias-disable; 12777053e06bSLiang Chen drive-strength = <2>; 12787053e06bSLiang Chen }; 12797053e06bSLiang Chen 12807053e06bSLiang Chen pcfg_pull_up_2ma: pcfg-pull-up-2ma { 12817053e06bSLiang Chen bias-pull-up; 12827053e06bSLiang Chen drive-strength = <2>; 12837053e06bSLiang Chen }; 12847053e06bSLiang Chen 12857053e06bSLiang Chen pcfg_pull_up_4ma: pcfg-pull-up-4ma { 12867053e06bSLiang Chen bias-pull-up; 12877053e06bSLiang Chen drive-strength = <4>; 12887053e06bSLiang Chen }; 12897053e06bSLiang Chen 12907053e06bSLiang Chen pcfg_pull_none_4ma: pcfg-pull-none-4ma { 12917053e06bSLiang Chen bias-disable; 12927053e06bSLiang Chen drive-strength = <4>; 12937053e06bSLiang Chen }; 12947053e06bSLiang Chen 12957053e06bSLiang Chen pcfg_pull_down_4ma: pcfg-pull-down-4ma { 12967053e06bSLiang Chen bias-pull-down; 12977053e06bSLiang Chen drive-strength = <4>; 12987053e06bSLiang Chen }; 12997053e06bSLiang Chen 13007053e06bSLiang Chen pcfg_pull_none_8ma: pcfg-pull-none-8ma { 13017053e06bSLiang Chen bias-disable; 13027053e06bSLiang Chen drive-strength = <8>; 13037053e06bSLiang Chen }; 13047053e06bSLiang Chen 13057053e06bSLiang Chen pcfg_pull_up_8ma: pcfg-pull-up-8ma { 13067053e06bSLiang Chen bias-pull-up; 13077053e06bSLiang Chen drive-strength = <8>; 13087053e06bSLiang Chen }; 13097053e06bSLiang Chen 13107053e06bSLiang Chen pcfg_pull_none_12ma: pcfg-pull-none-12ma { 13117053e06bSLiang Chen bias-disable; 13127053e06bSLiang Chen drive-strength = <12>; 13137053e06bSLiang Chen }; 13147053e06bSLiang Chen 13157053e06bSLiang Chen pcfg_pull_up_12ma: pcfg-pull-up-12ma { 13167053e06bSLiang Chen bias-pull-up; 13177053e06bSLiang Chen drive-strength = <12>; 13187053e06bSLiang Chen }; 13197053e06bSLiang Chen 13207053e06bSLiang Chen pcfg_pull_none_smt: pcfg-pull-none-smt { 13217053e06bSLiang Chen bias-disable; 13227053e06bSLiang Chen input-schmitt-enable; 13237053e06bSLiang Chen }; 13247053e06bSLiang Chen 13257053e06bSLiang Chen pcfg_output_high: pcfg-output-high { 13267053e06bSLiang Chen output-high; 13277053e06bSLiang Chen }; 13287053e06bSLiang Chen 13297053e06bSLiang Chen pcfg_output_low: pcfg-output-low { 13307053e06bSLiang Chen output-low; 13317053e06bSLiang Chen }; 13327053e06bSLiang Chen 13337053e06bSLiang Chen pcfg_input_high: pcfg-input-high { 13347053e06bSLiang Chen bias-pull-up; 13357053e06bSLiang Chen input-enable; 13367053e06bSLiang Chen }; 13377053e06bSLiang Chen 13387053e06bSLiang Chen pcfg_input: pcfg-input { 13397053e06bSLiang Chen input-enable; 13407053e06bSLiang Chen }; 13417053e06bSLiang Chen 13427053e06bSLiang Chen i2c0 { 13437053e06bSLiang Chen i2c0_xfer: i2c0-xfer { 13447053e06bSLiang Chen rockchip,pins = 13457053e06bSLiang Chen <0 RK_PB0 1 &pcfg_pull_none_smt>, 13467053e06bSLiang Chen <0 RK_PB1 1 &pcfg_pull_none_smt>; 13477053e06bSLiang Chen }; 13487053e06bSLiang Chen }; 13497053e06bSLiang Chen 13507053e06bSLiang Chen i2c1 { 13517053e06bSLiang Chen i2c1_xfer: i2c1-xfer { 13527053e06bSLiang Chen rockchip,pins = 13537053e06bSLiang Chen <0 RK_PC2 1 &pcfg_pull_none_smt>, 13547053e06bSLiang Chen <0 RK_PC3 1 &pcfg_pull_none_smt>; 13557053e06bSLiang Chen }; 13567053e06bSLiang Chen }; 13577053e06bSLiang Chen 13587053e06bSLiang Chen i2c2 { 13597053e06bSLiang Chen i2c2_xfer: i2c2-xfer { 13607053e06bSLiang Chen rockchip,pins = 13617053e06bSLiang Chen <2 RK_PB7 2 &pcfg_pull_none_smt>, 13627053e06bSLiang Chen <2 RK_PC0 2 &pcfg_pull_none_smt>; 13637053e06bSLiang Chen }; 13647053e06bSLiang Chen }; 13657053e06bSLiang Chen 13667053e06bSLiang Chen i2c3 { 13677053e06bSLiang Chen i2c3_xfer: i2c3-xfer { 13687053e06bSLiang Chen rockchip,pins = 13697053e06bSLiang Chen <1 RK_PB4 4 &pcfg_pull_none_smt>, 13707053e06bSLiang Chen <1 RK_PB5 4 &pcfg_pull_none_smt>; 13717053e06bSLiang Chen }; 13727053e06bSLiang Chen }; 13737053e06bSLiang Chen 13747053e06bSLiang Chen tsadc { 13757053e06bSLiang Chen tsadc_otp_gpio: tsadc-otp-gpio { 13767053e06bSLiang Chen rockchip,pins = 13777053e06bSLiang Chen <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 13787053e06bSLiang Chen }; 13797053e06bSLiang Chen 13807053e06bSLiang Chen tsadc_otp_out: tsadc-otp-out { 13817053e06bSLiang Chen rockchip,pins = 13827053e06bSLiang Chen <0 RK_PA6 1 &pcfg_pull_none>; 13837053e06bSLiang Chen }; 13847053e06bSLiang Chen }; 13857053e06bSLiang Chen 13867053e06bSLiang Chen uart0 { 13877053e06bSLiang Chen uart0_xfer: uart0-xfer { 13887053e06bSLiang Chen rockchip,pins = 13897053e06bSLiang Chen <0 RK_PB2 1 &pcfg_pull_up>, 13907053e06bSLiang Chen <0 RK_PB3 1 &pcfg_pull_up>; 13917053e06bSLiang Chen }; 13927053e06bSLiang Chen 13937053e06bSLiang Chen uart0_cts: uart0-cts { 13947053e06bSLiang Chen rockchip,pins = 13957053e06bSLiang Chen <0 RK_PB4 1 &pcfg_pull_none>; 13967053e06bSLiang Chen }; 13977053e06bSLiang Chen 13987053e06bSLiang Chen uart0_rts: uart0-rts { 13997053e06bSLiang Chen rockchip,pins = 14007053e06bSLiang Chen <0 RK_PB5 1 &pcfg_pull_none>; 14017053e06bSLiang Chen }; 14027053e06bSLiang Chen }; 14037053e06bSLiang Chen 14047053e06bSLiang Chen uart1 { 14057053e06bSLiang Chen uart1_xfer: uart1-xfer { 14067053e06bSLiang Chen rockchip,pins = 14077053e06bSLiang Chen <1 RK_PC1 1 &pcfg_pull_up>, 14087053e06bSLiang Chen <1 RK_PC0 1 &pcfg_pull_up>; 14097053e06bSLiang Chen }; 14107053e06bSLiang Chen 14117053e06bSLiang Chen uart1_cts: uart1-cts { 14127053e06bSLiang Chen rockchip,pins = 14137053e06bSLiang Chen <1 RK_PC2 1 &pcfg_pull_none>; 14147053e06bSLiang Chen }; 14157053e06bSLiang Chen 14167053e06bSLiang Chen uart1_rts: uart1-rts { 14177053e06bSLiang Chen rockchip,pins = 14187053e06bSLiang Chen <1 RK_PC3 1 &pcfg_pull_none>; 14197053e06bSLiang Chen }; 14207053e06bSLiang Chen }; 14217053e06bSLiang Chen 14227053e06bSLiang Chen uart2-m0 { 14237053e06bSLiang Chen uart2m0_xfer: uart2m0-xfer { 14247053e06bSLiang Chen rockchip,pins = 14257053e06bSLiang Chen <1 RK_PD2 2 &pcfg_pull_up>, 14267053e06bSLiang Chen <1 RK_PD3 2 &pcfg_pull_up>; 14277053e06bSLiang Chen }; 14287053e06bSLiang Chen }; 14297053e06bSLiang Chen 14307053e06bSLiang Chen uart2-m1 { 14317053e06bSLiang Chen uart2m1_xfer: uart2m1-xfer { 14327053e06bSLiang Chen rockchip,pins = 14337053e06bSLiang Chen <2 RK_PB4 2 &pcfg_pull_up>, 14347053e06bSLiang Chen <2 RK_PB6 2 &pcfg_pull_up>; 14357053e06bSLiang Chen }; 14367053e06bSLiang Chen }; 14377053e06bSLiang Chen 14387053e06bSLiang Chen uart3-m0 { 14397053e06bSLiang Chen uart3m0_xfer: uart3m0-xfer { 14407053e06bSLiang Chen rockchip,pins = 14417053e06bSLiang Chen <0 RK_PC0 2 &pcfg_pull_up>, 14427053e06bSLiang Chen <0 RK_PC1 2 &pcfg_pull_up>; 14437053e06bSLiang Chen }; 14447053e06bSLiang Chen 14457053e06bSLiang Chen uart3m0_cts: uart3m0-cts { 14467053e06bSLiang Chen rockchip,pins = 14477053e06bSLiang Chen <0 RK_PC2 2 &pcfg_pull_none>; 14487053e06bSLiang Chen }; 14497053e06bSLiang Chen 14507053e06bSLiang Chen uart3m0_rts: uart3m0-rts { 14517053e06bSLiang Chen rockchip,pins = 14527053e06bSLiang Chen <0 RK_PC3 2 &pcfg_pull_none>; 14537053e06bSLiang Chen }; 14547053e06bSLiang Chen }; 14557053e06bSLiang Chen 14567053e06bSLiang Chen uart3-m1 { 14577053e06bSLiang Chen uart3m1_xfer: uart3m1-xfer { 14587053e06bSLiang Chen rockchip,pins = 14597053e06bSLiang Chen <1 RK_PB6 2 &pcfg_pull_up>, 14607053e06bSLiang Chen <1 RK_PB7 2 &pcfg_pull_up>; 14617053e06bSLiang Chen }; 14627053e06bSLiang Chen 14637053e06bSLiang Chen uart3m1_cts: uart3m1-cts { 14647053e06bSLiang Chen rockchip,pins = 14657053e06bSLiang Chen <1 RK_PB4 2 &pcfg_pull_none>; 14667053e06bSLiang Chen }; 14677053e06bSLiang Chen 14687053e06bSLiang Chen uart3m1_rts: uart3m1-rts { 14697053e06bSLiang Chen rockchip,pins = 14707053e06bSLiang Chen <1 RK_PB5 2 &pcfg_pull_none>; 14717053e06bSLiang Chen }; 14727053e06bSLiang Chen }; 14737053e06bSLiang Chen 14747053e06bSLiang Chen uart4 { 14757053e06bSLiang Chen uart4_xfer: uart4-xfer { 14767053e06bSLiang Chen rockchip,pins = 14777053e06bSLiang Chen <1 RK_PD4 2 &pcfg_pull_up>, 14787053e06bSLiang Chen <1 RK_PD5 2 &pcfg_pull_up>; 14797053e06bSLiang Chen }; 14807053e06bSLiang Chen 14817053e06bSLiang Chen uart4_cts: uart4-cts { 14827053e06bSLiang Chen rockchip,pins = 14837053e06bSLiang Chen <1 RK_PD6 2 &pcfg_pull_none>; 14847053e06bSLiang Chen }; 14857053e06bSLiang Chen 14867053e06bSLiang Chen uart4_rts: uart4-rts { 14877053e06bSLiang Chen rockchip,pins = 14887053e06bSLiang Chen <1 RK_PD7 2 &pcfg_pull_none>; 14897053e06bSLiang Chen }; 14907053e06bSLiang Chen }; 14917053e06bSLiang Chen 14927053e06bSLiang Chen uart5 { 14937053e06bSLiang Chen uart5_xfer: uart5-xfer { 14947053e06bSLiang Chen rockchip,pins = 14957053e06bSLiang Chen <3 RK_PA2 4 &pcfg_pull_up>, 14967053e06bSLiang Chen <3 RK_PA1 4 &pcfg_pull_up>; 14977053e06bSLiang Chen }; 14987053e06bSLiang Chen 14997053e06bSLiang Chen uart5_cts: uart5-cts { 15007053e06bSLiang Chen rockchip,pins = 15017053e06bSLiang Chen <3 RK_PA3 4 &pcfg_pull_none>; 15027053e06bSLiang Chen }; 15037053e06bSLiang Chen 15047053e06bSLiang Chen uart5_rts: uart5-rts { 15057053e06bSLiang Chen rockchip,pins = 15067053e06bSLiang Chen <3 RK_PA5 4 &pcfg_pull_none>; 15077053e06bSLiang Chen }; 15087053e06bSLiang Chen }; 15097053e06bSLiang Chen 15107053e06bSLiang Chen spi0 { 15117053e06bSLiang Chen spi0_clk: spi0-clk { 15127053e06bSLiang Chen rockchip,pins = 15137053e06bSLiang Chen <1 RK_PB7 3 &pcfg_pull_up_4ma>; 15147053e06bSLiang Chen }; 15157053e06bSLiang Chen 15167053e06bSLiang Chen spi0_csn: spi0-csn { 15177053e06bSLiang Chen rockchip,pins = 15187053e06bSLiang Chen <1 RK_PB6 3 &pcfg_pull_up_4ma>; 15197053e06bSLiang Chen }; 15207053e06bSLiang Chen 15217053e06bSLiang Chen spi0_miso: spi0-miso { 15227053e06bSLiang Chen rockchip,pins = 15237053e06bSLiang Chen <1 RK_PB5 3 &pcfg_pull_up_4ma>; 15247053e06bSLiang Chen }; 15257053e06bSLiang Chen 15267053e06bSLiang Chen spi0_mosi: spi0-mosi { 15277053e06bSLiang Chen rockchip,pins = 15287053e06bSLiang Chen <1 RK_PB4 3 &pcfg_pull_up_4ma>; 15297053e06bSLiang Chen }; 15307053e06bSLiang Chen 15317053e06bSLiang Chen spi0_clk_hs: spi0-clk-hs { 15327053e06bSLiang Chen rockchip,pins = 15337053e06bSLiang Chen <1 RK_PB7 3 &pcfg_pull_up_8ma>; 15347053e06bSLiang Chen }; 15357053e06bSLiang Chen 15367053e06bSLiang Chen spi0_miso_hs: spi0-miso-hs { 15377053e06bSLiang Chen rockchip,pins = 15387053e06bSLiang Chen <1 RK_PB5 3 &pcfg_pull_up_8ma>; 15397053e06bSLiang Chen }; 15407053e06bSLiang Chen 15417053e06bSLiang Chen spi0_mosi_hs: spi0-mosi-hs { 15427053e06bSLiang Chen rockchip,pins = 15437053e06bSLiang Chen <1 RK_PB4 3 &pcfg_pull_up_8ma>; 15447053e06bSLiang Chen }; 15457053e06bSLiang Chen }; 15467053e06bSLiang Chen 15477053e06bSLiang Chen spi1 { 15487053e06bSLiang Chen spi1_clk: spi1-clk { 15497053e06bSLiang Chen rockchip,pins = 15507053e06bSLiang Chen <3 RK_PB7 4 &pcfg_pull_up_4ma>; 15517053e06bSLiang Chen }; 15527053e06bSLiang Chen 15537053e06bSLiang Chen spi1_csn0: spi1-csn0 { 15547053e06bSLiang Chen rockchip,pins = 15557053e06bSLiang Chen <3 RK_PB1 4 &pcfg_pull_up_4ma>; 15567053e06bSLiang Chen }; 15577053e06bSLiang Chen 15587053e06bSLiang Chen spi1_csn1: spi1-csn1 { 15597053e06bSLiang Chen rockchip,pins = 15607053e06bSLiang Chen <3 RK_PB2 2 &pcfg_pull_up_4ma>; 15617053e06bSLiang Chen }; 15627053e06bSLiang Chen 15637053e06bSLiang Chen spi1_miso: spi1-miso { 15647053e06bSLiang Chen rockchip,pins = 15657053e06bSLiang Chen <3 RK_PB6 4 &pcfg_pull_up_4ma>; 15667053e06bSLiang Chen }; 15677053e06bSLiang Chen 15687053e06bSLiang Chen spi1_mosi: spi1-mosi { 15697053e06bSLiang Chen rockchip,pins = 15707053e06bSLiang Chen <3 RK_PB4 4 &pcfg_pull_up_4ma>; 15717053e06bSLiang Chen }; 15727053e06bSLiang Chen 15737053e06bSLiang Chen spi1_clk_hs: spi1-clk-hs { 15747053e06bSLiang Chen rockchip,pins = 15757053e06bSLiang Chen <3 RK_PB7 4 &pcfg_pull_up_8ma>; 15767053e06bSLiang Chen }; 15777053e06bSLiang Chen 15787053e06bSLiang Chen spi1_miso_hs: spi1-miso-hs { 15797053e06bSLiang Chen rockchip,pins = 15807053e06bSLiang Chen <3 RK_PB6 4 &pcfg_pull_up_8ma>; 15817053e06bSLiang Chen }; 15827053e06bSLiang Chen 15837053e06bSLiang Chen spi1_mosi_hs: spi1-mosi-hs { 15847053e06bSLiang Chen rockchip,pins = 15857053e06bSLiang Chen <3 RK_PB4 4 &pcfg_pull_up_8ma>; 15867053e06bSLiang Chen }; 15877053e06bSLiang Chen }; 15887053e06bSLiang Chen 15897053e06bSLiang Chen pdm { 15907053e06bSLiang Chen pdm_clk0m0: pdm-clk0m0 { 15917053e06bSLiang Chen rockchip,pins = 15927053e06bSLiang Chen <3 RK_PC6 2 &pcfg_pull_none>; 15937053e06bSLiang Chen }; 15947053e06bSLiang Chen 15957053e06bSLiang Chen pdm_clk0m1: pdm-clk0m1 { 15967053e06bSLiang Chen rockchip,pins = 15977053e06bSLiang Chen <2 RK_PC6 1 &pcfg_pull_none>; 15987053e06bSLiang Chen }; 15997053e06bSLiang Chen 16007053e06bSLiang Chen pdm_clk1: pdm-clk1 { 16017053e06bSLiang Chen rockchip,pins = 16027053e06bSLiang Chen <3 RK_PC7 2 &pcfg_pull_none>; 16037053e06bSLiang Chen }; 16047053e06bSLiang Chen 16057053e06bSLiang Chen pdm_sdi0m0: pdm-sdi0m0 { 16067053e06bSLiang Chen rockchip,pins = 16077053e06bSLiang Chen <3 RK_PD3 2 &pcfg_pull_none>; 16087053e06bSLiang Chen }; 16097053e06bSLiang Chen 16107053e06bSLiang Chen pdm_sdi0m1: pdm-sdi0m1 { 16117053e06bSLiang Chen rockchip,pins = 16127053e06bSLiang Chen <2 RK_PC5 2 &pcfg_pull_none>; 16137053e06bSLiang Chen }; 16147053e06bSLiang Chen 16157053e06bSLiang Chen pdm_sdi1: pdm-sdi1 { 16167053e06bSLiang Chen rockchip,pins = 16177053e06bSLiang Chen <3 RK_PD0 2 &pcfg_pull_none>; 16187053e06bSLiang Chen }; 16197053e06bSLiang Chen 16207053e06bSLiang Chen pdm_sdi2: pdm-sdi2 { 16217053e06bSLiang Chen rockchip,pins = 16227053e06bSLiang Chen <3 RK_PD1 2 &pcfg_pull_none>; 16237053e06bSLiang Chen }; 16247053e06bSLiang Chen 16257053e06bSLiang Chen pdm_sdi3: pdm-sdi3 { 16267053e06bSLiang Chen rockchip,pins = 16277053e06bSLiang Chen <3 RK_PD2 2 &pcfg_pull_none>; 16287053e06bSLiang Chen }; 16297053e06bSLiang Chen 16307053e06bSLiang Chen pdm_clk0m0_sleep: pdm-clk0m0-sleep { 16317053e06bSLiang Chen rockchip,pins = 16327053e06bSLiang Chen <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 16337053e06bSLiang Chen }; 16347053e06bSLiang Chen 16357053e06bSLiang Chen pdm_clk0m_sleep1: pdm-clk0m1-sleep { 16367053e06bSLiang Chen rockchip,pins = 16377053e06bSLiang Chen <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 16387053e06bSLiang Chen }; 16397053e06bSLiang Chen 16407053e06bSLiang Chen pdm_clk1_sleep: pdm-clk1-sleep { 16417053e06bSLiang Chen rockchip,pins = 16427053e06bSLiang Chen <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 16437053e06bSLiang Chen }; 16447053e06bSLiang Chen 16457053e06bSLiang Chen pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 16467053e06bSLiang Chen rockchip,pins = 16477053e06bSLiang Chen <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 16487053e06bSLiang Chen }; 16497053e06bSLiang Chen 16507053e06bSLiang Chen pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 16517053e06bSLiang Chen rockchip,pins = 16527053e06bSLiang Chen <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 16537053e06bSLiang Chen }; 16547053e06bSLiang Chen 16557053e06bSLiang Chen pdm_sdi1_sleep: pdm-sdi1-sleep { 16567053e06bSLiang Chen rockchip,pins = 16577053e06bSLiang Chen <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 16587053e06bSLiang Chen }; 16597053e06bSLiang Chen 16607053e06bSLiang Chen pdm_sdi2_sleep: pdm-sdi2-sleep { 16617053e06bSLiang Chen rockchip,pins = 16627053e06bSLiang Chen <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 16637053e06bSLiang Chen }; 16647053e06bSLiang Chen 16657053e06bSLiang Chen pdm_sdi3_sleep: pdm-sdi3-sleep { 16667053e06bSLiang Chen rockchip,pins = 16677053e06bSLiang Chen <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 16687053e06bSLiang Chen }; 16697053e06bSLiang Chen }; 16707053e06bSLiang Chen 16717053e06bSLiang Chen i2s0 { 16727053e06bSLiang Chen i2s0_8ch_mclk: i2s0-8ch-mclk { 16737053e06bSLiang Chen rockchip,pins = 16747053e06bSLiang Chen <3 RK_PC1 2 &pcfg_pull_none>; 16757053e06bSLiang Chen }; 16767053e06bSLiang Chen 16777053e06bSLiang Chen i2s0_8ch_sclktx: i2s0-8ch-sclktx { 16787053e06bSLiang Chen rockchip,pins = 16797053e06bSLiang Chen <3 RK_PC3 2 &pcfg_pull_none>; 16807053e06bSLiang Chen }; 16817053e06bSLiang Chen 16827053e06bSLiang Chen i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 16837053e06bSLiang Chen rockchip,pins = 16847053e06bSLiang Chen <3 RK_PB4 2 &pcfg_pull_none>; 16857053e06bSLiang Chen }; 16867053e06bSLiang Chen 16877053e06bSLiang Chen i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 16887053e06bSLiang Chen rockchip,pins = 16897053e06bSLiang Chen <3 RK_PC2 2 &pcfg_pull_none>; 16907053e06bSLiang Chen }; 16917053e06bSLiang Chen 16927053e06bSLiang Chen i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 16937053e06bSLiang Chen rockchip,pins = 16947053e06bSLiang Chen <3 RK_PB5 2 &pcfg_pull_none>; 16957053e06bSLiang Chen }; 16967053e06bSLiang Chen 16977053e06bSLiang Chen i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 16987053e06bSLiang Chen rockchip,pins = 16997053e06bSLiang Chen <3 RK_PC4 2 &pcfg_pull_none>; 17007053e06bSLiang Chen }; 17017053e06bSLiang Chen 17027053e06bSLiang Chen i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 17037053e06bSLiang Chen rockchip,pins = 17047053e06bSLiang Chen <3 RK_PC0 2 &pcfg_pull_none>; 17057053e06bSLiang Chen }; 17067053e06bSLiang Chen 17077053e06bSLiang Chen i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 17087053e06bSLiang Chen rockchip,pins = 17097053e06bSLiang Chen <3 RK_PB7 2 &pcfg_pull_none>; 17107053e06bSLiang Chen }; 17117053e06bSLiang Chen 17127053e06bSLiang Chen i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 17137053e06bSLiang Chen rockchip,pins = 17147053e06bSLiang Chen <3 RK_PB6 2 &pcfg_pull_none>; 17157053e06bSLiang Chen }; 17167053e06bSLiang Chen 17177053e06bSLiang Chen i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 17187053e06bSLiang Chen rockchip,pins = 17197053e06bSLiang Chen <3 RK_PC5 2 &pcfg_pull_none>; 17207053e06bSLiang Chen }; 17217053e06bSLiang Chen 17227053e06bSLiang Chen i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 17237053e06bSLiang Chen rockchip,pins = 17247053e06bSLiang Chen <3 RK_PB3 2 &pcfg_pull_none>; 17257053e06bSLiang Chen }; 17267053e06bSLiang Chen 17277053e06bSLiang Chen i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 17287053e06bSLiang Chen rockchip,pins = 17297053e06bSLiang Chen <3 RK_PB1 2 &pcfg_pull_none>; 17307053e06bSLiang Chen }; 17317053e06bSLiang Chen 17327053e06bSLiang Chen i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 17337053e06bSLiang Chen rockchip,pins = 17347053e06bSLiang Chen <3 RK_PB0 2 &pcfg_pull_none>; 17357053e06bSLiang Chen }; 17367053e06bSLiang Chen }; 17377053e06bSLiang Chen 17387053e06bSLiang Chen i2s1 { 17397053e06bSLiang Chen i2s1_2ch_mclk: i2s1-2ch-mclk { 17407053e06bSLiang Chen rockchip,pins = 17417053e06bSLiang Chen <2 RK_PC3 1 &pcfg_pull_none>; 17427053e06bSLiang Chen }; 17437053e06bSLiang Chen 17447053e06bSLiang Chen i2s1_2ch_sclk: i2s1-2ch-sclk { 17457053e06bSLiang Chen rockchip,pins = 17467053e06bSLiang Chen <2 RK_PC2 1 &pcfg_pull_none>; 17477053e06bSLiang Chen }; 17487053e06bSLiang Chen 17497053e06bSLiang Chen i2s1_2ch_lrck: i2s1-2ch-lrck { 17507053e06bSLiang Chen rockchip,pins = 17517053e06bSLiang Chen <2 RK_PC1 1 &pcfg_pull_none>; 17527053e06bSLiang Chen }; 17537053e06bSLiang Chen 17547053e06bSLiang Chen i2s1_2ch_sdi: i2s1-2ch-sdi { 17557053e06bSLiang Chen rockchip,pins = 17567053e06bSLiang Chen <2 RK_PC5 1 &pcfg_pull_none>; 17577053e06bSLiang Chen }; 17587053e06bSLiang Chen 17597053e06bSLiang Chen i2s1_2ch_sdo: i2s1-2ch-sdo { 17607053e06bSLiang Chen rockchip,pins = 17617053e06bSLiang Chen <2 RK_PC4 1 &pcfg_pull_none>; 17627053e06bSLiang Chen }; 17637053e06bSLiang Chen }; 17647053e06bSLiang Chen 17657053e06bSLiang Chen i2s2 { 17667053e06bSLiang Chen i2s2_2ch_mclk: i2s2-2ch-mclk { 17677053e06bSLiang Chen rockchip,pins = 17687053e06bSLiang Chen <3 RK_PA1 2 &pcfg_pull_none>; 17697053e06bSLiang Chen }; 17707053e06bSLiang Chen 17717053e06bSLiang Chen i2s2_2ch_sclk: i2s2-2ch-sclk { 17727053e06bSLiang Chen rockchip,pins = 17737053e06bSLiang Chen <3 RK_PA2 2 &pcfg_pull_none>; 17747053e06bSLiang Chen }; 17757053e06bSLiang Chen 17767053e06bSLiang Chen i2s2_2ch_lrck: i2s2-2ch-lrck { 17777053e06bSLiang Chen rockchip,pins = 17787053e06bSLiang Chen <3 RK_PA3 2 &pcfg_pull_none>; 17797053e06bSLiang Chen }; 17807053e06bSLiang Chen 17817053e06bSLiang Chen i2s2_2ch_sdi: i2s2-2ch-sdi { 17827053e06bSLiang Chen rockchip,pins = 17837053e06bSLiang Chen <3 RK_PA5 2 &pcfg_pull_none>; 17847053e06bSLiang Chen }; 17857053e06bSLiang Chen 17867053e06bSLiang Chen i2s2_2ch_sdo: i2s2-2ch-sdo { 17877053e06bSLiang Chen rockchip,pins = 17887053e06bSLiang Chen <3 RK_PA7 2 &pcfg_pull_none>; 17897053e06bSLiang Chen }; 17907053e06bSLiang Chen }; 17917053e06bSLiang Chen 17927053e06bSLiang Chen sdmmc { 17937053e06bSLiang Chen sdmmc_clk: sdmmc-clk { 17947053e06bSLiang Chen rockchip,pins = 17957053e06bSLiang Chen <1 RK_PD6 1 &pcfg_pull_none_8ma>; 17967053e06bSLiang Chen }; 17977053e06bSLiang Chen 17987053e06bSLiang Chen sdmmc_cmd: sdmmc-cmd { 17997053e06bSLiang Chen rockchip,pins = 18007053e06bSLiang Chen <1 RK_PD7 1 &pcfg_pull_up_8ma>; 18017053e06bSLiang Chen }; 18027053e06bSLiang Chen 18037053e06bSLiang Chen sdmmc_det: sdmmc-det { 18047053e06bSLiang Chen rockchip,pins = 18057053e06bSLiang Chen <0 RK_PA3 1 &pcfg_pull_up_8ma>; 18067053e06bSLiang Chen }; 18077053e06bSLiang Chen 18087053e06bSLiang Chen sdmmc_bus1: sdmmc-bus1 { 18097053e06bSLiang Chen rockchip,pins = 18107053e06bSLiang Chen <1 RK_PD2 1 &pcfg_pull_up_8ma>; 18117053e06bSLiang Chen }; 18127053e06bSLiang Chen 18137053e06bSLiang Chen sdmmc_bus4: sdmmc-bus4 { 18147053e06bSLiang Chen rockchip,pins = 18157053e06bSLiang Chen <1 RK_PD2 1 &pcfg_pull_up_8ma>, 18167053e06bSLiang Chen <1 RK_PD3 1 &pcfg_pull_up_8ma>, 18177053e06bSLiang Chen <1 RK_PD4 1 &pcfg_pull_up_8ma>, 18187053e06bSLiang Chen <1 RK_PD5 1 &pcfg_pull_up_8ma>; 18197053e06bSLiang Chen }; 18207053e06bSLiang Chen }; 18217053e06bSLiang Chen 18227053e06bSLiang Chen sdio { 18237053e06bSLiang Chen sdio_clk: sdio-clk { 18247053e06bSLiang Chen rockchip,pins = 18257053e06bSLiang Chen <1 RK_PC5 1 &pcfg_pull_none>; 18267053e06bSLiang Chen }; 18277053e06bSLiang Chen 18287053e06bSLiang Chen sdio_cmd: sdio-cmd { 18297053e06bSLiang Chen rockchip,pins = 18307053e06bSLiang Chen <1 RK_PC4 1 &pcfg_pull_up>; 18317053e06bSLiang Chen }; 18327053e06bSLiang Chen 18337053e06bSLiang Chen sdio_bus4: sdio-bus4 { 18347053e06bSLiang Chen rockchip,pins = 18357053e06bSLiang Chen <1 RK_PC6 1 &pcfg_pull_up>, 18367053e06bSLiang Chen <1 RK_PC7 1 &pcfg_pull_up>, 18377053e06bSLiang Chen <1 RK_PD0 1 &pcfg_pull_up>, 18387053e06bSLiang Chen <1 RK_PD1 1 &pcfg_pull_up>; 18397053e06bSLiang Chen }; 18407053e06bSLiang Chen }; 18417053e06bSLiang Chen 18427053e06bSLiang Chen emmc { 18437053e06bSLiang Chen emmc_clk: emmc-clk { 18447053e06bSLiang Chen rockchip,pins = 18457053e06bSLiang Chen <1 RK_PB1 2 &pcfg_pull_none_8ma>; 18467053e06bSLiang Chen }; 18477053e06bSLiang Chen 18487053e06bSLiang Chen emmc_cmd: emmc-cmd { 18497053e06bSLiang Chen rockchip,pins = 18507053e06bSLiang Chen <1 RK_PB2 2 &pcfg_pull_up_8ma>; 18517053e06bSLiang Chen }; 18527053e06bSLiang Chen 18537053e06bSLiang Chen emmc_rstnout: emmc-rstnout { 18547053e06bSLiang Chen rockchip,pins = 18557053e06bSLiang Chen <1 RK_PB3 2 &pcfg_pull_none>; 18567053e06bSLiang Chen }; 18577053e06bSLiang Chen 18587053e06bSLiang Chen emmc_bus1: emmc-bus1 { 18597053e06bSLiang Chen rockchip,pins = 18607053e06bSLiang Chen <1 RK_PA0 2 &pcfg_pull_up_8ma>; 18617053e06bSLiang Chen }; 18627053e06bSLiang Chen 18637053e06bSLiang Chen emmc_bus4: emmc-bus4 { 18647053e06bSLiang Chen rockchip,pins = 18657053e06bSLiang Chen <1 RK_PA0 2 &pcfg_pull_up_8ma>, 18667053e06bSLiang Chen <1 RK_PA1 2 &pcfg_pull_up_8ma>, 18677053e06bSLiang Chen <1 RK_PA2 2 &pcfg_pull_up_8ma>, 18687053e06bSLiang Chen <1 RK_PA3 2 &pcfg_pull_up_8ma>; 18697053e06bSLiang Chen }; 18707053e06bSLiang Chen 18717053e06bSLiang Chen emmc_bus8: emmc-bus8 { 18727053e06bSLiang Chen rockchip,pins = 18737053e06bSLiang Chen <1 RK_PA0 2 &pcfg_pull_up_8ma>, 18747053e06bSLiang Chen <1 RK_PA1 2 &pcfg_pull_up_8ma>, 18757053e06bSLiang Chen <1 RK_PA2 2 &pcfg_pull_up_8ma>, 18767053e06bSLiang Chen <1 RK_PA3 2 &pcfg_pull_up_8ma>, 18777053e06bSLiang Chen <1 RK_PA4 2 &pcfg_pull_up_8ma>, 18787053e06bSLiang Chen <1 RK_PA5 2 &pcfg_pull_up_8ma>, 18797053e06bSLiang Chen <1 RK_PA6 2 &pcfg_pull_up_8ma>, 18807053e06bSLiang Chen <1 RK_PA7 2 &pcfg_pull_up_8ma>; 18817053e06bSLiang Chen }; 18827053e06bSLiang Chen }; 18837053e06bSLiang Chen 18847053e06bSLiang Chen flash { 18857053e06bSLiang Chen flash_cs0: flash-cs0 { 18867053e06bSLiang Chen rockchip,pins = 18877053e06bSLiang Chen <1 RK_PB0 1 &pcfg_pull_none>; 18887053e06bSLiang Chen }; 18897053e06bSLiang Chen 18907053e06bSLiang Chen flash_rdy: flash-rdy { 18917053e06bSLiang Chen rockchip,pins = 18927053e06bSLiang Chen <1 RK_PB1 1 &pcfg_pull_none>; 18937053e06bSLiang Chen }; 18947053e06bSLiang Chen 18957053e06bSLiang Chen flash_dqs: flash-dqs { 18967053e06bSLiang Chen rockchip,pins = 18977053e06bSLiang Chen <1 RK_PB2 1 &pcfg_pull_none>; 18987053e06bSLiang Chen }; 18997053e06bSLiang Chen 19007053e06bSLiang Chen flash_ale: flash-ale { 19017053e06bSLiang Chen rockchip,pins = 19027053e06bSLiang Chen <1 RK_PB3 1 &pcfg_pull_none>; 19037053e06bSLiang Chen }; 19047053e06bSLiang Chen 19057053e06bSLiang Chen flash_cle: flash-cle { 19067053e06bSLiang Chen rockchip,pins = 19077053e06bSLiang Chen <1 RK_PB4 1 &pcfg_pull_none>; 19087053e06bSLiang Chen }; 19097053e06bSLiang Chen 19107053e06bSLiang Chen flash_wrn: flash-wrn { 19117053e06bSLiang Chen rockchip,pins = 19127053e06bSLiang Chen <1 RK_PB5 1 &pcfg_pull_none>; 19137053e06bSLiang Chen }; 19147053e06bSLiang Chen 19157053e06bSLiang Chen flash_csl: flash-csl { 19167053e06bSLiang Chen rockchip,pins = 19177053e06bSLiang Chen <1 RK_PB6 1 &pcfg_pull_none>; 19187053e06bSLiang Chen }; 19197053e06bSLiang Chen 19207053e06bSLiang Chen flash_rdn: flash-rdn { 19217053e06bSLiang Chen rockchip,pins = 19227053e06bSLiang Chen <1 RK_PB7 1 &pcfg_pull_none>; 19237053e06bSLiang Chen }; 19247053e06bSLiang Chen 19257053e06bSLiang Chen flash_bus8: flash-bus8 { 19267053e06bSLiang Chen rockchip,pins = 19277053e06bSLiang Chen <1 RK_PA0 1 &pcfg_pull_up_12ma>, 19287053e06bSLiang Chen <1 RK_PA1 1 &pcfg_pull_up_12ma>, 19297053e06bSLiang Chen <1 RK_PA2 1 &pcfg_pull_up_12ma>, 19307053e06bSLiang Chen <1 RK_PA3 1 &pcfg_pull_up_12ma>, 19317053e06bSLiang Chen <1 RK_PA4 1 &pcfg_pull_up_12ma>, 19327053e06bSLiang Chen <1 RK_PA5 1 &pcfg_pull_up_12ma>, 19337053e06bSLiang Chen <1 RK_PA6 1 &pcfg_pull_up_12ma>, 19347053e06bSLiang Chen <1 RK_PA7 1 &pcfg_pull_up_12ma>; 19357053e06bSLiang Chen }; 19367053e06bSLiang Chen }; 19377053e06bSLiang Chen 19387053e06bSLiang Chen lcdc { 19397053e06bSLiang Chen lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 19407053e06bSLiang Chen rockchip,pins = 19417053e06bSLiang Chen <3 RK_PA0 1 &pcfg_pull_none_12ma>; 19427053e06bSLiang Chen }; 19437053e06bSLiang Chen 19447053e06bSLiang Chen lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 19457053e06bSLiang Chen rockchip,pins = 19467053e06bSLiang Chen <3 RK_PA1 1 &pcfg_pull_none_12ma>; 19477053e06bSLiang Chen }; 19487053e06bSLiang Chen 19497053e06bSLiang Chen lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 19507053e06bSLiang Chen rockchip,pins = 19517053e06bSLiang Chen <3 RK_PA2 1 &pcfg_pull_none_12ma>; 19527053e06bSLiang Chen }; 19537053e06bSLiang Chen 19547053e06bSLiang Chen lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 19557053e06bSLiang Chen rockchip,pins = 19567053e06bSLiang Chen <3 RK_PA3 1 &pcfg_pull_none_12ma>; 19577053e06bSLiang Chen }; 19587053e06bSLiang Chen 19597053e06bSLiang Chen lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 19607053e06bSLiang Chen rockchip,pins = 19617053e06bSLiang Chen <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 19627053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 19637053e06bSLiang Chen <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 19647053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 19657053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 19667053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 19677053e06bSLiang Chen <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 19687053e06bSLiang Chen <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 19697053e06bSLiang Chen <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 19707053e06bSLiang Chen <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 19717053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 19727053e06bSLiang Chen <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 19737053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 19747053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 19757053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 19767053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 19777053e06bSLiang Chen <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 19787053e06bSLiang Chen <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 19797053e06bSLiang Chen <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 19807053e06bSLiang Chen <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 19817053e06bSLiang Chen <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 19827053e06bSLiang Chen <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 19837053e06bSLiang Chen <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 19847053e06bSLiang Chen <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 19857053e06bSLiang Chen }; 19867053e06bSLiang Chen 19877053e06bSLiang Chen lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 19887053e06bSLiang Chen rockchip,pins = 19897053e06bSLiang Chen <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 19907053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 19917053e06bSLiang Chen <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 19927053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 19937053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 19947053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 19957053e06bSLiang Chen <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 19967053e06bSLiang Chen <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 19977053e06bSLiang Chen <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 19987053e06bSLiang Chen <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 19997053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20007053e06bSLiang Chen <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 20017053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20027053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20037053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20047053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 20057053e06bSLiang Chen <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 20067053e06bSLiang Chen <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 20077053e06bSLiang Chen }; 20087053e06bSLiang Chen 20097053e06bSLiang Chen lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 20107053e06bSLiang Chen rockchip,pins = 20117053e06bSLiang Chen <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 20127053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20137053e06bSLiang Chen <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 20147053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20157053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20167053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20177053e06bSLiang Chen <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 20187053e06bSLiang Chen <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 20197053e06bSLiang Chen <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 20207053e06bSLiang Chen <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 20217053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20227053e06bSLiang Chen <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 20237053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20247053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20257053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20267053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 20277053e06bSLiang Chen }; 20287053e06bSLiang Chen 20297053e06bSLiang Chen lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 20307053e06bSLiang Chen rockchip,pins = 20317053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20327053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20337053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20347053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20357053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20367053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20377053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20387053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20397053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 20407053e06bSLiang Chen <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 20417053e06bSLiang Chen <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 20427053e06bSLiang Chen <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 20437053e06bSLiang Chen <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 20447053e06bSLiang Chen <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 20457053e06bSLiang Chen <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 20467053e06bSLiang Chen <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 20477053e06bSLiang Chen <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 20487053e06bSLiang Chen }; 20497053e06bSLiang Chen 20507053e06bSLiang Chen lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 20517053e06bSLiang Chen rockchip,pins = 20527053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20537053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20547053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20557053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20567053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20577053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20587053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20597053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20607053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 20617053e06bSLiang Chen <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 20627053e06bSLiang Chen <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 20637053e06bSLiang Chen }; 20647053e06bSLiang Chen 20657053e06bSLiang Chen lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 20667053e06bSLiang Chen rockchip,pins = 20677053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20687053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20697053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20707053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20717053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20727053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20737053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20747053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20757053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 20767053e06bSLiang Chen }; 20777053e06bSLiang Chen }; 20787053e06bSLiang Chen 20797053e06bSLiang Chen pwm0 { 20807053e06bSLiang Chen pwm0_pin: pwm0-pin { 20817053e06bSLiang Chen rockchip,pins = 20827053e06bSLiang Chen <0 RK_PB7 1 &pcfg_pull_none>; 20837053e06bSLiang Chen }; 20847053e06bSLiang Chen }; 20857053e06bSLiang Chen 20867053e06bSLiang Chen pwm1 { 20877053e06bSLiang Chen pwm1_pin: pwm1-pin { 20887053e06bSLiang Chen rockchip,pins = 20897053e06bSLiang Chen <0 RK_PC0 1 &pcfg_pull_none>; 20907053e06bSLiang Chen }; 20917053e06bSLiang Chen }; 20927053e06bSLiang Chen 20937053e06bSLiang Chen pwm2 { 20947053e06bSLiang Chen pwm2_pin: pwm2-pin { 20957053e06bSLiang Chen rockchip,pins = 20967053e06bSLiang Chen <2 RK_PB5 1 &pcfg_pull_none>; 20977053e06bSLiang Chen }; 20987053e06bSLiang Chen }; 20997053e06bSLiang Chen 21007053e06bSLiang Chen pwm3 { 21017053e06bSLiang Chen pwm3_pin: pwm3-pin { 21027053e06bSLiang Chen rockchip,pins = 21037053e06bSLiang Chen <0 RK_PC1 1 &pcfg_pull_none>; 21047053e06bSLiang Chen }; 21057053e06bSLiang Chen }; 21067053e06bSLiang Chen 21077053e06bSLiang Chen pwm4 { 21087053e06bSLiang Chen pwm4_pin: pwm4-pin { 21097053e06bSLiang Chen rockchip,pins = 21107053e06bSLiang Chen <3 RK_PC2 3 &pcfg_pull_none>; 21117053e06bSLiang Chen }; 21127053e06bSLiang Chen }; 21137053e06bSLiang Chen 21147053e06bSLiang Chen pwm5 { 21157053e06bSLiang Chen pwm5_pin: pwm5-pin { 21167053e06bSLiang Chen rockchip,pins = 21177053e06bSLiang Chen <3 RK_PC3 3 &pcfg_pull_none>; 21187053e06bSLiang Chen }; 21197053e06bSLiang Chen }; 21207053e06bSLiang Chen 21217053e06bSLiang Chen pwm6 { 21227053e06bSLiang Chen pwm6_pin: pwm6-pin { 21237053e06bSLiang Chen rockchip,pins = 21247053e06bSLiang Chen <3 RK_PC4 3 &pcfg_pull_none>; 21257053e06bSLiang Chen }; 21267053e06bSLiang Chen }; 21277053e06bSLiang Chen 21287053e06bSLiang Chen pwm7 { 21297053e06bSLiang Chen pwm7_pin: pwm7-pin { 21307053e06bSLiang Chen rockchip,pins = 21317053e06bSLiang Chen <3 RK_PC5 3 &pcfg_pull_none>; 21327053e06bSLiang Chen }; 21337053e06bSLiang Chen }; 21347053e06bSLiang Chen 21357053e06bSLiang Chen gmac { 21367053e06bSLiang Chen rmii_pins: rmii-pins { 21377053e06bSLiang Chen rockchip,pins = 21387053e06bSLiang Chen <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 21397053e06bSLiang Chen <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 21407053e06bSLiang Chen <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 21417053e06bSLiang Chen <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 21427053e06bSLiang Chen <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 21437053e06bSLiang Chen <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 21447053e06bSLiang Chen <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 21457053e06bSLiang Chen <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 21467053e06bSLiang Chen <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 21477053e06bSLiang Chen }; 21487053e06bSLiang Chen 21497053e06bSLiang Chen mac_refclk_12ma: mac-refclk-12ma { 21507053e06bSLiang Chen rockchip,pins = 21517053e06bSLiang Chen <2 RK_PB2 2 &pcfg_pull_none_12ma>; 21527053e06bSLiang Chen }; 21537053e06bSLiang Chen 21547053e06bSLiang Chen mac_refclk: mac-refclk { 21557053e06bSLiang Chen rockchip,pins = 21567053e06bSLiang Chen <2 RK_PB2 2 &pcfg_pull_none>; 21577053e06bSLiang Chen }; 21587053e06bSLiang Chen }; 21597053e06bSLiang Chen 21607053e06bSLiang Chen cif-m0 { 21617053e06bSLiang Chen cif_clkout_m0: cif-clkout-m0 { 21627053e06bSLiang Chen rockchip,pins = 21637053e06bSLiang Chen <2 RK_PB3 1 &pcfg_pull_none>; 21647053e06bSLiang Chen }; 21657053e06bSLiang Chen 21667053e06bSLiang Chen dvp_d2d9_m0: dvp-d2d9-m0 { 21677053e06bSLiang Chen rockchip,pins = 21687053e06bSLiang Chen <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 21697053e06bSLiang Chen <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 21707053e06bSLiang Chen <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 21717053e06bSLiang Chen <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 21727053e06bSLiang Chen <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 21737053e06bSLiang Chen <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 21747053e06bSLiang Chen <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 21757053e06bSLiang Chen <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 21767053e06bSLiang Chen <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 21777053e06bSLiang Chen <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 21787053e06bSLiang Chen <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 21797053e06bSLiang Chen <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 21807053e06bSLiang Chen }; 21817053e06bSLiang Chen 21827053e06bSLiang Chen dvp_d0d1_m0: dvp-d0d1-m0 { 21837053e06bSLiang Chen rockchip,pins = 21847053e06bSLiang Chen <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 21857053e06bSLiang Chen <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 21867053e06bSLiang Chen }; 21877053e06bSLiang Chen 21887053e06bSLiang Chen dvp_d10d11_m0:d10-d11-m0 { 21897053e06bSLiang Chen rockchip,pins = 21907053e06bSLiang Chen <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 21917053e06bSLiang Chen <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 21927053e06bSLiang Chen }; 21937053e06bSLiang Chen }; 21947053e06bSLiang Chen 21957053e06bSLiang Chen cif-m1 { 21967053e06bSLiang Chen cif_clkout_m1: cif-clkout-m1 { 21977053e06bSLiang Chen rockchip,pins = 21987053e06bSLiang Chen <3 RK_PD0 3 &pcfg_pull_none>; 21997053e06bSLiang Chen }; 22007053e06bSLiang Chen 22017053e06bSLiang Chen dvp_d2d9_m1: dvp-d2d9-m1 { 22027053e06bSLiang Chen rockchip,pins = 22037053e06bSLiang Chen <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 22047053e06bSLiang Chen <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 22057053e06bSLiang Chen <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 22067053e06bSLiang Chen <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 22077053e06bSLiang Chen <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 22087053e06bSLiang Chen <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 22097053e06bSLiang Chen <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 22107053e06bSLiang Chen <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 22117053e06bSLiang Chen <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 22127053e06bSLiang Chen <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 22137053e06bSLiang Chen <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 22147053e06bSLiang Chen <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 22157053e06bSLiang Chen }; 22167053e06bSLiang Chen 22177053e06bSLiang Chen dvp_d0d1_m1: dvp-d0d1-m1 { 22187053e06bSLiang Chen rockchip,pins = 22197053e06bSLiang Chen <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 22207053e06bSLiang Chen <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 22217053e06bSLiang Chen }; 22227053e06bSLiang Chen 22237053e06bSLiang Chen dvp_d10d11_m1:d10-d11-m1 { 22247053e06bSLiang Chen rockchip,pins = 22257053e06bSLiang Chen <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 22267053e06bSLiang Chen <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 22277053e06bSLiang Chen }; 22287053e06bSLiang Chen }; 22297053e06bSLiang Chen 22307053e06bSLiang Chen isp { 22317053e06bSLiang Chen isp_prelight: isp-prelight { 22327053e06bSLiang Chen rockchip,pins = 22337053e06bSLiang Chen <3 RK_PD1 4 &pcfg_pull_none>; 22347053e06bSLiang Chen }; 22357053e06bSLiang Chen }; 22367053e06bSLiang Chen }; 22377053e06bSLiang Chen}; 2238