17053e06bSLiang Chen// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 27053e06bSLiang Chen/* 37053e06bSLiang Chen * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 47053e06bSLiang Chen */ 57053e06bSLiang Chen 67053e06bSLiang Chen#include <dt-bindings/clock/px30-cru.h> 77053e06bSLiang Chen#include <dt-bindings/gpio/gpio.h> 87053e06bSLiang Chen#include <dt-bindings/interrupt-controller/arm-gic.h> 97053e06bSLiang Chen#include <dt-bindings/interrupt-controller/irq.h> 107053e06bSLiang Chen#include <dt-bindings/pinctrl/rockchip.h> 117053e06bSLiang Chen#include <dt-bindings/power/px30-power.h> 127053e06bSLiang Chen#include <dt-bindings/soc/rockchip,boot-mode.h> 13023115cdSHeiko Stuebner#include <dt-bindings/thermal/thermal.h> 147053e06bSLiang Chen 157053e06bSLiang Chen/ { 167053e06bSLiang Chen compatible = "rockchip,px30"; 177053e06bSLiang Chen 187053e06bSLiang Chen interrupt-parent = <&gic>; 197053e06bSLiang Chen #address-cells = <2>; 207053e06bSLiang Chen #size-cells = <2>; 217053e06bSLiang Chen 227053e06bSLiang Chen aliases { 237053e06bSLiang Chen ethernet0 = &gmac; 247053e06bSLiang Chen i2c0 = &i2c0; 257053e06bSLiang Chen i2c1 = &i2c1; 267053e06bSLiang Chen i2c2 = &i2c2; 277053e06bSLiang Chen i2c3 = &i2c3; 28*84b2c2c8SJohan Jonker mmc0 = &sdmmc; 29*84b2c2c8SJohan Jonker mmc1 = &sdio; 30*84b2c2c8SJohan Jonker mmc2 = &emmc; 317053e06bSLiang Chen serial0 = &uart0; 327053e06bSLiang Chen serial1 = &uart1; 337053e06bSLiang Chen serial2 = &uart2; 347053e06bSLiang Chen serial3 = &uart3; 357053e06bSLiang Chen serial4 = &uart4; 367053e06bSLiang Chen serial5 = &uart5; 377053e06bSLiang Chen spi0 = &spi0; 387053e06bSLiang Chen spi1 = &spi1; 397053e06bSLiang Chen }; 407053e06bSLiang Chen 417053e06bSLiang Chen cpus { 427053e06bSLiang Chen #address-cells = <2>; 437053e06bSLiang Chen #size-cells = <0>; 447053e06bSLiang Chen 457053e06bSLiang Chen cpu0: cpu@0 { 467053e06bSLiang Chen device_type = "cpu"; 4731af04cdSRob Herring compatible = "arm,cortex-a35"; 487053e06bSLiang Chen reg = <0x0 0x0>; 497053e06bSLiang Chen enable-method = "psci"; 507053e06bSLiang Chen clocks = <&cru ARMCLK>; 517053e06bSLiang Chen #cooling-cells = <2>; 527053e06bSLiang Chen cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 537053e06bSLiang Chen dynamic-power-coefficient = <90>; 547053e06bSLiang Chen operating-points-v2 = <&cpu0_opp_table>; 557053e06bSLiang Chen }; 567053e06bSLiang Chen 577053e06bSLiang Chen cpu1: cpu@1 { 587053e06bSLiang Chen device_type = "cpu"; 5931af04cdSRob Herring compatible = "arm,cortex-a35"; 607053e06bSLiang Chen reg = <0x0 0x1>; 617053e06bSLiang Chen enable-method = "psci"; 627053e06bSLiang Chen clocks = <&cru ARMCLK>; 637053e06bSLiang Chen #cooling-cells = <2>; 647053e06bSLiang Chen cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 657053e06bSLiang Chen dynamic-power-coefficient = <90>; 667053e06bSLiang Chen operating-points-v2 = <&cpu0_opp_table>; 677053e06bSLiang Chen }; 687053e06bSLiang Chen 697053e06bSLiang Chen cpu2: cpu@2 { 707053e06bSLiang Chen device_type = "cpu"; 7131af04cdSRob Herring compatible = "arm,cortex-a35"; 727053e06bSLiang Chen reg = <0x0 0x2>; 737053e06bSLiang Chen enable-method = "psci"; 747053e06bSLiang Chen clocks = <&cru ARMCLK>; 757053e06bSLiang Chen #cooling-cells = <2>; 767053e06bSLiang Chen cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 777053e06bSLiang Chen dynamic-power-coefficient = <90>; 787053e06bSLiang Chen operating-points-v2 = <&cpu0_opp_table>; 797053e06bSLiang Chen }; 807053e06bSLiang Chen 817053e06bSLiang Chen cpu3: cpu@3 { 827053e06bSLiang Chen device_type = "cpu"; 8331af04cdSRob Herring compatible = "arm,cortex-a35"; 847053e06bSLiang Chen reg = <0x0 0x3>; 857053e06bSLiang Chen enable-method = "psci"; 867053e06bSLiang Chen clocks = <&cru ARMCLK>; 877053e06bSLiang Chen #cooling-cells = <2>; 887053e06bSLiang Chen cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 897053e06bSLiang Chen dynamic-power-coefficient = <90>; 907053e06bSLiang Chen operating-points-v2 = <&cpu0_opp_table>; 917053e06bSLiang Chen }; 927053e06bSLiang Chen 937053e06bSLiang Chen idle-states { 947053e06bSLiang Chen entry-method = "psci"; 957053e06bSLiang Chen 967053e06bSLiang Chen CPU_SLEEP: cpu-sleep { 977053e06bSLiang Chen compatible = "arm,idle-state"; 987053e06bSLiang Chen local-timer-stop; 997053e06bSLiang Chen arm,psci-suspend-param = <0x0010000>; 1007053e06bSLiang Chen entry-latency-us = <120>; 1017053e06bSLiang Chen exit-latency-us = <250>; 1027053e06bSLiang Chen min-residency-us = <900>; 1037053e06bSLiang Chen }; 1047053e06bSLiang Chen 1057053e06bSLiang Chen CLUSTER_SLEEP: cluster-sleep { 1067053e06bSLiang Chen compatible = "arm,idle-state"; 1077053e06bSLiang Chen local-timer-stop; 1087053e06bSLiang Chen arm,psci-suspend-param = <0x1010000>; 1097053e06bSLiang Chen entry-latency-us = <400>; 1107053e06bSLiang Chen exit-latency-us = <500>; 1117053e06bSLiang Chen min-residency-us = <2000>; 1127053e06bSLiang Chen }; 1137053e06bSLiang Chen }; 1147053e06bSLiang Chen }; 1157053e06bSLiang Chen 1167053e06bSLiang Chen cpu0_opp_table: cpu0-opp-table { 1177053e06bSLiang Chen compatible = "operating-points-v2"; 1187053e06bSLiang Chen opp-shared; 1197053e06bSLiang Chen 1207053e06bSLiang Chen opp-600000000 { 1217053e06bSLiang Chen opp-hz = /bits/ 64 <600000000>; 1227053e06bSLiang Chen opp-microvolt = <950000 950000 1350000>; 1237053e06bSLiang Chen clock-latency-ns = <40000>; 1248554723eSHeiko Stuebner opp-suspend; 1257053e06bSLiang Chen }; 1267053e06bSLiang Chen opp-816000000 { 1277053e06bSLiang Chen opp-hz = /bits/ 64 <816000000>; 1287053e06bSLiang Chen opp-microvolt = <1050000 1050000 1350000>; 1297053e06bSLiang Chen clock-latency-ns = <40000>; 1307053e06bSLiang Chen }; 1317053e06bSLiang Chen opp-1008000000 { 1327053e06bSLiang Chen opp-hz = /bits/ 64 <1008000000>; 1337053e06bSLiang Chen opp-microvolt = <1175000 1175000 1350000>; 1347053e06bSLiang Chen clock-latency-ns = <40000>; 1357053e06bSLiang Chen }; 1367053e06bSLiang Chen opp-1200000000 { 1377053e06bSLiang Chen opp-hz = /bits/ 64 <1200000000>; 1387053e06bSLiang Chen opp-microvolt = <1300000 1300000 1350000>; 1397053e06bSLiang Chen clock-latency-ns = <40000>; 1407053e06bSLiang Chen }; 1417053e06bSLiang Chen opp-1296000000 { 1427053e06bSLiang Chen opp-hz = /bits/ 64 <1296000000>; 1437053e06bSLiang Chen opp-microvolt = <1350000 1350000 1350000>; 1447053e06bSLiang Chen clock-latency-ns = <40000>; 1457053e06bSLiang Chen }; 1467053e06bSLiang Chen }; 1477053e06bSLiang Chen 1487053e06bSLiang Chen arm-pmu { 1495944eb7aSRobin Murphy compatible = "arm,cortex-a35-pmu"; 1507053e06bSLiang Chen interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1517053e06bSLiang Chen <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1527053e06bSLiang Chen <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1537053e06bSLiang Chen <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1547053e06bSLiang Chen interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1557053e06bSLiang Chen }; 1567053e06bSLiang Chen 1577053e06bSLiang Chen display_subsystem: display-subsystem { 1587053e06bSLiang Chen compatible = "rockchip,display-subsystem"; 159967c1464SSandy Huang ports = <&vopb_out>, <&vopl_out>; 1607053e06bSLiang Chen status = "disabled"; 1617053e06bSLiang Chen }; 1627053e06bSLiang Chen 1637053e06bSLiang Chen gmac_clkin: external-gmac-clock { 1647053e06bSLiang Chen compatible = "fixed-clock"; 1657053e06bSLiang Chen clock-frequency = <50000000>; 1667053e06bSLiang Chen clock-output-names = "gmac_clkin"; 1677053e06bSLiang Chen #clock-cells = <0>; 1687053e06bSLiang Chen }; 1697053e06bSLiang Chen 1707053e06bSLiang Chen psci { 1717053e06bSLiang Chen compatible = "arm,psci-1.0"; 1727053e06bSLiang Chen method = "smc"; 1737053e06bSLiang Chen }; 1747053e06bSLiang Chen 1757053e06bSLiang Chen timer { 1767053e06bSLiang Chen compatible = "arm,armv8-timer"; 1777053e06bSLiang Chen interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1787053e06bSLiang Chen <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1797053e06bSLiang Chen <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 1807053e06bSLiang Chen <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1817053e06bSLiang Chen }; 1827053e06bSLiang Chen 183023115cdSHeiko Stuebner thermal_zones: thermal-zones { 184023115cdSHeiko Stuebner soc_thermal: soc-thermal { 185023115cdSHeiko Stuebner polling-delay-passive = <20>; 186023115cdSHeiko Stuebner polling-delay = <1000>; 187023115cdSHeiko Stuebner sustainable-power = <750>; 188023115cdSHeiko Stuebner thermal-sensors = <&tsadc 0>; 189023115cdSHeiko Stuebner 190023115cdSHeiko Stuebner trips { 191023115cdSHeiko Stuebner threshold: trip-point-0 { 192023115cdSHeiko Stuebner temperature = <70000>; 193023115cdSHeiko Stuebner hysteresis = <2000>; 194023115cdSHeiko Stuebner type = "passive"; 195023115cdSHeiko Stuebner }; 196023115cdSHeiko Stuebner 197023115cdSHeiko Stuebner target: trip-point-1 { 198023115cdSHeiko Stuebner temperature = <85000>; 199023115cdSHeiko Stuebner hysteresis = <2000>; 200023115cdSHeiko Stuebner type = "passive"; 201023115cdSHeiko Stuebner }; 202023115cdSHeiko Stuebner 203023115cdSHeiko Stuebner soc_crit: soc-crit { 204023115cdSHeiko Stuebner temperature = <115000>; 205023115cdSHeiko Stuebner hysteresis = <2000>; 206023115cdSHeiko Stuebner type = "critical"; 207023115cdSHeiko Stuebner }; 208023115cdSHeiko Stuebner }; 209023115cdSHeiko Stuebner 210023115cdSHeiko Stuebner cooling-maps { 211023115cdSHeiko Stuebner map0 { 212023115cdSHeiko Stuebner trip = <&target>; 213023115cdSHeiko Stuebner cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 214023115cdSHeiko Stuebner contribution = <4096>; 215023115cdSHeiko Stuebner }; 216a07f34a0SHeiko Stuebner 217a07f34a0SHeiko Stuebner map1 { 218a07f34a0SHeiko Stuebner trip = <&target>; 219a07f34a0SHeiko Stuebner cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 220a07f34a0SHeiko Stuebner contribution = <4096>; 221a07f34a0SHeiko Stuebner }; 222023115cdSHeiko Stuebner }; 223023115cdSHeiko Stuebner }; 224023115cdSHeiko Stuebner 225023115cdSHeiko Stuebner gpu_thermal: gpu-thermal { 226023115cdSHeiko Stuebner polling-delay-passive = <100>; /* milliseconds */ 227023115cdSHeiko Stuebner polling-delay = <1000>; /* milliseconds */ 228023115cdSHeiko Stuebner thermal-sensors = <&tsadc 1>; 229023115cdSHeiko Stuebner }; 230023115cdSHeiko Stuebner }; 231023115cdSHeiko Stuebner 2327053e06bSLiang Chen xin24m: xin24m { 2337053e06bSLiang Chen compatible = "fixed-clock"; 2347053e06bSLiang Chen #clock-cells = <0>; 2357053e06bSLiang Chen clock-frequency = <24000000>; 2367053e06bSLiang Chen clock-output-names = "xin24m"; 2377053e06bSLiang Chen }; 2387053e06bSLiang Chen 2397053e06bSLiang Chen pmu: power-management@ff000000 { 2407053e06bSLiang Chen compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 2417053e06bSLiang Chen reg = <0x0 0xff000000 0x0 0x1000>; 2427053e06bSLiang Chen 2437053e06bSLiang Chen power: power-controller { 2447053e06bSLiang Chen compatible = "rockchip,px30-power-controller"; 2457053e06bSLiang Chen #power-domain-cells = <1>; 2467053e06bSLiang Chen #address-cells = <1>; 2477053e06bSLiang Chen #size-cells = <0>; 2487053e06bSLiang Chen 2497053e06bSLiang Chen /* These power domains are grouped by VD_LOGIC */ 2507053e06bSLiang Chen pd_usb@PX30_PD_USB { 2517053e06bSLiang Chen reg = <PX30_PD_USB>; 2527053e06bSLiang Chen clocks = <&cru HCLK_HOST>, 2537053e06bSLiang Chen <&cru HCLK_OTG>, 2547053e06bSLiang Chen <&cru SCLK_OTG_ADP>; 2557053e06bSLiang Chen pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 2567053e06bSLiang Chen }; 2577053e06bSLiang Chen pd_sdcard@PX30_PD_SDCARD { 2587053e06bSLiang Chen reg = <PX30_PD_SDCARD>; 2597053e06bSLiang Chen clocks = <&cru HCLK_SDMMC>, 2607053e06bSLiang Chen <&cru SCLK_SDMMC>; 2617053e06bSLiang Chen pm_qos = <&qos_sdmmc>; 2627053e06bSLiang Chen }; 2637053e06bSLiang Chen pd_gmac@PX30_PD_GMAC { 2647053e06bSLiang Chen reg = <PX30_PD_GMAC>; 2657053e06bSLiang Chen clocks = <&cru ACLK_GMAC>, 2667053e06bSLiang Chen <&cru PCLK_GMAC>, 2677053e06bSLiang Chen <&cru SCLK_MAC_REF>, 2687053e06bSLiang Chen <&cru SCLK_GMAC_RX_TX>; 2697053e06bSLiang Chen pm_qos = <&qos_gmac>; 2707053e06bSLiang Chen }; 2717053e06bSLiang Chen pd_mmc_nand@PX30_PD_MMC_NAND { 2727053e06bSLiang Chen reg = <PX30_PD_MMC_NAND>; 2737053e06bSLiang Chen clocks = <&cru HCLK_NANDC>, 2747053e06bSLiang Chen <&cru HCLK_EMMC>, 2757053e06bSLiang Chen <&cru HCLK_SDIO>, 2767053e06bSLiang Chen <&cru HCLK_SFC>, 2777053e06bSLiang Chen <&cru SCLK_EMMC>, 2787053e06bSLiang Chen <&cru SCLK_NANDC>, 2797053e06bSLiang Chen <&cru SCLK_SDIO>, 2807053e06bSLiang Chen <&cru SCLK_SFC>; 2817053e06bSLiang Chen pm_qos = <&qos_emmc>, <&qos_nand>, 2827053e06bSLiang Chen <&qos_sdio>, <&qos_sfc>; 2837053e06bSLiang Chen }; 2847053e06bSLiang Chen pd_vpu@PX30_PD_VPU { 2857053e06bSLiang Chen reg = <PX30_PD_VPU>; 2867053e06bSLiang Chen clocks = <&cru ACLK_VPU>, 2877053e06bSLiang Chen <&cru HCLK_VPU>, 2887053e06bSLiang Chen <&cru SCLK_CORE_VPU>; 2897053e06bSLiang Chen pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 2907053e06bSLiang Chen }; 2917053e06bSLiang Chen pd_vo@PX30_PD_VO { 2927053e06bSLiang Chen reg = <PX30_PD_VO>; 2937053e06bSLiang Chen clocks = <&cru ACLK_RGA>, 2947053e06bSLiang Chen <&cru ACLK_VOPB>, 2957053e06bSLiang Chen <&cru ACLK_VOPL>, 2967053e06bSLiang Chen <&cru DCLK_VOPB>, 2977053e06bSLiang Chen <&cru DCLK_VOPL>, 2987053e06bSLiang Chen <&cru HCLK_RGA>, 2997053e06bSLiang Chen <&cru HCLK_VOPB>, 3007053e06bSLiang Chen <&cru HCLK_VOPL>, 3017053e06bSLiang Chen <&cru PCLK_MIPI_DSI>, 3027053e06bSLiang Chen <&cru SCLK_RGA_CORE>, 3037053e06bSLiang Chen <&cru SCLK_VOPB_PWM>; 3047053e06bSLiang Chen pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 3057053e06bSLiang Chen <&qos_vop_m0>, <&qos_vop_m1>; 3067053e06bSLiang Chen }; 3077053e06bSLiang Chen pd_vi@PX30_PD_VI { 3087053e06bSLiang Chen reg = <PX30_PD_VI>; 3097053e06bSLiang Chen clocks = <&cru ACLK_CIF>, 3107053e06bSLiang Chen <&cru ACLK_ISP>, 3117053e06bSLiang Chen <&cru HCLK_CIF>, 3127053e06bSLiang Chen <&cru HCLK_ISP>, 3137053e06bSLiang Chen <&cru SCLK_ISP>; 3147053e06bSLiang Chen pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 3157053e06bSLiang Chen <&qos_isp_wr>, <&qos_isp_m1>, 3167053e06bSLiang Chen <&qos_vip>; 3177053e06bSLiang Chen }; 3187053e06bSLiang Chen pd_gpu@PX30_PD_GPU { 3197053e06bSLiang Chen reg = <PX30_PD_GPU>; 3207053e06bSLiang Chen clocks = <&cru SCLK_GPU>; 3217053e06bSLiang Chen pm_qos = <&qos_gpu>; 3227053e06bSLiang Chen }; 3237053e06bSLiang Chen }; 3247053e06bSLiang Chen }; 3257053e06bSLiang Chen 3267053e06bSLiang Chen pmugrf: syscon@ff010000 { 3277053e06bSLiang Chen compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 3287053e06bSLiang Chen reg = <0x0 0xff010000 0x0 0x1000>; 3297053e06bSLiang Chen #address-cells = <1>; 3307053e06bSLiang Chen #size-cells = <1>; 3317053e06bSLiang Chen 3327053e06bSLiang Chen pmu_io_domains: io-domains { 3337053e06bSLiang Chen compatible = "rockchip,px30-pmu-io-voltage-domain"; 3347053e06bSLiang Chen status = "disabled"; 3357053e06bSLiang Chen }; 3367053e06bSLiang Chen 3377053e06bSLiang Chen reboot-mode { 3387053e06bSLiang Chen compatible = "syscon-reboot-mode"; 3397053e06bSLiang Chen offset = <0x200>; 3407053e06bSLiang Chen mode-bootloader = <BOOT_BL_DOWNLOAD>; 3417053e06bSLiang Chen mode-fastboot = <BOOT_FASTBOOT>; 3427053e06bSLiang Chen mode-loader = <BOOT_BL_DOWNLOAD>; 3437053e06bSLiang Chen mode-normal = <BOOT_NORMAL>; 3447053e06bSLiang Chen mode-recovery = <BOOT_RECOVERY>; 3457053e06bSLiang Chen }; 3467053e06bSLiang Chen }; 3477053e06bSLiang Chen 3487053e06bSLiang Chen uart0: serial@ff030000 { 3497053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 3507053e06bSLiang Chen reg = <0x0 0xff030000 0x0 0x100>; 3517053e06bSLiang Chen interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 3527053e06bSLiang Chen clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 3537053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 3547053e06bSLiang Chen dmas = <&dmac 0>, <&dmac 1>; 3557053e06bSLiang Chen dma-names = "tx", "rx"; 3567053e06bSLiang Chen reg-shift = <2>; 3577053e06bSLiang Chen reg-io-width = <4>; 3587053e06bSLiang Chen pinctrl-names = "default"; 3597053e06bSLiang Chen pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 3607053e06bSLiang Chen status = "disabled"; 3617053e06bSLiang Chen }; 3627053e06bSLiang Chen 3637053e06bSLiang Chen i2s1_2ch: i2s@ff070000 { 3647053e06bSLiang Chen compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 3657053e06bSLiang Chen reg = <0x0 0xff070000 0x0 0x1000>; 3667053e06bSLiang Chen interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3677053e06bSLiang Chen clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 3687053e06bSLiang Chen clock-names = "i2s_clk", "i2s_hclk"; 3697053e06bSLiang Chen dmas = <&dmac 18>, <&dmac 19>; 3707053e06bSLiang Chen dma-names = "tx", "rx"; 3717053e06bSLiang Chen pinctrl-names = "default"; 3727053e06bSLiang Chen pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 3737053e06bSLiang Chen &i2s1_2ch_sdi &i2s1_2ch_sdo>; 3747053e06bSLiang Chen #sound-dai-cells = <0>; 3757053e06bSLiang Chen status = "disabled"; 3767053e06bSLiang Chen }; 3777053e06bSLiang Chen 3787053e06bSLiang Chen i2s2_2ch: i2s@ff080000 { 3797053e06bSLiang Chen compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 3807053e06bSLiang Chen reg = <0x0 0xff080000 0x0 0x1000>; 3817053e06bSLiang Chen interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3827053e06bSLiang Chen clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 3837053e06bSLiang Chen clock-names = "i2s_clk", "i2s_hclk"; 3847053e06bSLiang Chen dmas = <&dmac 20>, <&dmac 21>; 3857053e06bSLiang Chen dma-names = "tx", "rx"; 3867053e06bSLiang Chen pinctrl-names = "default"; 3877053e06bSLiang Chen pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 3887053e06bSLiang Chen &i2s2_2ch_sdi &i2s2_2ch_sdo>; 3897053e06bSLiang Chen #sound-dai-cells = <0>; 3907053e06bSLiang Chen status = "disabled"; 3917053e06bSLiang Chen }; 3927053e06bSLiang Chen 3937053e06bSLiang Chen gic: interrupt-controller@ff131000 { 3947053e06bSLiang Chen compatible = "arm,gic-400"; 3957053e06bSLiang Chen #interrupt-cells = <3>; 3967053e06bSLiang Chen #address-cells = <0>; 3977053e06bSLiang Chen interrupt-controller; 3987053e06bSLiang Chen reg = <0x0 0xff131000 0 0x1000>, 3997053e06bSLiang Chen <0x0 0xff132000 0 0x2000>, 4007053e06bSLiang Chen <0x0 0xff134000 0 0x2000>, 4017053e06bSLiang Chen <0x0 0xff136000 0 0x2000>; 4027053e06bSLiang Chen interrupts = <GIC_PPI 9 4037053e06bSLiang Chen (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 4047053e06bSLiang Chen }; 4057053e06bSLiang Chen 4067053e06bSLiang Chen grf: syscon@ff140000 { 4077053e06bSLiang Chen compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 4087053e06bSLiang Chen reg = <0x0 0xff140000 0x0 0x1000>; 4097053e06bSLiang Chen #address-cells = <1>; 4107053e06bSLiang Chen #size-cells = <1>; 4117053e06bSLiang Chen 4127053e06bSLiang Chen io_domains: io-domains { 4137053e06bSLiang Chen compatible = "rockchip,px30-io-voltage-domain"; 4147053e06bSLiang Chen status = "disabled"; 4157053e06bSLiang Chen }; 416dbb6f778SMiquel Raynal 417dbb6f778SMiquel Raynal lvds: lvds { 418dbb6f778SMiquel Raynal compatible = "rockchip,px30-lvds"; 419dbb6f778SMiquel Raynal phys = <&dsi_dphy>; 420dbb6f778SMiquel Raynal phy-names = "dphy"; 421dbb6f778SMiquel Raynal rockchip,grf = <&grf>; 422dbb6f778SMiquel Raynal rockchip,output = "lvds"; 423dbb6f778SMiquel Raynal status = "disabled"; 424dbb6f778SMiquel Raynal 425186444c1SHeiko Stuebner ports { 426186444c1SHeiko Stuebner #address-cells = <1>; 427186444c1SHeiko Stuebner #size-cells = <0>; 428186444c1SHeiko Stuebner 429dbb6f778SMiquel Raynal port@0 { 430dbb6f778SMiquel Raynal reg = <0>; 431dbb6f778SMiquel Raynal #address-cells = <1>; 432dbb6f778SMiquel Raynal #size-cells = <0>; 433dbb6f778SMiquel Raynal 434dbb6f778SMiquel Raynal lvds_vopb_in: endpoint@0 { 435dbb6f778SMiquel Raynal reg = <0>; 436dbb6f778SMiquel Raynal remote-endpoint = <&vopb_out_lvds>; 437dbb6f778SMiquel Raynal }; 438dbb6f778SMiquel Raynal 439dbb6f778SMiquel Raynal lvds_vopl_in: endpoint@1 { 440dbb6f778SMiquel Raynal reg = <1>; 441dbb6f778SMiquel Raynal remote-endpoint = <&vopl_out_lvds>; 442dbb6f778SMiquel Raynal }; 443dbb6f778SMiquel Raynal }; 444dbb6f778SMiquel Raynal }; 4457053e06bSLiang Chen }; 446186444c1SHeiko Stuebner }; 4477053e06bSLiang Chen 4487053e06bSLiang Chen uart1: serial@ff158000 { 4497053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 4507053e06bSLiang Chen reg = <0x0 0xff158000 0x0 0x100>; 4517053e06bSLiang Chen interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 4527053e06bSLiang Chen clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 4537053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 4547053e06bSLiang Chen dmas = <&dmac 2>, <&dmac 3>; 4557053e06bSLiang Chen dma-names = "tx", "rx"; 4567053e06bSLiang Chen reg-shift = <2>; 4577053e06bSLiang Chen reg-io-width = <4>; 4587053e06bSLiang Chen pinctrl-names = "default"; 4597053e06bSLiang Chen pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 4607053e06bSLiang Chen status = "disabled"; 4617053e06bSLiang Chen }; 4627053e06bSLiang Chen 4637053e06bSLiang Chen uart2: serial@ff160000 { 4647053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 4657053e06bSLiang Chen reg = <0x0 0xff160000 0x0 0x100>; 4667053e06bSLiang Chen interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 4677053e06bSLiang Chen clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 4687053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 4697053e06bSLiang Chen dmas = <&dmac 4>, <&dmac 5>; 4707053e06bSLiang Chen dma-names = "tx", "rx"; 4717053e06bSLiang Chen reg-shift = <2>; 4727053e06bSLiang Chen reg-io-width = <4>; 4737053e06bSLiang Chen pinctrl-names = "default"; 4747053e06bSLiang Chen pinctrl-0 = <&uart2m0_xfer>; 4757053e06bSLiang Chen status = "disabled"; 4767053e06bSLiang Chen }; 4777053e06bSLiang Chen 4787053e06bSLiang Chen uart3: serial@ff168000 { 4797053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 4807053e06bSLiang Chen reg = <0x0 0xff168000 0x0 0x100>; 4817053e06bSLiang Chen interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 4827053e06bSLiang Chen clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 4837053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 4847053e06bSLiang Chen dmas = <&dmac 6>, <&dmac 7>; 4857053e06bSLiang Chen dma-names = "tx", "rx"; 4867053e06bSLiang Chen reg-shift = <2>; 4877053e06bSLiang Chen reg-io-width = <4>; 4887053e06bSLiang Chen pinctrl-names = "default"; 4897053e06bSLiang Chen pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 4907053e06bSLiang Chen status = "disabled"; 4917053e06bSLiang Chen }; 4927053e06bSLiang Chen 4937053e06bSLiang Chen uart4: serial@ff170000 { 4947053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 4957053e06bSLiang Chen reg = <0x0 0xff170000 0x0 0x100>; 4967053e06bSLiang Chen interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4977053e06bSLiang Chen clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 4987053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 4997053e06bSLiang Chen dmas = <&dmac 8>, <&dmac 9>; 5007053e06bSLiang Chen dma-names = "tx", "rx"; 5017053e06bSLiang Chen reg-shift = <2>; 5027053e06bSLiang Chen reg-io-width = <4>; 5037053e06bSLiang Chen pinctrl-names = "default"; 5047053e06bSLiang Chen pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 5057053e06bSLiang Chen status = "disabled"; 5067053e06bSLiang Chen }; 5077053e06bSLiang Chen 5087053e06bSLiang Chen uart5: serial@ff178000 { 5097053e06bSLiang Chen compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 5107053e06bSLiang Chen reg = <0x0 0xff178000 0x0 0x100>; 5117053e06bSLiang Chen interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 5127053e06bSLiang Chen clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 5137053e06bSLiang Chen clock-names = "baudclk", "apb_pclk"; 5147053e06bSLiang Chen dmas = <&dmac 10>, <&dmac 11>; 5157053e06bSLiang Chen dma-names = "tx", "rx"; 5167053e06bSLiang Chen reg-shift = <2>; 5177053e06bSLiang Chen reg-io-width = <4>; 5187053e06bSLiang Chen pinctrl-names = "default"; 5197053e06bSLiang Chen pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 5207053e06bSLiang Chen status = "disabled"; 5217053e06bSLiang Chen }; 5227053e06bSLiang Chen 5237053e06bSLiang Chen i2c0: i2c@ff180000 { 5247053e06bSLiang Chen compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 5257053e06bSLiang Chen reg = <0x0 0xff180000 0x0 0x1000>; 5267053e06bSLiang Chen clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 5277053e06bSLiang Chen clock-names = "i2c", "pclk"; 5287053e06bSLiang Chen interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 5297053e06bSLiang Chen pinctrl-names = "default"; 5307053e06bSLiang Chen pinctrl-0 = <&i2c0_xfer>; 5317053e06bSLiang Chen #address-cells = <1>; 5327053e06bSLiang Chen #size-cells = <0>; 5337053e06bSLiang Chen status = "disabled"; 5347053e06bSLiang Chen }; 5357053e06bSLiang Chen 5367053e06bSLiang Chen i2c1: i2c@ff190000 { 5377053e06bSLiang Chen compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 5387053e06bSLiang Chen reg = <0x0 0xff190000 0x0 0x1000>; 5397053e06bSLiang Chen clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 5407053e06bSLiang Chen clock-names = "i2c", "pclk"; 5417053e06bSLiang Chen interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 5427053e06bSLiang Chen pinctrl-names = "default"; 5437053e06bSLiang Chen pinctrl-0 = <&i2c1_xfer>; 5447053e06bSLiang Chen #address-cells = <1>; 5457053e06bSLiang Chen #size-cells = <0>; 5467053e06bSLiang Chen status = "disabled"; 5477053e06bSLiang Chen }; 5487053e06bSLiang Chen 5497053e06bSLiang Chen i2c2: i2c@ff1a0000 { 5507053e06bSLiang Chen compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 5517053e06bSLiang Chen reg = <0x0 0xff1a0000 0x0 0x1000>; 5527053e06bSLiang Chen clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 5537053e06bSLiang Chen clock-names = "i2c", "pclk"; 5547053e06bSLiang Chen interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5557053e06bSLiang Chen pinctrl-names = "default"; 5567053e06bSLiang Chen pinctrl-0 = <&i2c2_xfer>; 5577053e06bSLiang Chen #address-cells = <1>; 5587053e06bSLiang Chen #size-cells = <0>; 5597053e06bSLiang Chen status = "disabled"; 5607053e06bSLiang Chen }; 5617053e06bSLiang Chen 5627053e06bSLiang Chen i2c3: i2c@ff1b0000 { 5637053e06bSLiang Chen compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 5647053e06bSLiang Chen reg = <0x0 0xff1b0000 0x0 0x1000>; 5657053e06bSLiang Chen clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 5667053e06bSLiang Chen clock-names = "i2c", "pclk"; 5677053e06bSLiang Chen interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5687053e06bSLiang Chen pinctrl-names = "default"; 5697053e06bSLiang Chen pinctrl-0 = <&i2c3_xfer>; 5707053e06bSLiang Chen #address-cells = <1>; 5717053e06bSLiang Chen #size-cells = <0>; 5727053e06bSLiang Chen status = "disabled"; 5737053e06bSLiang Chen }; 5747053e06bSLiang Chen 5757053e06bSLiang Chen spi0: spi@ff1d0000 { 5767053e06bSLiang Chen compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 5777053e06bSLiang Chen reg = <0x0 0xff1d0000 0x0 0x1000>; 5787053e06bSLiang Chen interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 5797053e06bSLiang Chen clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 5807053e06bSLiang Chen clock-names = "spiclk", "apb_pclk"; 5817053e06bSLiang Chen dmas = <&dmac 12>, <&dmac 13>; 5827053e06bSLiang Chen dma-names = "tx", "rx"; 5837053e06bSLiang Chen pinctrl-names = "default"; 5847053e06bSLiang Chen pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 5857053e06bSLiang Chen #address-cells = <1>; 5867053e06bSLiang Chen #size-cells = <0>; 5877053e06bSLiang Chen status = "disabled"; 5887053e06bSLiang Chen }; 5897053e06bSLiang Chen 5907053e06bSLiang Chen spi1: spi@ff1d8000 { 5917053e06bSLiang Chen compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 5927053e06bSLiang Chen reg = <0x0 0xff1d8000 0x0 0x1000>; 5937053e06bSLiang Chen interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 5947053e06bSLiang Chen clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 5957053e06bSLiang Chen clock-names = "spiclk", "apb_pclk"; 5967053e06bSLiang Chen dmas = <&dmac 14>, <&dmac 15>; 5977053e06bSLiang Chen dma-names = "tx", "rx"; 5987053e06bSLiang Chen pinctrl-names = "default"; 5997053e06bSLiang Chen pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 6007053e06bSLiang Chen #address-cells = <1>; 6017053e06bSLiang Chen #size-cells = <0>; 6027053e06bSLiang Chen status = "disabled"; 6037053e06bSLiang Chen }; 6047053e06bSLiang Chen 6057053e06bSLiang Chen wdt: watchdog@ff1e0000 { 6067053e06bSLiang Chen compatible = "snps,dw-wdt"; 6077053e06bSLiang Chen reg = <0x0 0xff1e0000 0x0 0x100>; 6087053e06bSLiang Chen clocks = <&cru PCLK_WDT_NS>; 6097053e06bSLiang Chen interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 6107053e06bSLiang Chen status = "disabled"; 6117053e06bSLiang Chen }; 6127053e06bSLiang Chen 6137053e06bSLiang Chen pwm0: pwm@ff200000 { 6147053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6157053e06bSLiang Chen reg = <0x0 0xff200000 0x0 0x10>; 6167053e06bSLiang Chen clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 6177053e06bSLiang Chen clock-names = "pwm", "pclk"; 6187053e06bSLiang Chen pinctrl-names = "default"; 6197053e06bSLiang Chen pinctrl-0 = <&pwm0_pin>; 6207053e06bSLiang Chen #pwm-cells = <3>; 6217053e06bSLiang Chen status = "disabled"; 6227053e06bSLiang Chen }; 6237053e06bSLiang Chen 6247053e06bSLiang Chen pwm1: pwm@ff200010 { 6257053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6267053e06bSLiang Chen reg = <0x0 0xff200010 0x0 0x10>; 6277053e06bSLiang Chen clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 6287053e06bSLiang Chen clock-names = "pwm", "pclk"; 6297053e06bSLiang Chen pinctrl-names = "default"; 6307053e06bSLiang Chen pinctrl-0 = <&pwm1_pin>; 6317053e06bSLiang Chen #pwm-cells = <3>; 6327053e06bSLiang Chen status = "disabled"; 6337053e06bSLiang Chen }; 6347053e06bSLiang Chen 6357053e06bSLiang Chen pwm2: pwm@ff200020 { 6367053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6377053e06bSLiang Chen reg = <0x0 0xff200020 0x0 0x10>; 6387053e06bSLiang Chen clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 6397053e06bSLiang Chen clock-names = "pwm", "pclk"; 6407053e06bSLiang Chen pinctrl-names = "default"; 6417053e06bSLiang Chen pinctrl-0 = <&pwm2_pin>; 6427053e06bSLiang Chen #pwm-cells = <3>; 6437053e06bSLiang Chen status = "disabled"; 6447053e06bSLiang Chen }; 6457053e06bSLiang Chen 6467053e06bSLiang Chen pwm3: pwm@ff200030 { 6477053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6487053e06bSLiang Chen reg = <0x0 0xff200030 0x0 0x10>; 6497053e06bSLiang Chen clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 6507053e06bSLiang Chen clock-names = "pwm", "pclk"; 6517053e06bSLiang Chen pinctrl-names = "default"; 6527053e06bSLiang Chen pinctrl-0 = <&pwm3_pin>; 6537053e06bSLiang Chen #pwm-cells = <3>; 6547053e06bSLiang Chen status = "disabled"; 6557053e06bSLiang Chen }; 6567053e06bSLiang Chen 6577053e06bSLiang Chen pwm4: pwm@ff208000 { 6587053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6597053e06bSLiang Chen reg = <0x0 0xff208000 0x0 0x10>; 6607053e06bSLiang Chen clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 6617053e06bSLiang Chen clock-names = "pwm", "pclk"; 6627053e06bSLiang Chen pinctrl-names = "default"; 6637053e06bSLiang Chen pinctrl-0 = <&pwm4_pin>; 6647053e06bSLiang Chen #pwm-cells = <3>; 6657053e06bSLiang Chen status = "disabled"; 6667053e06bSLiang Chen }; 6677053e06bSLiang Chen 6687053e06bSLiang Chen pwm5: pwm@ff208010 { 6697053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6707053e06bSLiang Chen reg = <0x0 0xff208010 0x0 0x10>; 6717053e06bSLiang Chen clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 6727053e06bSLiang Chen clock-names = "pwm", "pclk"; 6737053e06bSLiang Chen pinctrl-names = "default"; 6747053e06bSLiang Chen pinctrl-0 = <&pwm5_pin>; 6757053e06bSLiang Chen #pwm-cells = <3>; 6767053e06bSLiang Chen status = "disabled"; 6777053e06bSLiang Chen }; 6787053e06bSLiang Chen 6797053e06bSLiang Chen pwm6: pwm@ff208020 { 6807053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6817053e06bSLiang Chen reg = <0x0 0xff208020 0x0 0x10>; 6827053e06bSLiang Chen clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 6837053e06bSLiang Chen clock-names = "pwm", "pclk"; 6847053e06bSLiang Chen pinctrl-names = "default"; 6857053e06bSLiang Chen pinctrl-0 = <&pwm6_pin>; 6867053e06bSLiang Chen #pwm-cells = <3>; 6877053e06bSLiang Chen status = "disabled"; 6887053e06bSLiang Chen }; 6897053e06bSLiang Chen 6907053e06bSLiang Chen pwm7: pwm@ff208030 { 6917053e06bSLiang Chen compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 6927053e06bSLiang Chen reg = <0x0 0xff208030 0x0 0x10>; 6937053e06bSLiang Chen clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 6947053e06bSLiang Chen clock-names = "pwm", "pclk"; 6957053e06bSLiang Chen pinctrl-names = "default"; 6967053e06bSLiang Chen pinctrl-0 = <&pwm7_pin>; 6977053e06bSLiang Chen #pwm-cells = <3>; 6987053e06bSLiang Chen status = "disabled"; 6997053e06bSLiang Chen }; 7007053e06bSLiang Chen 7017053e06bSLiang Chen rktimer: timer@ff210000 { 7027053e06bSLiang Chen compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 7037053e06bSLiang Chen reg = <0x0 0xff210000 0x0 0x1000>; 7047053e06bSLiang Chen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 7057053e06bSLiang Chen clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 7067053e06bSLiang Chen clock-names = "pclk", "timer"; 7077053e06bSLiang Chen }; 7087053e06bSLiang Chen 7097053e06bSLiang Chen dmac: dmac@ff240000 { 7107053e06bSLiang Chen compatible = "arm,pl330", "arm,primecell"; 7117053e06bSLiang Chen reg = <0x0 0xff240000 0x0 0x4000>; 7127053e06bSLiang Chen interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 7137053e06bSLiang Chen <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 714505af918SSugar Zhang arm,pl330-periph-burst; 7157053e06bSLiang Chen clocks = <&cru ACLK_DMAC>; 7167053e06bSLiang Chen clock-names = "apb_pclk"; 7177053e06bSLiang Chen #dma-cells = <1>; 7187053e06bSLiang Chen }; 7197053e06bSLiang Chen 720023115cdSHeiko Stuebner tsadc: tsadc@ff280000 { 721023115cdSHeiko Stuebner compatible = "rockchip,px30-tsadc"; 722023115cdSHeiko Stuebner reg = <0x0 0xff280000 0x0 0x100>; 723023115cdSHeiko Stuebner interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 724023115cdSHeiko Stuebner assigned-clocks = <&cru SCLK_TSADC>; 725023115cdSHeiko Stuebner assigned-clock-rates = <50000>; 726023115cdSHeiko Stuebner clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 727023115cdSHeiko Stuebner clock-names = "tsadc", "apb_pclk"; 728023115cdSHeiko Stuebner resets = <&cru SRST_TSADC>; 729023115cdSHeiko Stuebner reset-names = "tsadc-apb"; 730023115cdSHeiko Stuebner rockchip,grf = <&grf>; 731023115cdSHeiko Stuebner rockchip,hw-tshut-temp = <120000>; 732023115cdSHeiko Stuebner pinctrl-names = "init", "default", "sleep"; 7332bc65fefSJohan Jonker pinctrl-0 = <&tsadc_otp_pin>; 734023115cdSHeiko Stuebner pinctrl-1 = <&tsadc_otp_out>; 7352bc65fefSJohan Jonker pinctrl-2 = <&tsadc_otp_pin>; 736023115cdSHeiko Stuebner #thermal-sensor-cells = <1>; 737023115cdSHeiko Stuebner status = "disabled"; 738023115cdSHeiko Stuebner }; 739023115cdSHeiko Stuebner 7407053e06bSLiang Chen saradc: saradc@ff288000 { 7417053e06bSLiang Chen compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 7427053e06bSLiang Chen reg = <0x0 0xff288000 0x0 0x100>; 7437053e06bSLiang Chen interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 7447053e06bSLiang Chen #io-channel-cells = <1>; 7457053e06bSLiang Chen clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 7467053e06bSLiang Chen clock-names = "saradc", "apb_pclk"; 7477053e06bSLiang Chen resets = <&cru SRST_SARADC_P>; 7487053e06bSLiang Chen reset-names = "saradc-apb"; 7497053e06bSLiang Chen status = "disabled"; 7507053e06bSLiang Chen }; 7517053e06bSLiang Chen 752fbb78418SHeiko Stuebner otp: nvmem@ff290000 { 753fbb78418SHeiko Stuebner compatible = "rockchip,px30-otp"; 754fbb78418SHeiko Stuebner reg = <0x0 0xff290000 0x0 0x4000>; 755fbb78418SHeiko Stuebner clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 756fbb78418SHeiko Stuebner <&cru PCLK_OTP_PHY>; 757fbb78418SHeiko Stuebner clock-names = "otp", "apb_pclk", "phy"; 758fbb78418SHeiko Stuebner resets = <&cru SRST_OTP_PHY>; 759fbb78418SHeiko Stuebner reset-names = "phy"; 760fbb78418SHeiko Stuebner #address-cells = <1>; 761fbb78418SHeiko Stuebner #size-cells = <1>; 762fbb78418SHeiko Stuebner 763fbb78418SHeiko Stuebner /* Data cells */ 764fbb78418SHeiko Stuebner cpu_id: id@7 { 765fbb78418SHeiko Stuebner reg = <0x07 0x10>; 766fbb78418SHeiko Stuebner }; 767fbb78418SHeiko Stuebner cpu_leakage: cpu-leakage@17 { 768fbb78418SHeiko Stuebner reg = <0x17 0x1>; 769fbb78418SHeiko Stuebner }; 770fbb78418SHeiko Stuebner performance: performance@1e { 771fbb78418SHeiko Stuebner reg = <0x1e 0x1>; 772fbb78418SHeiko Stuebner bits = <4 3>; 773fbb78418SHeiko Stuebner }; 774fbb78418SHeiko Stuebner }; 775fbb78418SHeiko Stuebner 7767053e06bSLiang Chen cru: clock-controller@ff2b0000 { 7777053e06bSLiang Chen compatible = "rockchip,px30-cru"; 7787053e06bSLiang Chen reg = <0x0 0xff2b0000 0x0 0x1000>; 77945cb61b4SHeiko Stuebner clocks = <&xin24m>, <&pmucru PLL_GPLL>; 78045cb61b4SHeiko Stuebner clock-names = "xin24m", "gpll"; 7817053e06bSLiang Chen rockchip,grf = <&grf>; 7827053e06bSLiang Chen #clock-cells = <1>; 7837053e06bSLiang Chen #reset-cells = <1>; 7847053e06bSLiang Chen 78545cb61b4SHeiko Stuebner assigned-clocks = <&cru PLL_NPLL>, 78645cb61b4SHeiko Stuebner <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 78745cb61b4SHeiko Stuebner <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 78845cb61b4SHeiko Stuebner <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 78945cb61b4SHeiko Stuebner 79045cb61b4SHeiko Stuebner assigned-clock-rates = <1188000000>, 79145cb61b4SHeiko Stuebner <200000000>, <200000000>, 79245cb61b4SHeiko Stuebner <150000000>, <150000000>, 79345cb61b4SHeiko Stuebner <100000000>, <200000000>; 7947053e06bSLiang Chen }; 7957053e06bSLiang Chen 7967053e06bSLiang Chen pmucru: clock-controller@ff2bc000 { 7977053e06bSLiang Chen compatible = "rockchip,px30-pmucru"; 7987053e06bSLiang Chen reg = <0x0 0xff2bc000 0x0 0x1000>; 79945cb61b4SHeiko Stuebner clocks = <&xin24m>; 80045cb61b4SHeiko Stuebner clock-names = "xin24m"; 8017053e06bSLiang Chen rockchip,grf = <&grf>; 8027053e06bSLiang Chen #clock-cells = <1>; 8037053e06bSLiang Chen #reset-cells = <1>; 8047053e06bSLiang Chen 8057053e06bSLiang Chen assigned-clocks = 8067053e06bSLiang Chen <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 80745cb61b4SHeiko Stuebner <&pmucru SCLK_WIFI_PMU>; 8087053e06bSLiang Chen assigned-clock-rates = 8097053e06bSLiang Chen <1200000000>, <100000000>, 81045cb61b4SHeiko Stuebner <26000000>; 8117053e06bSLiang Chen }; 8127053e06bSLiang Chen 813f952b45bSHeiko Stuebner usb2phy_grf: syscon@ff2c0000 { 814f952b45bSHeiko Stuebner compatible = "rockchip,px30-usb2phy-grf", "syscon", 815f952b45bSHeiko Stuebner "simple-mfd"; 816f952b45bSHeiko Stuebner reg = <0x0 0xff2c0000 0x0 0x10000>; 817f952b45bSHeiko Stuebner #address-cells = <1>; 818f952b45bSHeiko Stuebner #size-cells = <1>; 819f952b45bSHeiko Stuebner 820f952b45bSHeiko Stuebner u2phy: usb2-phy@100 { 821f952b45bSHeiko Stuebner compatible = "rockchip,px30-usb2phy"; 822f952b45bSHeiko Stuebner reg = <0x100 0x20>; 823f952b45bSHeiko Stuebner clocks = <&pmucru SCLK_USBPHY_REF>; 824f952b45bSHeiko Stuebner clock-names = "phyclk"; 825f952b45bSHeiko Stuebner #clock-cells = <0>; 826f952b45bSHeiko Stuebner assigned-clocks = <&cru USB480M>; 827f952b45bSHeiko Stuebner assigned-clock-parents = <&u2phy>; 828f952b45bSHeiko Stuebner clock-output-names = "usb480m_phy"; 829f952b45bSHeiko Stuebner status = "disabled"; 830f952b45bSHeiko Stuebner 831f952b45bSHeiko Stuebner u2phy_host: host-port { 832f952b45bSHeiko Stuebner #phy-cells = <0>; 833f952b45bSHeiko Stuebner interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 834f952b45bSHeiko Stuebner interrupt-names = "linestate"; 835f952b45bSHeiko Stuebner status = "disabled"; 836f952b45bSHeiko Stuebner }; 837f952b45bSHeiko Stuebner 838f952b45bSHeiko Stuebner u2phy_otg: otg-port { 839f952b45bSHeiko Stuebner #phy-cells = <0>; 840f952b45bSHeiko Stuebner interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 841f952b45bSHeiko Stuebner <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 842f952b45bSHeiko Stuebner <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 843f952b45bSHeiko Stuebner interrupt-names = "otg-bvalid", "otg-id", 844f952b45bSHeiko Stuebner "linestate"; 845f952b45bSHeiko Stuebner status = "disabled"; 846f952b45bSHeiko Stuebner }; 847f952b45bSHeiko Stuebner }; 848f952b45bSHeiko Stuebner }; 849f952b45bSHeiko Stuebner 8507e90ccecSMiquel Raynal dsi_dphy: phy@ff2e0000 { 8517e90ccecSMiquel Raynal compatible = "rockchip,px30-dsi-dphy"; 8527e90ccecSMiquel Raynal reg = <0x0 0xff2e0000 0x0 0x10000>; 8537e90ccecSMiquel Raynal clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 8547e90ccecSMiquel Raynal clock-names = "ref", "pclk"; 8557e90ccecSMiquel Raynal resets = <&cru SRST_MIPIDSIPHY_P>; 8567e90ccecSMiquel Raynal reset-names = "apb"; 8577e90ccecSMiquel Raynal #phy-cells = <0>; 8587e90ccecSMiquel Raynal power-domains = <&power PX30_PD_VO>; 8597e90ccecSMiquel Raynal status = "disabled"; 8607e90ccecSMiquel Raynal }; 8617e90ccecSMiquel Raynal 862bb598133SHeiko Stuebner usb20_otg: usb@ff300000 { 863bb598133SHeiko Stuebner compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 864bb598133SHeiko Stuebner "snps,dwc2"; 865bb598133SHeiko Stuebner reg = <0x0 0xff300000 0x0 0x40000>; 866bb598133SHeiko Stuebner interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 867bb598133SHeiko Stuebner clocks = <&cru HCLK_OTG>; 868bb598133SHeiko Stuebner clock-names = "otg"; 869bb598133SHeiko Stuebner dr_mode = "otg"; 870bb598133SHeiko Stuebner g-np-tx-fifo-size = <16>; 871bb598133SHeiko Stuebner g-rx-fifo-size = <280>; 872bb598133SHeiko Stuebner g-tx-fifo-size = <256 128 128 64 32 16>; 873f952b45bSHeiko Stuebner phys = <&u2phy_otg>; 874f952b45bSHeiko Stuebner phy-names = "usb2-phy"; 875bb598133SHeiko Stuebner power-domains = <&power PX30_PD_USB>; 876bb598133SHeiko Stuebner status = "disabled"; 877bb598133SHeiko Stuebner }; 878bb598133SHeiko Stuebner 8797053e06bSLiang Chen usb_host0_ehci: usb@ff340000 { 8807053e06bSLiang Chen compatible = "generic-ehci"; 8817053e06bSLiang Chen reg = <0x0 0xff340000 0x0 0x10000>; 8827053e06bSLiang Chen interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 8837053e06bSLiang Chen clocks = <&cru HCLK_HOST>; 884f952b45bSHeiko Stuebner phys = <&u2phy_host>; 885f952b45bSHeiko Stuebner phy-names = "usb"; 8867053e06bSLiang Chen power-domains = <&power PX30_PD_USB>; 8877053e06bSLiang Chen status = "disabled"; 8887053e06bSLiang Chen }; 8897053e06bSLiang Chen 8907053e06bSLiang Chen usb_host0_ohci: usb@ff350000 { 8917053e06bSLiang Chen compatible = "generic-ohci"; 8927053e06bSLiang Chen reg = <0x0 0xff350000 0x0 0x10000>; 8937053e06bSLiang Chen interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 8947053e06bSLiang Chen clocks = <&cru HCLK_HOST>; 895f952b45bSHeiko Stuebner phys = <&u2phy_host>; 896f952b45bSHeiko Stuebner phy-names = "usb"; 8977053e06bSLiang Chen power-domains = <&power PX30_PD_USB>; 8987053e06bSLiang Chen status = "disabled"; 8997053e06bSLiang Chen }; 9007053e06bSLiang Chen 9017053e06bSLiang Chen gmac: ethernet@ff360000 { 9027053e06bSLiang Chen compatible = "rockchip,px30-gmac"; 9037053e06bSLiang Chen reg = <0x0 0xff360000 0x0 0x10000>; 9047053e06bSLiang Chen interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 9057053e06bSLiang Chen interrupt-names = "macirq"; 9067053e06bSLiang Chen clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 9077053e06bSLiang Chen <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 9087053e06bSLiang Chen <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 9097053e06bSLiang Chen <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 9107053e06bSLiang Chen clock-names = "stmmaceth", "mac_clk_rx", 9117053e06bSLiang Chen "mac_clk_tx", "clk_mac_ref", 9127053e06bSLiang Chen "clk_mac_refout", "aclk_mac", 9137053e06bSLiang Chen "pclk_mac", "clk_mac_speed"; 9147053e06bSLiang Chen rockchip,grf = <&grf>; 9157053e06bSLiang Chen phy-mode = "rmii"; 9167053e06bSLiang Chen pinctrl-names = "default"; 9177053e06bSLiang Chen pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 9187053e06bSLiang Chen power-domains = <&power PX30_PD_GMAC>; 9197053e06bSLiang Chen resets = <&cru SRST_GMAC_A>; 9207053e06bSLiang Chen reset-names = "stmmaceth"; 9217053e06bSLiang Chen status = "disabled"; 9227053e06bSLiang Chen }; 9237053e06bSLiang Chen 9243ef7c255SJohan Jonker sdmmc: mmc@ff370000 { 9257053e06bSLiang Chen compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 9267053e06bSLiang Chen reg = <0x0 0xff370000 0x0 0x4000>; 9277053e06bSLiang Chen interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 9287053e06bSLiang Chen clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 9297053e06bSLiang Chen <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 9307f214735SJohan Jonker clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 931fb0ab17fSJohan Jonker bus-width = <4>; 9327053e06bSLiang Chen fifo-depth = <0x100>; 9337053e06bSLiang Chen max-frequency = <150000000>; 9347053e06bSLiang Chen pinctrl-names = "default"; 9357053e06bSLiang Chen pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 9367053e06bSLiang Chen power-domains = <&power PX30_PD_SDCARD>; 9377053e06bSLiang Chen status = "disabled"; 9387053e06bSLiang Chen }; 9397053e06bSLiang Chen 9403ef7c255SJohan Jonker sdio: mmc@ff380000 { 9417053e06bSLiang Chen compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 9427053e06bSLiang Chen reg = <0x0 0xff380000 0x0 0x4000>; 9437053e06bSLiang Chen interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 9447053e06bSLiang Chen clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 9457053e06bSLiang Chen <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 9467f214735SJohan Jonker clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 947fb0ab17fSJohan Jonker bus-width = <4>; 9487053e06bSLiang Chen fifo-depth = <0x100>; 9497053e06bSLiang Chen max-frequency = <150000000>; 9507053e06bSLiang Chen pinctrl-names = "default"; 9517053e06bSLiang Chen pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 9527053e06bSLiang Chen power-domains = <&power PX30_PD_MMC_NAND>; 9537053e06bSLiang Chen status = "disabled"; 9547053e06bSLiang Chen }; 9557053e06bSLiang Chen 9563ef7c255SJohan Jonker emmc: mmc@ff390000 { 9577053e06bSLiang Chen compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 9587053e06bSLiang Chen reg = <0x0 0xff390000 0x0 0x4000>; 9597053e06bSLiang Chen interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 9607053e06bSLiang Chen clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 9617053e06bSLiang Chen <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 9627f214735SJohan Jonker clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 963fb0ab17fSJohan Jonker bus-width = <8>; 9647053e06bSLiang Chen fifo-depth = <0x100>; 9657053e06bSLiang Chen max-frequency = <150000000>; 966cdfebb27SHeiko Stuebner pinctrl-names = "default"; 967cdfebb27SHeiko Stuebner pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 9687053e06bSLiang Chen power-domains = <&power PX30_PD_MMC_NAND>; 9697053e06bSLiang Chen status = "disabled"; 9707053e06bSLiang Chen }; 9717053e06bSLiang Chen 972d00e6e22SYifeng Zhao nfc: nand-controller@ff3b0000 { 973d00e6e22SYifeng Zhao compatible = "rockchip,px30-nfc"; 974d00e6e22SYifeng Zhao reg = <0x0 0xff3b0000 0x0 0x4000>; 975d00e6e22SYifeng Zhao interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 976d00e6e22SYifeng Zhao clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 977d00e6e22SYifeng Zhao clock-names = "ahb", "nfc"; 978d00e6e22SYifeng Zhao assigned-clocks = <&cru SCLK_NANDC>; 979d00e6e22SYifeng Zhao assigned-clock-rates = <150000000>; 980d00e6e22SYifeng Zhao pinctrl-names = "default"; 981d00e6e22SYifeng Zhao pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 982d00e6e22SYifeng Zhao &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; 983d00e6e22SYifeng Zhao power-domains = <&power PX30_PD_MMC_NAND>; 984d00e6e22SYifeng Zhao status = "disabled"; 985d00e6e22SYifeng Zhao }; 986d00e6e22SYifeng Zhao 987a07f34a0SHeiko Stuebner gpu: gpu@ff400000 { 988a07f34a0SHeiko Stuebner compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 989a07f34a0SHeiko Stuebner reg = <0x0 0xff400000 0x0 0x4000>; 990a07f34a0SHeiko Stuebner interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 991a07f34a0SHeiko Stuebner <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 992a07f34a0SHeiko Stuebner <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 993a07f34a0SHeiko Stuebner interrupt-names = "job", "mmu", "gpu"; 994a07f34a0SHeiko Stuebner clocks = <&cru SCLK_GPU>; 995a07f34a0SHeiko Stuebner #cooling-cells = <2>; 996a07f34a0SHeiko Stuebner power-domains = <&power PX30_PD_GPU>; 997a07f34a0SHeiko Stuebner status = "disabled"; 998a07f34a0SHeiko Stuebner }; 999a07f34a0SHeiko Stuebner 1000cc5912abSHeiko Stuebner dsi: dsi@ff450000 { 1001cc5912abSHeiko Stuebner compatible = "rockchip,px30-mipi-dsi"; 1002cc5912abSHeiko Stuebner reg = <0x0 0xff450000 0x0 0x10000>; 1003cc5912abSHeiko Stuebner interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1004cc5912abSHeiko Stuebner clocks = <&cru PCLK_MIPI_DSI>; 1005cc5912abSHeiko Stuebner clock-names = "pclk"; 1006cc5912abSHeiko Stuebner phys = <&dsi_dphy>; 1007cc5912abSHeiko Stuebner phy-names = "dphy"; 1008cc5912abSHeiko Stuebner power-domains = <&power PX30_PD_VO>; 1009cc5912abSHeiko Stuebner resets = <&cru SRST_MIPIDSI_HOST_P>; 1010cc5912abSHeiko Stuebner reset-names = "apb"; 1011cc5912abSHeiko Stuebner rockchip,grf = <&grf>; 1012cc5912abSHeiko Stuebner #address-cells = <1>; 1013cc5912abSHeiko Stuebner #size-cells = <0>; 1014cc5912abSHeiko Stuebner status = "disabled"; 1015cc5912abSHeiko Stuebner 1016cc5912abSHeiko Stuebner ports { 1017cc5912abSHeiko Stuebner #address-cells = <1>; 1018cc5912abSHeiko Stuebner #size-cells = <0>; 1019cc5912abSHeiko Stuebner 1020cc5912abSHeiko Stuebner port@0 { 1021cc5912abSHeiko Stuebner reg = <0>; 1022cc5912abSHeiko Stuebner #address-cells = <1>; 1023cc5912abSHeiko Stuebner #size-cells = <0>; 1024cc5912abSHeiko Stuebner 1025cc5912abSHeiko Stuebner dsi_in_vopb: endpoint@0 { 1026cc5912abSHeiko Stuebner reg = <0>; 1027cc5912abSHeiko Stuebner remote-endpoint = <&vopb_out_dsi>; 1028cc5912abSHeiko Stuebner }; 1029cc5912abSHeiko Stuebner 1030cc5912abSHeiko Stuebner dsi_in_vopl: endpoint@1 { 1031cc5912abSHeiko Stuebner reg = <1>; 1032cc5912abSHeiko Stuebner remote-endpoint = <&vopl_out_dsi>; 1033cc5912abSHeiko Stuebner }; 1034cc5912abSHeiko Stuebner }; 1035cc5912abSHeiko Stuebner }; 1036cc5912abSHeiko Stuebner }; 1037cc5912abSHeiko Stuebner 10387053e06bSLiang Chen vopb: vop@ff460000 { 10397053e06bSLiang Chen compatible = "rockchip,px30-vop-big"; 10407053e06bSLiang Chen reg = <0x0 0xff460000 0x0 0xefc>; 10417053e06bSLiang Chen interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 10427053e06bSLiang Chen clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 10437053e06bSLiang Chen <&cru HCLK_VOPB>; 10447053e06bSLiang Chen clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1045967c1464SSandy Huang resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1046967c1464SSandy Huang reset-names = "axi", "ahb", "dclk"; 10477053e06bSLiang Chen iommus = <&vopb_mmu>; 10487053e06bSLiang Chen power-domains = <&power PX30_PD_VO>; 10497053e06bSLiang Chen status = "disabled"; 1050967c1464SSandy Huang 1051967c1464SSandy Huang vopb_out: port { 1052967c1464SSandy Huang #address-cells = <1>; 1053967c1464SSandy Huang #size-cells = <0>; 1054cc5912abSHeiko Stuebner 1055cc5912abSHeiko Stuebner vopb_out_dsi: endpoint@0 { 1056cc5912abSHeiko Stuebner reg = <0>; 1057cc5912abSHeiko Stuebner remote-endpoint = <&dsi_in_vopb>; 1058cc5912abSHeiko Stuebner }; 1059dbb6f778SMiquel Raynal 1060dbb6f778SMiquel Raynal vopb_out_lvds: endpoint@1 { 1061dbb6f778SMiquel Raynal reg = <1>; 1062dbb6f778SMiquel Raynal remote-endpoint = <&lvds_vopb_in>; 1063dbb6f778SMiquel Raynal }; 1064967c1464SSandy Huang }; 10657053e06bSLiang Chen }; 10667053e06bSLiang Chen 10677053e06bSLiang Chen vopb_mmu: iommu@ff460f00 { 10687053e06bSLiang Chen compatible = "rockchip,iommu"; 10697053e06bSLiang Chen reg = <0x0 0xff460f00 0x0 0x100>; 10707053e06bSLiang Chen interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 10717053e06bSLiang Chen interrupt-names = "vopb_mmu"; 10727053e06bSLiang Chen clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 10738e57eed2SHeiko Stuebner clock-names = "aclk", "iface"; 10747053e06bSLiang Chen power-domains = <&power PX30_PD_VO>; 10757053e06bSLiang Chen #iommu-cells = <0>; 10767053e06bSLiang Chen status = "disabled"; 10777053e06bSLiang Chen }; 10787053e06bSLiang Chen 10797053e06bSLiang Chen vopl: vop@ff470000 { 10807053e06bSLiang Chen compatible = "rockchip,px30-vop-lit"; 10817053e06bSLiang Chen reg = <0x0 0xff470000 0x0 0xefc>; 10827053e06bSLiang Chen interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 10837053e06bSLiang Chen clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 10847053e06bSLiang Chen <&cru HCLK_VOPL>; 10857053e06bSLiang Chen clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1086967c1464SSandy Huang resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1087967c1464SSandy Huang reset-names = "axi", "ahb", "dclk"; 10887053e06bSLiang Chen iommus = <&vopl_mmu>; 10897053e06bSLiang Chen power-domains = <&power PX30_PD_VO>; 10907053e06bSLiang Chen status = "disabled"; 1091967c1464SSandy Huang 1092967c1464SSandy Huang vopl_out: port { 1093967c1464SSandy Huang #address-cells = <1>; 1094967c1464SSandy Huang #size-cells = <0>; 1095cc5912abSHeiko Stuebner 1096cc5912abSHeiko Stuebner vopl_out_dsi: endpoint@0 { 1097cc5912abSHeiko Stuebner reg = <0>; 1098cc5912abSHeiko Stuebner remote-endpoint = <&dsi_in_vopl>; 1099cc5912abSHeiko Stuebner }; 1100dbb6f778SMiquel Raynal 1101dbb6f778SMiquel Raynal vopl_out_lvds: endpoint@1 { 1102dbb6f778SMiquel Raynal reg = <1>; 1103dbb6f778SMiquel Raynal remote-endpoint = <&lvds_vopl_in>; 1104dbb6f778SMiquel Raynal }; 1105967c1464SSandy Huang }; 11067053e06bSLiang Chen }; 11077053e06bSLiang Chen 11087053e06bSLiang Chen vopl_mmu: iommu@ff470f00 { 11097053e06bSLiang Chen compatible = "rockchip,iommu"; 11107053e06bSLiang Chen reg = <0x0 0xff470f00 0x0 0x100>; 11117053e06bSLiang Chen interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 11127053e06bSLiang Chen interrupt-names = "vopl_mmu"; 11137053e06bSLiang Chen clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 11148e57eed2SHeiko Stuebner clock-names = "aclk", "iface"; 11157053e06bSLiang Chen power-domains = <&power PX30_PD_VO>; 11167053e06bSLiang Chen #iommu-cells = <0>; 11177053e06bSLiang Chen status = "disabled"; 11187053e06bSLiang Chen }; 11197053e06bSLiang Chen 11207053e06bSLiang Chen qos_gmac: qos@ff518000 { 11216c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11227053e06bSLiang Chen reg = <0x0 0xff518000 0x0 0x20>; 11237053e06bSLiang Chen }; 11247053e06bSLiang Chen 11257053e06bSLiang Chen qos_gpu: qos@ff520000 { 11266c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11277053e06bSLiang Chen reg = <0x0 0xff520000 0x0 0x20>; 11287053e06bSLiang Chen }; 11297053e06bSLiang Chen 11307053e06bSLiang Chen qos_sdmmc: qos@ff52c000 { 11316c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11327053e06bSLiang Chen reg = <0x0 0xff52c000 0x0 0x20>; 11337053e06bSLiang Chen }; 11347053e06bSLiang Chen 11357053e06bSLiang Chen qos_emmc: qos@ff538000 { 11366c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11377053e06bSLiang Chen reg = <0x0 0xff538000 0x0 0x20>; 11387053e06bSLiang Chen }; 11397053e06bSLiang Chen 11407053e06bSLiang Chen qos_nand: qos@ff538080 { 11416c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11427053e06bSLiang Chen reg = <0x0 0xff538080 0x0 0x20>; 11437053e06bSLiang Chen }; 11447053e06bSLiang Chen 11457053e06bSLiang Chen qos_sdio: qos@ff538100 { 11466c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11477053e06bSLiang Chen reg = <0x0 0xff538100 0x0 0x20>; 11487053e06bSLiang Chen }; 11497053e06bSLiang Chen 11507053e06bSLiang Chen qos_sfc: qos@ff538180 { 11516c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11527053e06bSLiang Chen reg = <0x0 0xff538180 0x0 0x20>; 11537053e06bSLiang Chen }; 11547053e06bSLiang Chen 11557053e06bSLiang Chen qos_usb_host: qos@ff540000 { 11566c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11577053e06bSLiang Chen reg = <0x0 0xff540000 0x0 0x20>; 11587053e06bSLiang Chen }; 11597053e06bSLiang Chen 11607053e06bSLiang Chen qos_usb_otg: qos@ff540080 { 11616c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11627053e06bSLiang Chen reg = <0x0 0xff540080 0x0 0x20>; 11637053e06bSLiang Chen }; 11647053e06bSLiang Chen 11657053e06bSLiang Chen qos_isp_128: qos@ff548000 { 11666c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11677053e06bSLiang Chen reg = <0x0 0xff548000 0x0 0x20>; 11687053e06bSLiang Chen }; 11697053e06bSLiang Chen 11707053e06bSLiang Chen qos_isp_rd: qos@ff548080 { 11716c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11727053e06bSLiang Chen reg = <0x0 0xff548080 0x0 0x20>; 11737053e06bSLiang Chen }; 11747053e06bSLiang Chen 11757053e06bSLiang Chen qos_isp_wr: qos@ff548100 { 11766c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11777053e06bSLiang Chen reg = <0x0 0xff548100 0x0 0x20>; 11787053e06bSLiang Chen }; 11797053e06bSLiang Chen 11807053e06bSLiang Chen qos_isp_m1: qos@ff548180 { 11816c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11827053e06bSLiang Chen reg = <0x0 0xff548180 0x0 0x20>; 11837053e06bSLiang Chen }; 11847053e06bSLiang Chen 11857053e06bSLiang Chen qos_vip: qos@ff548200 { 11866c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11877053e06bSLiang Chen reg = <0x0 0xff548200 0x0 0x20>; 11887053e06bSLiang Chen }; 11897053e06bSLiang Chen 11907053e06bSLiang Chen qos_rga_rd: qos@ff550000 { 11916c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11927053e06bSLiang Chen reg = <0x0 0xff550000 0x0 0x20>; 11937053e06bSLiang Chen }; 11947053e06bSLiang Chen 11957053e06bSLiang Chen qos_rga_wr: qos@ff550080 { 11966c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 11977053e06bSLiang Chen reg = <0x0 0xff550080 0x0 0x20>; 11987053e06bSLiang Chen }; 11997053e06bSLiang Chen 12007053e06bSLiang Chen qos_vop_m0: qos@ff550100 { 12016c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 12027053e06bSLiang Chen reg = <0x0 0xff550100 0x0 0x20>; 12037053e06bSLiang Chen }; 12047053e06bSLiang Chen 12057053e06bSLiang Chen qos_vop_m1: qos@ff550180 { 12066c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 12077053e06bSLiang Chen reg = <0x0 0xff550180 0x0 0x20>; 12087053e06bSLiang Chen }; 12097053e06bSLiang Chen 12107053e06bSLiang Chen qos_vpu: qos@ff558000 { 12116c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 12127053e06bSLiang Chen reg = <0x0 0xff558000 0x0 0x20>; 12137053e06bSLiang Chen }; 12147053e06bSLiang Chen 12157053e06bSLiang Chen qos_vpu_r128: qos@ff558080 { 12166c3ae9f9SJohan Jonker compatible = "rockchip,px30-qos", "syscon"; 12177053e06bSLiang Chen reg = <0x0 0xff558080 0x0 0x20>; 12187053e06bSLiang Chen }; 12197053e06bSLiang Chen 12207053e06bSLiang Chen pinctrl: pinctrl { 12217053e06bSLiang Chen compatible = "rockchip,px30-pinctrl"; 12227053e06bSLiang Chen rockchip,grf = <&grf>; 12237053e06bSLiang Chen rockchip,pmu = <&pmugrf>; 12247053e06bSLiang Chen #address-cells = <2>; 12257053e06bSLiang Chen #size-cells = <2>; 12267053e06bSLiang Chen ranges; 12277053e06bSLiang Chen 12287053e06bSLiang Chen gpio0: gpio0@ff040000 { 12297053e06bSLiang Chen compatible = "rockchip,gpio-bank"; 12307053e06bSLiang Chen reg = <0x0 0xff040000 0x0 0x100>; 12317053e06bSLiang Chen interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 12327053e06bSLiang Chen clocks = <&pmucru PCLK_GPIO0_PMU>; 12337053e06bSLiang Chen gpio-controller; 12347053e06bSLiang Chen #gpio-cells = <2>; 12357053e06bSLiang Chen 12367053e06bSLiang Chen interrupt-controller; 12377053e06bSLiang Chen #interrupt-cells = <2>; 12387053e06bSLiang Chen }; 12397053e06bSLiang Chen 12407053e06bSLiang Chen gpio1: gpio1@ff250000 { 12417053e06bSLiang Chen compatible = "rockchip,gpio-bank"; 12427053e06bSLiang Chen reg = <0x0 0xff250000 0x0 0x100>; 12437053e06bSLiang Chen interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 12447053e06bSLiang Chen clocks = <&cru PCLK_GPIO1>; 12457053e06bSLiang Chen gpio-controller; 12467053e06bSLiang Chen #gpio-cells = <2>; 12477053e06bSLiang Chen 12487053e06bSLiang Chen interrupt-controller; 12497053e06bSLiang Chen #interrupt-cells = <2>; 12507053e06bSLiang Chen }; 12517053e06bSLiang Chen 12527053e06bSLiang Chen gpio2: gpio2@ff260000 { 12537053e06bSLiang Chen compatible = "rockchip,gpio-bank"; 12547053e06bSLiang Chen reg = <0x0 0xff260000 0x0 0x100>; 12557053e06bSLiang Chen interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 12567053e06bSLiang Chen clocks = <&cru PCLK_GPIO2>; 12577053e06bSLiang Chen gpio-controller; 12587053e06bSLiang Chen #gpio-cells = <2>; 12597053e06bSLiang Chen 12607053e06bSLiang Chen interrupt-controller; 12617053e06bSLiang Chen #interrupt-cells = <2>; 12627053e06bSLiang Chen }; 12637053e06bSLiang Chen 12647053e06bSLiang Chen gpio3: gpio3@ff270000 { 12657053e06bSLiang Chen compatible = "rockchip,gpio-bank"; 12667053e06bSLiang Chen reg = <0x0 0xff270000 0x0 0x100>; 12677053e06bSLiang Chen interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 12687053e06bSLiang Chen clocks = <&cru PCLK_GPIO3>; 12697053e06bSLiang Chen gpio-controller; 12707053e06bSLiang Chen #gpio-cells = <2>; 12717053e06bSLiang Chen 12727053e06bSLiang Chen interrupt-controller; 12737053e06bSLiang Chen #interrupt-cells = <2>; 12747053e06bSLiang Chen }; 12757053e06bSLiang Chen 12767053e06bSLiang Chen pcfg_pull_up: pcfg-pull-up { 12777053e06bSLiang Chen bias-pull-up; 12787053e06bSLiang Chen }; 12797053e06bSLiang Chen 12807053e06bSLiang Chen pcfg_pull_down: pcfg-pull-down { 12817053e06bSLiang Chen bias-pull-down; 12827053e06bSLiang Chen }; 12837053e06bSLiang Chen 12847053e06bSLiang Chen pcfg_pull_none: pcfg-pull-none { 12857053e06bSLiang Chen bias-disable; 12867053e06bSLiang Chen }; 12877053e06bSLiang Chen 12887053e06bSLiang Chen pcfg_pull_none_2ma: pcfg-pull-none-2ma { 12897053e06bSLiang Chen bias-disable; 12907053e06bSLiang Chen drive-strength = <2>; 12917053e06bSLiang Chen }; 12927053e06bSLiang Chen 12937053e06bSLiang Chen pcfg_pull_up_2ma: pcfg-pull-up-2ma { 12947053e06bSLiang Chen bias-pull-up; 12957053e06bSLiang Chen drive-strength = <2>; 12967053e06bSLiang Chen }; 12977053e06bSLiang Chen 12987053e06bSLiang Chen pcfg_pull_up_4ma: pcfg-pull-up-4ma { 12997053e06bSLiang Chen bias-pull-up; 13007053e06bSLiang Chen drive-strength = <4>; 13017053e06bSLiang Chen }; 13027053e06bSLiang Chen 13037053e06bSLiang Chen pcfg_pull_none_4ma: pcfg-pull-none-4ma { 13047053e06bSLiang Chen bias-disable; 13057053e06bSLiang Chen drive-strength = <4>; 13067053e06bSLiang Chen }; 13077053e06bSLiang Chen 13087053e06bSLiang Chen pcfg_pull_down_4ma: pcfg-pull-down-4ma { 13097053e06bSLiang Chen bias-pull-down; 13107053e06bSLiang Chen drive-strength = <4>; 13117053e06bSLiang Chen }; 13127053e06bSLiang Chen 13137053e06bSLiang Chen pcfg_pull_none_8ma: pcfg-pull-none-8ma { 13147053e06bSLiang Chen bias-disable; 13157053e06bSLiang Chen drive-strength = <8>; 13167053e06bSLiang Chen }; 13177053e06bSLiang Chen 13187053e06bSLiang Chen pcfg_pull_up_8ma: pcfg-pull-up-8ma { 13197053e06bSLiang Chen bias-pull-up; 13207053e06bSLiang Chen drive-strength = <8>; 13217053e06bSLiang Chen }; 13227053e06bSLiang Chen 13237053e06bSLiang Chen pcfg_pull_none_12ma: pcfg-pull-none-12ma { 13247053e06bSLiang Chen bias-disable; 13257053e06bSLiang Chen drive-strength = <12>; 13267053e06bSLiang Chen }; 13277053e06bSLiang Chen 13287053e06bSLiang Chen pcfg_pull_up_12ma: pcfg-pull-up-12ma { 13297053e06bSLiang Chen bias-pull-up; 13307053e06bSLiang Chen drive-strength = <12>; 13317053e06bSLiang Chen }; 13327053e06bSLiang Chen 13337053e06bSLiang Chen pcfg_pull_none_smt: pcfg-pull-none-smt { 13347053e06bSLiang Chen bias-disable; 13357053e06bSLiang Chen input-schmitt-enable; 13367053e06bSLiang Chen }; 13377053e06bSLiang Chen 13387053e06bSLiang Chen pcfg_output_high: pcfg-output-high { 13397053e06bSLiang Chen output-high; 13407053e06bSLiang Chen }; 13417053e06bSLiang Chen 13427053e06bSLiang Chen pcfg_output_low: pcfg-output-low { 13437053e06bSLiang Chen output-low; 13447053e06bSLiang Chen }; 13457053e06bSLiang Chen 13467053e06bSLiang Chen pcfg_input_high: pcfg-input-high { 13477053e06bSLiang Chen bias-pull-up; 13487053e06bSLiang Chen input-enable; 13497053e06bSLiang Chen }; 13507053e06bSLiang Chen 13517053e06bSLiang Chen pcfg_input: pcfg-input { 13527053e06bSLiang Chen input-enable; 13537053e06bSLiang Chen }; 13547053e06bSLiang Chen 13557053e06bSLiang Chen i2c0 { 13567053e06bSLiang Chen i2c0_xfer: i2c0-xfer { 13577053e06bSLiang Chen rockchip,pins = 13587053e06bSLiang Chen <0 RK_PB0 1 &pcfg_pull_none_smt>, 13597053e06bSLiang Chen <0 RK_PB1 1 &pcfg_pull_none_smt>; 13607053e06bSLiang Chen }; 13617053e06bSLiang Chen }; 13627053e06bSLiang Chen 13637053e06bSLiang Chen i2c1 { 13647053e06bSLiang Chen i2c1_xfer: i2c1-xfer { 13657053e06bSLiang Chen rockchip,pins = 13667053e06bSLiang Chen <0 RK_PC2 1 &pcfg_pull_none_smt>, 13677053e06bSLiang Chen <0 RK_PC3 1 &pcfg_pull_none_smt>; 13687053e06bSLiang Chen }; 13697053e06bSLiang Chen }; 13707053e06bSLiang Chen 13717053e06bSLiang Chen i2c2 { 13727053e06bSLiang Chen i2c2_xfer: i2c2-xfer { 13737053e06bSLiang Chen rockchip,pins = 13747053e06bSLiang Chen <2 RK_PB7 2 &pcfg_pull_none_smt>, 13757053e06bSLiang Chen <2 RK_PC0 2 &pcfg_pull_none_smt>; 13767053e06bSLiang Chen }; 13777053e06bSLiang Chen }; 13787053e06bSLiang Chen 13797053e06bSLiang Chen i2c3 { 13807053e06bSLiang Chen i2c3_xfer: i2c3-xfer { 13817053e06bSLiang Chen rockchip,pins = 13827053e06bSLiang Chen <1 RK_PB4 4 &pcfg_pull_none_smt>, 13837053e06bSLiang Chen <1 RK_PB5 4 &pcfg_pull_none_smt>; 13847053e06bSLiang Chen }; 13857053e06bSLiang Chen }; 13867053e06bSLiang Chen 13877053e06bSLiang Chen tsadc { 13882bc65fefSJohan Jonker tsadc_otp_pin: tsadc-otp-pin { 13897053e06bSLiang Chen rockchip,pins = 13907053e06bSLiang Chen <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 13917053e06bSLiang Chen }; 13927053e06bSLiang Chen 13937053e06bSLiang Chen tsadc_otp_out: tsadc-otp-out { 13947053e06bSLiang Chen rockchip,pins = 13957053e06bSLiang Chen <0 RK_PA6 1 &pcfg_pull_none>; 13967053e06bSLiang Chen }; 13977053e06bSLiang Chen }; 13987053e06bSLiang Chen 13997053e06bSLiang Chen uart0 { 14007053e06bSLiang Chen uart0_xfer: uart0-xfer { 14017053e06bSLiang Chen rockchip,pins = 14027053e06bSLiang Chen <0 RK_PB2 1 &pcfg_pull_up>, 14037053e06bSLiang Chen <0 RK_PB3 1 &pcfg_pull_up>; 14047053e06bSLiang Chen }; 14057053e06bSLiang Chen 14067053e06bSLiang Chen uart0_cts: uart0-cts { 14077053e06bSLiang Chen rockchip,pins = 14087053e06bSLiang Chen <0 RK_PB4 1 &pcfg_pull_none>; 14097053e06bSLiang Chen }; 14107053e06bSLiang Chen 14117053e06bSLiang Chen uart0_rts: uart0-rts { 14127053e06bSLiang Chen rockchip,pins = 14137053e06bSLiang Chen <0 RK_PB5 1 &pcfg_pull_none>; 14147053e06bSLiang Chen }; 14157053e06bSLiang Chen }; 14167053e06bSLiang Chen 14177053e06bSLiang Chen uart1 { 14187053e06bSLiang Chen uart1_xfer: uart1-xfer { 14197053e06bSLiang Chen rockchip,pins = 14207053e06bSLiang Chen <1 RK_PC1 1 &pcfg_pull_up>, 14217053e06bSLiang Chen <1 RK_PC0 1 &pcfg_pull_up>; 14227053e06bSLiang Chen }; 14237053e06bSLiang Chen 14247053e06bSLiang Chen uart1_cts: uart1-cts { 14257053e06bSLiang Chen rockchip,pins = 14267053e06bSLiang Chen <1 RK_PC2 1 &pcfg_pull_none>; 14277053e06bSLiang Chen }; 14287053e06bSLiang Chen 14297053e06bSLiang Chen uart1_rts: uart1-rts { 14307053e06bSLiang Chen rockchip,pins = 14317053e06bSLiang Chen <1 RK_PC3 1 &pcfg_pull_none>; 14327053e06bSLiang Chen }; 14337053e06bSLiang Chen }; 14347053e06bSLiang Chen 14357053e06bSLiang Chen uart2-m0 { 14367053e06bSLiang Chen uart2m0_xfer: uart2m0-xfer { 14377053e06bSLiang Chen rockchip,pins = 14387053e06bSLiang Chen <1 RK_PD2 2 &pcfg_pull_up>, 14397053e06bSLiang Chen <1 RK_PD3 2 &pcfg_pull_up>; 14407053e06bSLiang Chen }; 14417053e06bSLiang Chen }; 14427053e06bSLiang Chen 14437053e06bSLiang Chen uart2-m1 { 14447053e06bSLiang Chen uart2m1_xfer: uart2m1-xfer { 14457053e06bSLiang Chen rockchip,pins = 14467053e06bSLiang Chen <2 RK_PB4 2 &pcfg_pull_up>, 14477053e06bSLiang Chen <2 RK_PB6 2 &pcfg_pull_up>; 14487053e06bSLiang Chen }; 14497053e06bSLiang Chen }; 14507053e06bSLiang Chen 14517053e06bSLiang Chen uart3-m0 { 14527053e06bSLiang Chen uart3m0_xfer: uart3m0-xfer { 14537053e06bSLiang Chen rockchip,pins = 14547053e06bSLiang Chen <0 RK_PC0 2 &pcfg_pull_up>, 14557053e06bSLiang Chen <0 RK_PC1 2 &pcfg_pull_up>; 14567053e06bSLiang Chen }; 14577053e06bSLiang Chen 14587053e06bSLiang Chen uart3m0_cts: uart3m0-cts { 14597053e06bSLiang Chen rockchip,pins = 14607053e06bSLiang Chen <0 RK_PC2 2 &pcfg_pull_none>; 14617053e06bSLiang Chen }; 14627053e06bSLiang Chen 14637053e06bSLiang Chen uart3m0_rts: uart3m0-rts { 14647053e06bSLiang Chen rockchip,pins = 14657053e06bSLiang Chen <0 RK_PC3 2 &pcfg_pull_none>; 14667053e06bSLiang Chen }; 14677053e06bSLiang Chen }; 14687053e06bSLiang Chen 14697053e06bSLiang Chen uart3-m1 { 14707053e06bSLiang Chen uart3m1_xfer: uart3m1-xfer { 14717053e06bSLiang Chen rockchip,pins = 14727053e06bSLiang Chen <1 RK_PB6 2 &pcfg_pull_up>, 14737053e06bSLiang Chen <1 RK_PB7 2 &pcfg_pull_up>; 14747053e06bSLiang Chen }; 14757053e06bSLiang Chen 14767053e06bSLiang Chen uart3m1_cts: uart3m1-cts { 14777053e06bSLiang Chen rockchip,pins = 14787053e06bSLiang Chen <1 RK_PB4 2 &pcfg_pull_none>; 14797053e06bSLiang Chen }; 14807053e06bSLiang Chen 14817053e06bSLiang Chen uart3m1_rts: uart3m1-rts { 14827053e06bSLiang Chen rockchip,pins = 14837053e06bSLiang Chen <1 RK_PB5 2 &pcfg_pull_none>; 14847053e06bSLiang Chen }; 14857053e06bSLiang Chen }; 14867053e06bSLiang Chen 14877053e06bSLiang Chen uart4 { 14887053e06bSLiang Chen uart4_xfer: uart4-xfer { 14897053e06bSLiang Chen rockchip,pins = 14907053e06bSLiang Chen <1 RK_PD4 2 &pcfg_pull_up>, 14917053e06bSLiang Chen <1 RK_PD5 2 &pcfg_pull_up>; 14927053e06bSLiang Chen }; 14937053e06bSLiang Chen 14947053e06bSLiang Chen uart4_cts: uart4-cts { 14957053e06bSLiang Chen rockchip,pins = 14967053e06bSLiang Chen <1 RK_PD6 2 &pcfg_pull_none>; 14977053e06bSLiang Chen }; 14987053e06bSLiang Chen 14997053e06bSLiang Chen uart4_rts: uart4-rts { 15007053e06bSLiang Chen rockchip,pins = 15017053e06bSLiang Chen <1 RK_PD7 2 &pcfg_pull_none>; 15027053e06bSLiang Chen }; 15037053e06bSLiang Chen }; 15047053e06bSLiang Chen 15057053e06bSLiang Chen uart5 { 15067053e06bSLiang Chen uart5_xfer: uart5-xfer { 15077053e06bSLiang Chen rockchip,pins = 15087053e06bSLiang Chen <3 RK_PA2 4 &pcfg_pull_up>, 15097053e06bSLiang Chen <3 RK_PA1 4 &pcfg_pull_up>; 15107053e06bSLiang Chen }; 15117053e06bSLiang Chen 15127053e06bSLiang Chen uart5_cts: uart5-cts { 15137053e06bSLiang Chen rockchip,pins = 15147053e06bSLiang Chen <3 RK_PA3 4 &pcfg_pull_none>; 15157053e06bSLiang Chen }; 15167053e06bSLiang Chen 15177053e06bSLiang Chen uart5_rts: uart5-rts { 15187053e06bSLiang Chen rockchip,pins = 15197053e06bSLiang Chen <3 RK_PA5 4 &pcfg_pull_none>; 15207053e06bSLiang Chen }; 15217053e06bSLiang Chen }; 15227053e06bSLiang Chen 15237053e06bSLiang Chen spi0 { 15247053e06bSLiang Chen spi0_clk: spi0-clk { 15257053e06bSLiang Chen rockchip,pins = 15267053e06bSLiang Chen <1 RK_PB7 3 &pcfg_pull_up_4ma>; 15277053e06bSLiang Chen }; 15287053e06bSLiang Chen 15297053e06bSLiang Chen spi0_csn: spi0-csn { 15307053e06bSLiang Chen rockchip,pins = 15317053e06bSLiang Chen <1 RK_PB6 3 &pcfg_pull_up_4ma>; 15327053e06bSLiang Chen }; 15337053e06bSLiang Chen 15347053e06bSLiang Chen spi0_miso: spi0-miso { 15357053e06bSLiang Chen rockchip,pins = 15367053e06bSLiang Chen <1 RK_PB5 3 &pcfg_pull_up_4ma>; 15377053e06bSLiang Chen }; 15387053e06bSLiang Chen 15397053e06bSLiang Chen spi0_mosi: spi0-mosi { 15407053e06bSLiang Chen rockchip,pins = 15417053e06bSLiang Chen <1 RK_PB4 3 &pcfg_pull_up_4ma>; 15427053e06bSLiang Chen }; 15437053e06bSLiang Chen 15447053e06bSLiang Chen spi0_clk_hs: spi0-clk-hs { 15457053e06bSLiang Chen rockchip,pins = 15467053e06bSLiang Chen <1 RK_PB7 3 &pcfg_pull_up_8ma>; 15477053e06bSLiang Chen }; 15487053e06bSLiang Chen 15497053e06bSLiang Chen spi0_miso_hs: spi0-miso-hs { 15507053e06bSLiang Chen rockchip,pins = 15517053e06bSLiang Chen <1 RK_PB5 3 &pcfg_pull_up_8ma>; 15527053e06bSLiang Chen }; 15537053e06bSLiang Chen 15547053e06bSLiang Chen spi0_mosi_hs: spi0-mosi-hs { 15557053e06bSLiang Chen rockchip,pins = 15567053e06bSLiang Chen <1 RK_PB4 3 &pcfg_pull_up_8ma>; 15577053e06bSLiang Chen }; 15587053e06bSLiang Chen }; 15597053e06bSLiang Chen 15607053e06bSLiang Chen spi1 { 15617053e06bSLiang Chen spi1_clk: spi1-clk { 15627053e06bSLiang Chen rockchip,pins = 15637053e06bSLiang Chen <3 RK_PB7 4 &pcfg_pull_up_4ma>; 15647053e06bSLiang Chen }; 15657053e06bSLiang Chen 15667053e06bSLiang Chen spi1_csn0: spi1-csn0 { 15677053e06bSLiang Chen rockchip,pins = 15687053e06bSLiang Chen <3 RK_PB1 4 &pcfg_pull_up_4ma>; 15697053e06bSLiang Chen }; 15707053e06bSLiang Chen 15717053e06bSLiang Chen spi1_csn1: spi1-csn1 { 15727053e06bSLiang Chen rockchip,pins = 15737053e06bSLiang Chen <3 RK_PB2 2 &pcfg_pull_up_4ma>; 15747053e06bSLiang Chen }; 15757053e06bSLiang Chen 15767053e06bSLiang Chen spi1_miso: spi1-miso { 15777053e06bSLiang Chen rockchip,pins = 15787053e06bSLiang Chen <3 RK_PB6 4 &pcfg_pull_up_4ma>; 15797053e06bSLiang Chen }; 15807053e06bSLiang Chen 15817053e06bSLiang Chen spi1_mosi: spi1-mosi { 15827053e06bSLiang Chen rockchip,pins = 15837053e06bSLiang Chen <3 RK_PB4 4 &pcfg_pull_up_4ma>; 15847053e06bSLiang Chen }; 15857053e06bSLiang Chen 15867053e06bSLiang Chen spi1_clk_hs: spi1-clk-hs { 15877053e06bSLiang Chen rockchip,pins = 15887053e06bSLiang Chen <3 RK_PB7 4 &pcfg_pull_up_8ma>; 15897053e06bSLiang Chen }; 15907053e06bSLiang Chen 15917053e06bSLiang Chen spi1_miso_hs: spi1-miso-hs { 15927053e06bSLiang Chen rockchip,pins = 15937053e06bSLiang Chen <3 RK_PB6 4 &pcfg_pull_up_8ma>; 15947053e06bSLiang Chen }; 15957053e06bSLiang Chen 15967053e06bSLiang Chen spi1_mosi_hs: spi1-mosi-hs { 15977053e06bSLiang Chen rockchip,pins = 15987053e06bSLiang Chen <3 RK_PB4 4 &pcfg_pull_up_8ma>; 15997053e06bSLiang Chen }; 16007053e06bSLiang Chen }; 16017053e06bSLiang Chen 16027053e06bSLiang Chen pdm { 16037053e06bSLiang Chen pdm_clk0m0: pdm-clk0m0 { 16047053e06bSLiang Chen rockchip,pins = 16057053e06bSLiang Chen <3 RK_PC6 2 &pcfg_pull_none>; 16067053e06bSLiang Chen }; 16077053e06bSLiang Chen 16087053e06bSLiang Chen pdm_clk0m1: pdm-clk0m1 { 16097053e06bSLiang Chen rockchip,pins = 16107053e06bSLiang Chen <2 RK_PC6 1 &pcfg_pull_none>; 16117053e06bSLiang Chen }; 16127053e06bSLiang Chen 16137053e06bSLiang Chen pdm_clk1: pdm-clk1 { 16147053e06bSLiang Chen rockchip,pins = 16157053e06bSLiang Chen <3 RK_PC7 2 &pcfg_pull_none>; 16167053e06bSLiang Chen }; 16177053e06bSLiang Chen 16187053e06bSLiang Chen pdm_sdi0m0: pdm-sdi0m0 { 16197053e06bSLiang Chen rockchip,pins = 16207053e06bSLiang Chen <3 RK_PD3 2 &pcfg_pull_none>; 16217053e06bSLiang Chen }; 16227053e06bSLiang Chen 16237053e06bSLiang Chen pdm_sdi0m1: pdm-sdi0m1 { 16247053e06bSLiang Chen rockchip,pins = 16257053e06bSLiang Chen <2 RK_PC5 2 &pcfg_pull_none>; 16267053e06bSLiang Chen }; 16277053e06bSLiang Chen 16287053e06bSLiang Chen pdm_sdi1: pdm-sdi1 { 16297053e06bSLiang Chen rockchip,pins = 16307053e06bSLiang Chen <3 RK_PD0 2 &pcfg_pull_none>; 16317053e06bSLiang Chen }; 16327053e06bSLiang Chen 16337053e06bSLiang Chen pdm_sdi2: pdm-sdi2 { 16347053e06bSLiang Chen rockchip,pins = 16357053e06bSLiang Chen <3 RK_PD1 2 &pcfg_pull_none>; 16367053e06bSLiang Chen }; 16377053e06bSLiang Chen 16387053e06bSLiang Chen pdm_sdi3: pdm-sdi3 { 16397053e06bSLiang Chen rockchip,pins = 16407053e06bSLiang Chen <3 RK_PD2 2 &pcfg_pull_none>; 16417053e06bSLiang Chen }; 16427053e06bSLiang Chen 16437053e06bSLiang Chen pdm_clk0m0_sleep: pdm-clk0m0-sleep { 16447053e06bSLiang Chen rockchip,pins = 16457053e06bSLiang Chen <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 16467053e06bSLiang Chen }; 16477053e06bSLiang Chen 16487053e06bSLiang Chen pdm_clk0m_sleep1: pdm-clk0m1-sleep { 16497053e06bSLiang Chen rockchip,pins = 16507053e06bSLiang Chen <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 16517053e06bSLiang Chen }; 16527053e06bSLiang Chen 16537053e06bSLiang Chen pdm_clk1_sleep: pdm-clk1-sleep { 16547053e06bSLiang Chen rockchip,pins = 16557053e06bSLiang Chen <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 16567053e06bSLiang Chen }; 16577053e06bSLiang Chen 16587053e06bSLiang Chen pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 16597053e06bSLiang Chen rockchip,pins = 16607053e06bSLiang Chen <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 16617053e06bSLiang Chen }; 16627053e06bSLiang Chen 16637053e06bSLiang Chen pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 16647053e06bSLiang Chen rockchip,pins = 16657053e06bSLiang Chen <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 16667053e06bSLiang Chen }; 16677053e06bSLiang Chen 16687053e06bSLiang Chen pdm_sdi1_sleep: pdm-sdi1-sleep { 16697053e06bSLiang Chen rockchip,pins = 16707053e06bSLiang Chen <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 16717053e06bSLiang Chen }; 16727053e06bSLiang Chen 16737053e06bSLiang Chen pdm_sdi2_sleep: pdm-sdi2-sleep { 16747053e06bSLiang Chen rockchip,pins = 16757053e06bSLiang Chen <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 16767053e06bSLiang Chen }; 16777053e06bSLiang Chen 16787053e06bSLiang Chen pdm_sdi3_sleep: pdm-sdi3-sleep { 16797053e06bSLiang Chen rockchip,pins = 16807053e06bSLiang Chen <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 16817053e06bSLiang Chen }; 16827053e06bSLiang Chen }; 16837053e06bSLiang Chen 16847053e06bSLiang Chen i2s0 { 16857053e06bSLiang Chen i2s0_8ch_mclk: i2s0-8ch-mclk { 16867053e06bSLiang Chen rockchip,pins = 16877053e06bSLiang Chen <3 RK_PC1 2 &pcfg_pull_none>; 16887053e06bSLiang Chen }; 16897053e06bSLiang Chen 16907053e06bSLiang Chen i2s0_8ch_sclktx: i2s0-8ch-sclktx { 16917053e06bSLiang Chen rockchip,pins = 16927053e06bSLiang Chen <3 RK_PC3 2 &pcfg_pull_none>; 16937053e06bSLiang Chen }; 16947053e06bSLiang Chen 16957053e06bSLiang Chen i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 16967053e06bSLiang Chen rockchip,pins = 16977053e06bSLiang Chen <3 RK_PB4 2 &pcfg_pull_none>; 16987053e06bSLiang Chen }; 16997053e06bSLiang Chen 17007053e06bSLiang Chen i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 17017053e06bSLiang Chen rockchip,pins = 17027053e06bSLiang Chen <3 RK_PC2 2 &pcfg_pull_none>; 17037053e06bSLiang Chen }; 17047053e06bSLiang Chen 17057053e06bSLiang Chen i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 17067053e06bSLiang Chen rockchip,pins = 17077053e06bSLiang Chen <3 RK_PB5 2 &pcfg_pull_none>; 17087053e06bSLiang Chen }; 17097053e06bSLiang Chen 17107053e06bSLiang Chen i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 17117053e06bSLiang Chen rockchip,pins = 17127053e06bSLiang Chen <3 RK_PC4 2 &pcfg_pull_none>; 17137053e06bSLiang Chen }; 17147053e06bSLiang Chen 17157053e06bSLiang Chen i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 17167053e06bSLiang Chen rockchip,pins = 17177053e06bSLiang Chen <3 RK_PC0 2 &pcfg_pull_none>; 17187053e06bSLiang Chen }; 17197053e06bSLiang Chen 17207053e06bSLiang Chen i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 17217053e06bSLiang Chen rockchip,pins = 17227053e06bSLiang Chen <3 RK_PB7 2 &pcfg_pull_none>; 17237053e06bSLiang Chen }; 17247053e06bSLiang Chen 17257053e06bSLiang Chen i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 17267053e06bSLiang Chen rockchip,pins = 17277053e06bSLiang Chen <3 RK_PB6 2 &pcfg_pull_none>; 17287053e06bSLiang Chen }; 17297053e06bSLiang Chen 17307053e06bSLiang Chen i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 17317053e06bSLiang Chen rockchip,pins = 17327053e06bSLiang Chen <3 RK_PC5 2 &pcfg_pull_none>; 17337053e06bSLiang Chen }; 17347053e06bSLiang Chen 17357053e06bSLiang Chen i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 17367053e06bSLiang Chen rockchip,pins = 17377053e06bSLiang Chen <3 RK_PB3 2 &pcfg_pull_none>; 17387053e06bSLiang Chen }; 17397053e06bSLiang Chen 17407053e06bSLiang Chen i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 17417053e06bSLiang Chen rockchip,pins = 17427053e06bSLiang Chen <3 RK_PB1 2 &pcfg_pull_none>; 17437053e06bSLiang Chen }; 17447053e06bSLiang Chen 17457053e06bSLiang Chen i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 17467053e06bSLiang Chen rockchip,pins = 17477053e06bSLiang Chen <3 RK_PB0 2 &pcfg_pull_none>; 17487053e06bSLiang Chen }; 17497053e06bSLiang Chen }; 17507053e06bSLiang Chen 17517053e06bSLiang Chen i2s1 { 17527053e06bSLiang Chen i2s1_2ch_mclk: i2s1-2ch-mclk { 17537053e06bSLiang Chen rockchip,pins = 17547053e06bSLiang Chen <2 RK_PC3 1 &pcfg_pull_none>; 17557053e06bSLiang Chen }; 17567053e06bSLiang Chen 17577053e06bSLiang Chen i2s1_2ch_sclk: i2s1-2ch-sclk { 17587053e06bSLiang Chen rockchip,pins = 17597053e06bSLiang Chen <2 RK_PC2 1 &pcfg_pull_none>; 17607053e06bSLiang Chen }; 17617053e06bSLiang Chen 17627053e06bSLiang Chen i2s1_2ch_lrck: i2s1-2ch-lrck { 17637053e06bSLiang Chen rockchip,pins = 17647053e06bSLiang Chen <2 RK_PC1 1 &pcfg_pull_none>; 17657053e06bSLiang Chen }; 17667053e06bSLiang Chen 17677053e06bSLiang Chen i2s1_2ch_sdi: i2s1-2ch-sdi { 17687053e06bSLiang Chen rockchip,pins = 17697053e06bSLiang Chen <2 RK_PC5 1 &pcfg_pull_none>; 17707053e06bSLiang Chen }; 17717053e06bSLiang Chen 17727053e06bSLiang Chen i2s1_2ch_sdo: i2s1-2ch-sdo { 17737053e06bSLiang Chen rockchip,pins = 17747053e06bSLiang Chen <2 RK_PC4 1 &pcfg_pull_none>; 17757053e06bSLiang Chen }; 17767053e06bSLiang Chen }; 17777053e06bSLiang Chen 17787053e06bSLiang Chen i2s2 { 17797053e06bSLiang Chen i2s2_2ch_mclk: i2s2-2ch-mclk { 17807053e06bSLiang Chen rockchip,pins = 17817053e06bSLiang Chen <3 RK_PA1 2 &pcfg_pull_none>; 17827053e06bSLiang Chen }; 17837053e06bSLiang Chen 17847053e06bSLiang Chen i2s2_2ch_sclk: i2s2-2ch-sclk { 17857053e06bSLiang Chen rockchip,pins = 17867053e06bSLiang Chen <3 RK_PA2 2 &pcfg_pull_none>; 17877053e06bSLiang Chen }; 17887053e06bSLiang Chen 17897053e06bSLiang Chen i2s2_2ch_lrck: i2s2-2ch-lrck { 17907053e06bSLiang Chen rockchip,pins = 17917053e06bSLiang Chen <3 RK_PA3 2 &pcfg_pull_none>; 17927053e06bSLiang Chen }; 17937053e06bSLiang Chen 17947053e06bSLiang Chen i2s2_2ch_sdi: i2s2-2ch-sdi { 17957053e06bSLiang Chen rockchip,pins = 17967053e06bSLiang Chen <3 RK_PA5 2 &pcfg_pull_none>; 17977053e06bSLiang Chen }; 17987053e06bSLiang Chen 17997053e06bSLiang Chen i2s2_2ch_sdo: i2s2-2ch-sdo { 18007053e06bSLiang Chen rockchip,pins = 18017053e06bSLiang Chen <3 RK_PA7 2 &pcfg_pull_none>; 18027053e06bSLiang Chen }; 18037053e06bSLiang Chen }; 18047053e06bSLiang Chen 18057053e06bSLiang Chen sdmmc { 18067053e06bSLiang Chen sdmmc_clk: sdmmc-clk { 18077053e06bSLiang Chen rockchip,pins = 18087053e06bSLiang Chen <1 RK_PD6 1 &pcfg_pull_none_8ma>; 18097053e06bSLiang Chen }; 18107053e06bSLiang Chen 18117053e06bSLiang Chen sdmmc_cmd: sdmmc-cmd { 18127053e06bSLiang Chen rockchip,pins = 18137053e06bSLiang Chen <1 RK_PD7 1 &pcfg_pull_up_8ma>; 18147053e06bSLiang Chen }; 18157053e06bSLiang Chen 18167053e06bSLiang Chen sdmmc_det: sdmmc-det { 18177053e06bSLiang Chen rockchip,pins = 18187053e06bSLiang Chen <0 RK_PA3 1 &pcfg_pull_up_8ma>; 18197053e06bSLiang Chen }; 18207053e06bSLiang Chen 18217053e06bSLiang Chen sdmmc_bus1: sdmmc-bus1 { 18227053e06bSLiang Chen rockchip,pins = 18237053e06bSLiang Chen <1 RK_PD2 1 &pcfg_pull_up_8ma>; 18247053e06bSLiang Chen }; 18257053e06bSLiang Chen 18267053e06bSLiang Chen sdmmc_bus4: sdmmc-bus4 { 18277053e06bSLiang Chen rockchip,pins = 18287053e06bSLiang Chen <1 RK_PD2 1 &pcfg_pull_up_8ma>, 18297053e06bSLiang Chen <1 RK_PD3 1 &pcfg_pull_up_8ma>, 18307053e06bSLiang Chen <1 RK_PD4 1 &pcfg_pull_up_8ma>, 18317053e06bSLiang Chen <1 RK_PD5 1 &pcfg_pull_up_8ma>; 18327053e06bSLiang Chen }; 18337053e06bSLiang Chen }; 18347053e06bSLiang Chen 18357053e06bSLiang Chen sdio { 18367053e06bSLiang Chen sdio_clk: sdio-clk { 18377053e06bSLiang Chen rockchip,pins = 18387053e06bSLiang Chen <1 RK_PC5 1 &pcfg_pull_none>; 18397053e06bSLiang Chen }; 18407053e06bSLiang Chen 18417053e06bSLiang Chen sdio_cmd: sdio-cmd { 18427053e06bSLiang Chen rockchip,pins = 18437053e06bSLiang Chen <1 RK_PC4 1 &pcfg_pull_up>; 18447053e06bSLiang Chen }; 18457053e06bSLiang Chen 18467053e06bSLiang Chen sdio_bus4: sdio-bus4 { 18477053e06bSLiang Chen rockchip,pins = 18487053e06bSLiang Chen <1 RK_PC6 1 &pcfg_pull_up>, 18497053e06bSLiang Chen <1 RK_PC7 1 &pcfg_pull_up>, 18507053e06bSLiang Chen <1 RK_PD0 1 &pcfg_pull_up>, 18517053e06bSLiang Chen <1 RK_PD1 1 &pcfg_pull_up>; 18527053e06bSLiang Chen }; 18537053e06bSLiang Chen }; 18547053e06bSLiang Chen 18557053e06bSLiang Chen emmc { 18567053e06bSLiang Chen emmc_clk: emmc-clk { 18577053e06bSLiang Chen rockchip,pins = 18587053e06bSLiang Chen <1 RK_PB1 2 &pcfg_pull_none_8ma>; 18597053e06bSLiang Chen }; 18607053e06bSLiang Chen 18617053e06bSLiang Chen emmc_cmd: emmc-cmd { 18627053e06bSLiang Chen rockchip,pins = 18637053e06bSLiang Chen <1 RK_PB2 2 &pcfg_pull_up_8ma>; 18647053e06bSLiang Chen }; 18657053e06bSLiang Chen 18667053e06bSLiang Chen emmc_rstnout: emmc-rstnout { 18677053e06bSLiang Chen rockchip,pins = 18687053e06bSLiang Chen <1 RK_PB3 2 &pcfg_pull_none>; 18697053e06bSLiang Chen }; 18707053e06bSLiang Chen 18717053e06bSLiang Chen emmc_bus1: emmc-bus1 { 18727053e06bSLiang Chen rockchip,pins = 18737053e06bSLiang Chen <1 RK_PA0 2 &pcfg_pull_up_8ma>; 18747053e06bSLiang Chen }; 18757053e06bSLiang Chen 18767053e06bSLiang Chen emmc_bus4: emmc-bus4 { 18777053e06bSLiang Chen rockchip,pins = 18787053e06bSLiang Chen <1 RK_PA0 2 &pcfg_pull_up_8ma>, 18797053e06bSLiang Chen <1 RK_PA1 2 &pcfg_pull_up_8ma>, 18807053e06bSLiang Chen <1 RK_PA2 2 &pcfg_pull_up_8ma>, 18817053e06bSLiang Chen <1 RK_PA3 2 &pcfg_pull_up_8ma>; 18827053e06bSLiang Chen }; 18837053e06bSLiang Chen 18847053e06bSLiang Chen emmc_bus8: emmc-bus8 { 18857053e06bSLiang Chen rockchip,pins = 18867053e06bSLiang Chen <1 RK_PA0 2 &pcfg_pull_up_8ma>, 18877053e06bSLiang Chen <1 RK_PA1 2 &pcfg_pull_up_8ma>, 18887053e06bSLiang Chen <1 RK_PA2 2 &pcfg_pull_up_8ma>, 18897053e06bSLiang Chen <1 RK_PA3 2 &pcfg_pull_up_8ma>, 18907053e06bSLiang Chen <1 RK_PA4 2 &pcfg_pull_up_8ma>, 18917053e06bSLiang Chen <1 RK_PA5 2 &pcfg_pull_up_8ma>, 18927053e06bSLiang Chen <1 RK_PA6 2 &pcfg_pull_up_8ma>, 18937053e06bSLiang Chen <1 RK_PA7 2 &pcfg_pull_up_8ma>; 18947053e06bSLiang Chen }; 18957053e06bSLiang Chen }; 18967053e06bSLiang Chen 18977053e06bSLiang Chen flash { 18987053e06bSLiang Chen flash_cs0: flash-cs0 { 18997053e06bSLiang Chen rockchip,pins = 19007053e06bSLiang Chen <1 RK_PB0 1 &pcfg_pull_none>; 19017053e06bSLiang Chen }; 19027053e06bSLiang Chen 19037053e06bSLiang Chen flash_rdy: flash-rdy { 19047053e06bSLiang Chen rockchip,pins = 19057053e06bSLiang Chen <1 RK_PB1 1 &pcfg_pull_none>; 19067053e06bSLiang Chen }; 19077053e06bSLiang Chen 19087053e06bSLiang Chen flash_dqs: flash-dqs { 19097053e06bSLiang Chen rockchip,pins = 19107053e06bSLiang Chen <1 RK_PB2 1 &pcfg_pull_none>; 19117053e06bSLiang Chen }; 19127053e06bSLiang Chen 19137053e06bSLiang Chen flash_ale: flash-ale { 19147053e06bSLiang Chen rockchip,pins = 19157053e06bSLiang Chen <1 RK_PB3 1 &pcfg_pull_none>; 19167053e06bSLiang Chen }; 19177053e06bSLiang Chen 19187053e06bSLiang Chen flash_cle: flash-cle { 19197053e06bSLiang Chen rockchip,pins = 19207053e06bSLiang Chen <1 RK_PB4 1 &pcfg_pull_none>; 19217053e06bSLiang Chen }; 19227053e06bSLiang Chen 19237053e06bSLiang Chen flash_wrn: flash-wrn { 19247053e06bSLiang Chen rockchip,pins = 19257053e06bSLiang Chen <1 RK_PB5 1 &pcfg_pull_none>; 19267053e06bSLiang Chen }; 19277053e06bSLiang Chen 19287053e06bSLiang Chen flash_csl: flash-csl { 19297053e06bSLiang Chen rockchip,pins = 19307053e06bSLiang Chen <1 RK_PB6 1 &pcfg_pull_none>; 19317053e06bSLiang Chen }; 19327053e06bSLiang Chen 19337053e06bSLiang Chen flash_rdn: flash-rdn { 19347053e06bSLiang Chen rockchip,pins = 19357053e06bSLiang Chen <1 RK_PB7 1 &pcfg_pull_none>; 19367053e06bSLiang Chen }; 19377053e06bSLiang Chen 19387053e06bSLiang Chen flash_bus8: flash-bus8 { 19397053e06bSLiang Chen rockchip,pins = 19407053e06bSLiang Chen <1 RK_PA0 1 &pcfg_pull_up_12ma>, 19417053e06bSLiang Chen <1 RK_PA1 1 &pcfg_pull_up_12ma>, 19427053e06bSLiang Chen <1 RK_PA2 1 &pcfg_pull_up_12ma>, 19437053e06bSLiang Chen <1 RK_PA3 1 &pcfg_pull_up_12ma>, 19447053e06bSLiang Chen <1 RK_PA4 1 &pcfg_pull_up_12ma>, 19457053e06bSLiang Chen <1 RK_PA5 1 &pcfg_pull_up_12ma>, 19467053e06bSLiang Chen <1 RK_PA6 1 &pcfg_pull_up_12ma>, 19477053e06bSLiang Chen <1 RK_PA7 1 &pcfg_pull_up_12ma>; 19487053e06bSLiang Chen }; 19497053e06bSLiang Chen }; 19507053e06bSLiang Chen 19517053e06bSLiang Chen lcdc { 19527053e06bSLiang Chen lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 19537053e06bSLiang Chen rockchip,pins = 19547053e06bSLiang Chen <3 RK_PA0 1 &pcfg_pull_none_12ma>; 19557053e06bSLiang Chen }; 19567053e06bSLiang Chen 19577053e06bSLiang Chen lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 19587053e06bSLiang Chen rockchip,pins = 19597053e06bSLiang Chen <3 RK_PA1 1 &pcfg_pull_none_12ma>; 19607053e06bSLiang Chen }; 19617053e06bSLiang Chen 19627053e06bSLiang Chen lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 19637053e06bSLiang Chen rockchip,pins = 19647053e06bSLiang Chen <3 RK_PA2 1 &pcfg_pull_none_12ma>; 19657053e06bSLiang Chen }; 19667053e06bSLiang Chen 19677053e06bSLiang Chen lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 19687053e06bSLiang Chen rockchip,pins = 19697053e06bSLiang Chen <3 RK_PA3 1 &pcfg_pull_none_12ma>; 19707053e06bSLiang Chen }; 19717053e06bSLiang Chen 19727053e06bSLiang Chen lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 19737053e06bSLiang Chen rockchip,pins = 19747053e06bSLiang Chen <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 19757053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 19767053e06bSLiang Chen <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 19777053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 19787053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 19797053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 19807053e06bSLiang Chen <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 19817053e06bSLiang Chen <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 19827053e06bSLiang Chen <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 19837053e06bSLiang Chen <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 19847053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 19857053e06bSLiang Chen <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 19867053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 19877053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 19887053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 19897053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 19907053e06bSLiang Chen <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 19917053e06bSLiang Chen <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 19927053e06bSLiang Chen <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 19937053e06bSLiang Chen <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 19947053e06bSLiang Chen <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 19957053e06bSLiang Chen <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 19967053e06bSLiang Chen <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 19977053e06bSLiang Chen <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 19987053e06bSLiang Chen }; 19997053e06bSLiang Chen 20007053e06bSLiang Chen lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 20017053e06bSLiang Chen rockchip,pins = 20027053e06bSLiang Chen <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 20037053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20047053e06bSLiang Chen <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 20057053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20067053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20077053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20087053e06bSLiang Chen <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 20097053e06bSLiang Chen <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 20107053e06bSLiang Chen <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 20117053e06bSLiang Chen <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 20127053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20137053e06bSLiang Chen <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 20147053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20157053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20167053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20177053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 20187053e06bSLiang Chen <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 20197053e06bSLiang Chen <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 20207053e06bSLiang Chen }; 20217053e06bSLiang Chen 20227053e06bSLiang Chen lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 20237053e06bSLiang Chen rockchip,pins = 20247053e06bSLiang Chen <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 20257053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20267053e06bSLiang Chen <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 20277053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20287053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20297053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20307053e06bSLiang Chen <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 20317053e06bSLiang Chen <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 20327053e06bSLiang Chen <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 20337053e06bSLiang Chen <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 20347053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20357053e06bSLiang Chen <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 20367053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20377053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20387053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20397053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 20407053e06bSLiang Chen }; 20417053e06bSLiang Chen 20427053e06bSLiang Chen lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 20437053e06bSLiang Chen rockchip,pins = 20447053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20457053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20467053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20477053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20487053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20497053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20507053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20517053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20527053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 20537053e06bSLiang Chen <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 20547053e06bSLiang Chen <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 20557053e06bSLiang Chen <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 20567053e06bSLiang Chen <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 20577053e06bSLiang Chen <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 20587053e06bSLiang Chen <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 20597053e06bSLiang Chen <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 20607053e06bSLiang Chen <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 20617053e06bSLiang Chen }; 20627053e06bSLiang Chen 20637053e06bSLiang Chen lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 20647053e06bSLiang Chen rockchip,pins = 20657053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20667053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20677053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20687053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20697053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20707053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20717053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20727053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20737053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 20747053e06bSLiang Chen <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 20757053e06bSLiang Chen <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 20767053e06bSLiang Chen }; 20777053e06bSLiang Chen 20787053e06bSLiang Chen lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 20797053e06bSLiang Chen rockchip,pins = 20807053e06bSLiang Chen <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 20817053e06bSLiang Chen <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 20827053e06bSLiang Chen <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 20837053e06bSLiang Chen <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 20847053e06bSLiang Chen <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 20857053e06bSLiang Chen <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 20867053e06bSLiang Chen <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 20877053e06bSLiang Chen <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 20887053e06bSLiang Chen <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 20897053e06bSLiang Chen }; 20907053e06bSLiang Chen }; 20917053e06bSLiang Chen 20927053e06bSLiang Chen pwm0 { 20937053e06bSLiang Chen pwm0_pin: pwm0-pin { 20947053e06bSLiang Chen rockchip,pins = 20957053e06bSLiang Chen <0 RK_PB7 1 &pcfg_pull_none>; 20967053e06bSLiang Chen }; 20977053e06bSLiang Chen }; 20987053e06bSLiang Chen 20997053e06bSLiang Chen pwm1 { 21007053e06bSLiang Chen pwm1_pin: pwm1-pin { 21017053e06bSLiang Chen rockchip,pins = 21027053e06bSLiang Chen <0 RK_PC0 1 &pcfg_pull_none>; 21037053e06bSLiang Chen }; 21047053e06bSLiang Chen }; 21057053e06bSLiang Chen 21067053e06bSLiang Chen pwm2 { 21077053e06bSLiang Chen pwm2_pin: pwm2-pin { 21087053e06bSLiang Chen rockchip,pins = 21097053e06bSLiang Chen <2 RK_PB5 1 &pcfg_pull_none>; 21107053e06bSLiang Chen }; 21117053e06bSLiang Chen }; 21127053e06bSLiang Chen 21137053e06bSLiang Chen pwm3 { 21147053e06bSLiang Chen pwm3_pin: pwm3-pin { 21157053e06bSLiang Chen rockchip,pins = 21167053e06bSLiang Chen <0 RK_PC1 1 &pcfg_pull_none>; 21177053e06bSLiang Chen }; 21187053e06bSLiang Chen }; 21197053e06bSLiang Chen 21207053e06bSLiang Chen pwm4 { 21217053e06bSLiang Chen pwm4_pin: pwm4-pin { 21227053e06bSLiang Chen rockchip,pins = 21237053e06bSLiang Chen <3 RK_PC2 3 &pcfg_pull_none>; 21247053e06bSLiang Chen }; 21257053e06bSLiang Chen }; 21267053e06bSLiang Chen 21277053e06bSLiang Chen pwm5 { 21287053e06bSLiang Chen pwm5_pin: pwm5-pin { 21297053e06bSLiang Chen rockchip,pins = 21307053e06bSLiang Chen <3 RK_PC3 3 &pcfg_pull_none>; 21317053e06bSLiang Chen }; 21327053e06bSLiang Chen }; 21337053e06bSLiang Chen 21347053e06bSLiang Chen pwm6 { 21357053e06bSLiang Chen pwm6_pin: pwm6-pin { 21367053e06bSLiang Chen rockchip,pins = 21377053e06bSLiang Chen <3 RK_PC4 3 &pcfg_pull_none>; 21387053e06bSLiang Chen }; 21397053e06bSLiang Chen }; 21407053e06bSLiang Chen 21417053e06bSLiang Chen pwm7 { 21427053e06bSLiang Chen pwm7_pin: pwm7-pin { 21437053e06bSLiang Chen rockchip,pins = 21447053e06bSLiang Chen <3 RK_PC5 3 &pcfg_pull_none>; 21457053e06bSLiang Chen }; 21467053e06bSLiang Chen }; 21477053e06bSLiang Chen 21487053e06bSLiang Chen gmac { 21497053e06bSLiang Chen rmii_pins: rmii-pins { 21507053e06bSLiang Chen rockchip,pins = 21517053e06bSLiang Chen <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 21527053e06bSLiang Chen <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 21537053e06bSLiang Chen <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 21547053e06bSLiang Chen <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 21557053e06bSLiang Chen <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 21567053e06bSLiang Chen <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 21577053e06bSLiang Chen <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 21587053e06bSLiang Chen <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 21597053e06bSLiang Chen <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 21607053e06bSLiang Chen }; 21617053e06bSLiang Chen 21627053e06bSLiang Chen mac_refclk_12ma: mac-refclk-12ma { 21637053e06bSLiang Chen rockchip,pins = 21647053e06bSLiang Chen <2 RK_PB2 2 &pcfg_pull_none_12ma>; 21657053e06bSLiang Chen }; 21667053e06bSLiang Chen 21677053e06bSLiang Chen mac_refclk: mac-refclk { 21687053e06bSLiang Chen rockchip,pins = 21697053e06bSLiang Chen <2 RK_PB2 2 &pcfg_pull_none>; 21707053e06bSLiang Chen }; 21717053e06bSLiang Chen }; 21727053e06bSLiang Chen 21737053e06bSLiang Chen cif-m0 { 21747053e06bSLiang Chen cif_clkout_m0: cif-clkout-m0 { 21757053e06bSLiang Chen rockchip,pins = 21767053e06bSLiang Chen <2 RK_PB3 1 &pcfg_pull_none>; 21777053e06bSLiang Chen }; 21787053e06bSLiang Chen 21797053e06bSLiang Chen dvp_d2d9_m0: dvp-d2d9-m0 { 21807053e06bSLiang Chen rockchip,pins = 21817053e06bSLiang Chen <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 21827053e06bSLiang Chen <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 21837053e06bSLiang Chen <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 21847053e06bSLiang Chen <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 21857053e06bSLiang Chen <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 21867053e06bSLiang Chen <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 21877053e06bSLiang Chen <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 21887053e06bSLiang Chen <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 21897053e06bSLiang Chen <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 21907053e06bSLiang Chen <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 21917053e06bSLiang Chen <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 21927053e06bSLiang Chen <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 21937053e06bSLiang Chen }; 21947053e06bSLiang Chen 21957053e06bSLiang Chen dvp_d0d1_m0: dvp-d0d1-m0 { 21967053e06bSLiang Chen rockchip,pins = 21977053e06bSLiang Chen <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 21987053e06bSLiang Chen <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 21997053e06bSLiang Chen }; 22007053e06bSLiang Chen 22017053e06bSLiang Chen dvp_d10d11_m0:d10-d11-m0 { 22027053e06bSLiang Chen rockchip,pins = 22037053e06bSLiang Chen <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 22047053e06bSLiang Chen <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 22057053e06bSLiang Chen }; 22067053e06bSLiang Chen }; 22077053e06bSLiang Chen 22087053e06bSLiang Chen cif-m1 { 22097053e06bSLiang Chen cif_clkout_m1: cif-clkout-m1 { 22107053e06bSLiang Chen rockchip,pins = 22117053e06bSLiang Chen <3 RK_PD0 3 &pcfg_pull_none>; 22127053e06bSLiang Chen }; 22137053e06bSLiang Chen 22147053e06bSLiang Chen dvp_d2d9_m1: dvp-d2d9-m1 { 22157053e06bSLiang Chen rockchip,pins = 22167053e06bSLiang Chen <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 22177053e06bSLiang Chen <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 22187053e06bSLiang Chen <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 22197053e06bSLiang Chen <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 22207053e06bSLiang Chen <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 22217053e06bSLiang Chen <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 22227053e06bSLiang Chen <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 22237053e06bSLiang Chen <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 22247053e06bSLiang Chen <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 22257053e06bSLiang Chen <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 22267053e06bSLiang Chen <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 22277053e06bSLiang Chen <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 22287053e06bSLiang Chen }; 22297053e06bSLiang Chen 22307053e06bSLiang Chen dvp_d0d1_m1: dvp-d0d1-m1 { 22317053e06bSLiang Chen rockchip,pins = 22327053e06bSLiang Chen <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 22337053e06bSLiang Chen <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 22347053e06bSLiang Chen }; 22357053e06bSLiang Chen 22367053e06bSLiang Chen dvp_d10d11_m1:d10-d11-m1 { 22377053e06bSLiang Chen rockchip,pins = 22387053e06bSLiang Chen <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 22397053e06bSLiang Chen <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 22407053e06bSLiang Chen }; 22417053e06bSLiang Chen }; 22427053e06bSLiang Chen 22437053e06bSLiang Chen isp { 22447053e06bSLiang Chen isp_prelight: isp-prelight { 22457053e06bSLiang Chen rockchip,pins = 22467053e06bSLiang Chen <3 RK_PD1 4 &pcfg_pull_none>; 22477053e06bSLiang Chen }; 22487053e06bSLiang Chen }; 22497053e06bSLiang Chen }; 22507053e06bSLiang Chen}; 2251