1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L SMARC EVK common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11/*
12 * SSI-WM8978
13 *
14 * This command is required when Playback/Capture
15 *
16 *	amixer cset name='Left Input Mixer L2 Switch' on
17 *	amixer cset name='Right Input Mixer R2 Switch' on
18 *	amixer cset name='Headphone Playback Volume' 100
19 *	amixer cset name='PCM Volume' 100%
20 *	amixer cset name='Input PGA Volume' 25
21 *
22 */
23
24/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
25#define PMOD1_SER0	1
26
27/ {
28	aliases {
29		serial0 = &scif0;
30		serial1 = &scif2;
31		i2c0 = &i2c0;
32		i2c1 = &i2c1;
33		i2c3 = &i2c3;
34	};
35
36	chosen {
37		stdout-path = "serial0:115200n8";
38	};
39
40	audio_mclock: audio_mclock {
41		compatible = "fixed-clock";
42		#clock-cells = <0>;
43		clock-frequency = <11289600>;
44	};
45
46	snd_rzg2l: sound {
47		compatible = "simple-audio-card";
48		simple-audio-card,format = "i2s";
49		simple-audio-card,bitclock-master = <&cpu_dai>;
50		simple-audio-card,frame-master = <&cpu_dai>;
51		simple-audio-card,mclk-fs = <256>;
52
53		simple-audio-card,widgets = "Microphone", "Microphone Jack";
54		simple-audio-card,routing =
55			    "L2", "Mic Bias",
56			    "R2", "Mic Bias",
57			    "Mic Bias", "Microphone Jack";
58
59		cpu_dai: simple-audio-card,cpu {
60			sound-dai = <&ssi0>;
61		};
62
63		codec_dai: simple-audio-card,codec {
64			clocks = <&audio_mclock>;
65			sound-dai = <&wm8978>;
66		};
67	};
68
69	usb0_vbus_otg: regulator-usb0-vbus-otg {
70		compatible = "regulator-fixed";
71
72		regulator-name = "USB0_VBUS_OTG";
73		regulator-min-microvolt = <5000000>;
74		regulator-max-microvolt = <5000000>;
75	};
76
77	vccq_sdhi1: regulator-vccq-sdhi1 {
78		compatible = "regulator-gpio";
79		regulator-name = "SDHI1 VccQ";
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <3300000>;
82		gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
83		gpios-states = <1>;
84		states = <3300000 1>, <1800000 0>;
85	};
86};
87
88&audio_clk1{
89	clock-frequency = <11289600>;
90};
91
92&audio_clk2{
93	clock-frequency = <12288000>;
94};
95
96&canfd {
97	pinctrl-0 = <&can0_pins &can1_pins>;
98	pinctrl-names = "default";
99	status = "okay";
100
101	channel0 {
102		status = "okay";
103	};
104
105	channel1 {
106		status = "okay";
107	};
108};
109
110&ehci0 {
111	dr_mode = "otg";
112	status = "okay";
113};
114
115&ehci1 {
116	status = "okay";
117};
118
119&hsusb {
120	dr_mode = "otg";
121	status = "okay";
122};
123
124&i2c0 {
125	pinctrl-0 = <&i2c0_pins>;
126	pinctrl-names = "default";
127
128	status = "okay";
129};
130
131&i2c1 {
132	pinctrl-0 = <&i2c1_pins>;
133	pinctrl-names = "default";
134
135	status = "okay";
136};
137
138&i2c3 {
139	pinctrl-0 = <&i2c3_pins>;
140	pinctrl-names = "default";
141	clock-frequency = <400000>;
142
143	status = "okay";
144
145	wm8978: codec@1a {
146		compatible = "wlf,wm8978";
147		#sound-dai-cells = <0>;
148		reg = <0x1a>;
149	};
150};
151
152&ohci0 {
153	dr_mode = "otg";
154	status = "okay";
155};
156
157&ohci1 {
158	status = "okay";
159};
160
161&phyrst {
162	status = "okay";
163};
164
165&scif0 {
166	pinctrl-0 = <&scif0_pins>;
167	pinctrl-names = "default";
168	status = "okay";
169};
170
171/*
172 * To enable SCIF2 (SER0) on PMOD1 (CN7)
173 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
174 * SW2 should be at position 2->3 so that SER0_TX line is activated
175 * SW3 should be at position 2->3 so that SER0_RX line is activated
176 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
177 */
178#if PMOD1_SER0
179&scif2 {
180	pinctrl-0 = <&scif2_pins>;
181	pinctrl-names = "default";
182
183	uart-has-rtscts;
184	status = "okay";
185};
186#endif
187
188&sdhi1 {
189	pinctrl-0 = <&sdhi1_pins>;
190	pinctrl-1 = <&sdhi1_pins_uhs>;
191	pinctrl-names = "default", "state_uhs";
192
193	vmmc-supply = <&reg_3p3v>;
194	vqmmc-supply = <&vccq_sdhi1>;
195	bus-width = <4>;
196	sd-uhs-sdr50;
197	sd-uhs-sdr104;
198	status = "okay";
199};
200
201&spi1 {
202	pinctrl-0 = <&spi1_pins>;
203	pinctrl-names = "default";
204
205	status = "okay";
206};
207
208&ssi0 {
209	pinctrl-0 = <&ssi0_pins>;
210	pinctrl-names = "default";
211
212	status = "okay";
213};
214
215&usb2_phy0 {
216	pinctrl-0 = <&usb0_pins>;
217	pinctrl-names = "default";
218
219	vbus-supply = <&usb0_vbus_otg>;
220	status = "okay";
221};
222
223&usb2_phy1 {
224	pinctrl-0 = <&usb1_pins>;
225	pinctrl-names = "default";
226
227	status = "okay";
228};
229