155c68261SLad Prabhakar// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
255c68261SLad Prabhakar/*
355c68261SLad Prabhakar * Device Tree Source for the RZ/G2L SMARC SOM common parts
455c68261SLad Prabhakar *
555c68261SLad Prabhakar * Copyright (C) 2021 Renesas Electronics Corp.
655c68261SLad Prabhakar */
755c68261SLad Prabhakar
8*03f7d78eSLad Prabhakar#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
9*03f7d78eSLad Prabhakar
1055c68261SLad Prabhakar/ {
1155c68261SLad Prabhakar	memory@48000000 {
1255c68261SLad Prabhakar		device_type = "memory";
1355c68261SLad Prabhakar		/* first 128MB is reserved for secure area. */
1455c68261SLad Prabhakar		reg = <0x0 0x48000000 0x0 0x78000000>;
1555c68261SLad Prabhakar	};
1655c68261SLad Prabhakar};
1755c68261SLad Prabhakar
18*03f7d78eSLad Prabhakar&adc {
19*03f7d78eSLad Prabhakar	pinctrl-0 = <&adc_pins>;
20*03f7d78eSLad Prabhakar	pinctrl-names = "default";
21*03f7d78eSLad Prabhakar	status = "okay";
22*03f7d78eSLad Prabhakar
23*03f7d78eSLad Prabhakar	/delete-node/ channel@6;
24*03f7d78eSLad Prabhakar	/delete-node/ channel@7;
25*03f7d78eSLad Prabhakar};
26*03f7d78eSLad Prabhakar
2755c68261SLad Prabhakar&extal_clk {
2855c68261SLad Prabhakar	clock-frequency = <24000000>;
2955c68261SLad Prabhakar};
30*03f7d78eSLad Prabhakar
31*03f7d78eSLad Prabhakar&pinctrl {
32*03f7d78eSLad Prabhakar	adc_pins: adc {
33*03f7d78eSLad Prabhakar		pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
34*03f7d78eSLad Prabhakar	};
35*03f7d78eSLad Prabhakar};
36