1e4d755cfSYoshihiro Shimoda// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2e4d755cfSYoshihiro Shimoda/*
3e4d755cfSYoshihiro Shimoda * Device Tree Source for the White Hawk CPU board
4e4d755cfSYoshihiro Shimoda *
5e4d755cfSYoshihiro Shimoda * Copyright (C) 2022 Renesas Electronics Corp.
6e4d755cfSYoshihiro Shimoda */
7e4d755cfSYoshihiro Shimoda
8e4d755cfSYoshihiro Shimoda#include "r8a779g0.dtsi"
9e4d755cfSYoshihiro Shimoda
10e4d755cfSYoshihiro Shimoda/ {
11e4d755cfSYoshihiro Shimoda	model = "Renesas White Hawk CPU board";
12e4d755cfSYoshihiro Shimoda	compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
13e4d755cfSYoshihiro Shimoda
14e4d755cfSYoshihiro Shimoda	memory@48000000 {
15e4d755cfSYoshihiro Shimoda		device_type = "memory";
16e4d755cfSYoshihiro Shimoda		/* first 128MB is reserved for secure area. */
17e4d755cfSYoshihiro Shimoda		reg = <0x0 0x48000000 0x0 0x78000000>;
18e4d755cfSYoshihiro Shimoda	};
19e4d755cfSYoshihiro Shimoda
20e4d755cfSYoshihiro Shimoda	memory@480000000 {
21e4d755cfSYoshihiro Shimoda		device_type = "memory";
22e4d755cfSYoshihiro Shimoda		reg = <0x4 0x80000000 0x0 0x80000000>;
23e4d755cfSYoshihiro Shimoda	};
24e4d755cfSYoshihiro Shimoda
25e4d755cfSYoshihiro Shimoda	memory@600000000 {
26e4d755cfSYoshihiro Shimoda		device_type = "memory";
27e4d755cfSYoshihiro Shimoda		reg = <0x6 0x00000000 0x1 0x00000000>;
28e4d755cfSYoshihiro Shimoda	};
29e4d755cfSYoshihiro Shimoda};
30e4d755cfSYoshihiro Shimoda
31e4d755cfSYoshihiro Shimoda&extal_clk {
32e4d755cfSYoshihiro Shimoda	clock-frequency = <16666666>;
33e4d755cfSYoshihiro Shimoda};
34e4d755cfSYoshihiro Shimoda
35e4d755cfSYoshihiro Shimoda&extalr_clk {
36e4d755cfSYoshihiro Shimoda	clock-frequency = <32768>;
37e4d755cfSYoshihiro Shimoda};
38e4d755cfSYoshihiro Shimoda
39e4d755cfSYoshihiro Shimoda&hscif0 {
40e4d755cfSYoshihiro Shimoda	status = "okay";
41e4d755cfSYoshihiro Shimoda};
42e4d755cfSYoshihiro Shimoda
43*77643815SGeert Uytterhoeven&i2c0 {
44*77643815SGeert Uytterhoeven	pinctrl-0 = <&i2c0_pins>;
45*77643815SGeert Uytterhoeven	pinctrl-names = "default";
46*77643815SGeert Uytterhoeven
47*77643815SGeert Uytterhoeven	status = "okay";
48*77643815SGeert Uytterhoeven	clock-frequency = <400000>;
49*77643815SGeert Uytterhoeven
50*77643815SGeert Uytterhoeven	eeprom@50 {
51*77643815SGeert Uytterhoeven		compatible = "rohm,br24g01", "atmel,24c01";
52*77643815SGeert Uytterhoeven		label = "cpu-board";
53*77643815SGeert Uytterhoeven		reg = <0x50>;
54*77643815SGeert Uytterhoeven		pagesize = <8>;
55*77643815SGeert Uytterhoeven	};
56*77643815SGeert Uytterhoeven};
57*77643815SGeert Uytterhoeven
587a8d590dSGeert Uytterhoeven&pfc {
597a8d590dSGeert Uytterhoeven	pinctrl-0 = <&scif_clk_pins>;
607a8d590dSGeert Uytterhoeven	pinctrl-names = "default";
617a8d590dSGeert Uytterhoeven
627a8d590dSGeert Uytterhoeven	hscif0_pins: hscif0 {
637a8d590dSGeert Uytterhoeven		groups = "hscif0_data";
647a8d590dSGeert Uytterhoeven		function = "hscif0";
657a8d590dSGeert Uytterhoeven	};
667a8d590dSGeert Uytterhoeven
67*77643815SGeert Uytterhoeven	i2c0_pins: i2c0 {
68*77643815SGeert Uytterhoeven		groups = "i2c0";
69*77643815SGeert Uytterhoeven		function = "i2c0";
70*77643815SGeert Uytterhoeven	};
71*77643815SGeert Uytterhoeven
727a8d590dSGeert Uytterhoeven	scif_clk_pins: scif_clk {
737a8d590dSGeert Uytterhoeven		groups = "scif_clk";
747a8d590dSGeert Uytterhoeven		function = "scif_clk";
757a8d590dSGeert Uytterhoeven	};
767a8d590dSGeert Uytterhoeven};
777a8d590dSGeert Uytterhoeven
78e4d755cfSYoshihiro Shimoda&scif_clk {
79e4d755cfSYoshihiro Shimoda	clock-frequency = <24000000>;
80e4d755cfSYoshihiro Shimoda};
81495e36c3SGeert Uytterhoeven
82495e36c3SGeert Uytterhoeven&rwdt {
83495e36c3SGeert Uytterhoeven	timeout-sec = <60>;
84495e36c3SGeert Uytterhoeven	status = "okay";
85495e36c3SGeert Uytterhoeven};
86