1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the r8a77990 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	compatible = "renesas,r8a77990";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		/* 1 core only at this point */
21		a53_0: cpu@0 {
22			compatible = "arm,cortex-a53", "arm,armv8";
23			reg = <0x0>;
24			device_type = "cpu";
25			power-domains = <&sysc 5>;
26			next-level-cache = <&L2_CA53>;
27			enable-method = "psci";
28		};
29
30		L2_CA53: cache-controller@0 {
31			compatible = "cache";
32			reg = <0>;
33			power-domains = <&sysc 21>;
34			cache-unified;
35			cache-level = <2>;
36		};
37	};
38
39	extal_clk: extal {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		/* This value must be overridden by the board */
43		clock-frequency = <0>;
44	};
45
46	pmu_a53 {
47		compatible = "arm,cortex-a53-pmu";
48		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
49		interrupt-affinity = <&a53_0>;
50	};
51
52	psci {
53		compatible = "arm,psci-0.2";
54		method = "smc";
55	};
56
57	soc: soc {
58		compatible = "simple-bus";
59		interrupt-parent = <&gic>;
60		#address-cells = <2>;
61		#size-cells = <2>;
62		ranges;
63
64		cpg: clock-controller@e6150000 {
65			compatible = "renesas,r8a77990-cpg-mssr";
66			reg = <0 0xe6150000 0 0x1000>;
67			clocks = <&extal_clk>;
68			clock-names = "extal";
69			#clock-cells = <2>;
70			#power-domain-cells = <0>;
71			#reset-cells = <1>;
72		};
73
74		rst: reset-controller@e6160000 {
75			compatible = "renesas,r8a77990-rst";
76			reg = <0 0xe6160000 0 0x0200>;
77		};
78
79		sysc: system-controller@e6180000 {
80			compatible = "renesas,r8a77990-sysc";
81			reg = <0 0xe6180000 0 0x0400>;
82			#power-domain-cells = <1>;
83		};
84
85		scif2: serial@e6e88000 {
86			compatible = "renesas,scif-r8a77990",
87				     "renesas,rcar-gen3-scif", "renesas,scif";
88			reg = <0 0xe6e88000 0 64>;
89			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
90			clocks = <&cpg CPG_MOD 310>;
91			clock-names = "fck";
92			power-domains = <&sysc 32>;
93			resets = <&cpg 310>;
94			status = "disabled";
95		};
96
97		gic: interrupt-controller@f1010000 {
98			compatible = "arm,gic-400";
99			#interrupt-cells = <3>;
100			#address-cells = <0>;
101			interrupt-controller;
102			reg = <0x0 0xf1010000 0 0x1000>,
103			      <0x0 0xf1020000 0 0x20000>,
104			      <0x0 0xf1040000 0 0x20000>,
105			      <0x0 0xf1060000 0 0x20000>;
106			interrupts = <GIC_PPI 9
107					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
108			clocks = <&cpg CPG_MOD 408>;
109			clock-names = "clk";
110			power-domains = <&sysc 32>;
111			resets = <&cpg 408>;
112		};
113
114		prr: chipid@fff00044 {
115			compatible = "renesas,prr";
116			reg = <0 0xfff00044 0 4>;
117		};
118	};
119
120	timer {
121		compatible = "arm,armv8-timer";
122		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
123				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
124				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
125				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
126	};
127};
128