1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the r8a77990 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r8a77990"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 /* 1 core only at this point */ 21 a53_0: cpu@0 { 22 compatible = "arm,cortex-a53", "arm,armv8"; 23 reg = <0x0>; 24 device_type = "cpu"; 25 power-domains = <&sysc 5>; 26 next-level-cache = <&L2_CA53>; 27 enable-method = "psci"; 28 }; 29 30 L2_CA53: cache-controller-0 { 31 compatible = "cache"; 32 power-domains = <&sysc 21>; 33 cache-unified; 34 cache-level = <2>; 35 }; 36 }; 37 38 extal_clk: extal { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 pmu_a53 { 46 compatible = "arm,cortex-a53-pmu"; 47 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 48 interrupt-affinity = <&a53_0>; 49 }; 50 51 psci { 52 compatible = "arm,psci-1.0", "arm,psci-0.2"; 53 method = "smc"; 54 }; 55 56 soc: soc { 57 compatible = "simple-bus"; 58 interrupt-parent = <&gic>; 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges; 62 63 rwdt: watchdog@e6020000 { 64 compatible = "renesas,r8a77990-wdt", 65 "renesas,rcar-gen3-wdt"; 66 reg = <0 0xe6020000 0 0x0c>; 67 clocks = <&cpg CPG_MOD 402>; 68 power-domains = <&sysc 32>; 69 resets = <&cpg 402>; 70 status = "disabled"; 71 }; 72 73 gpio0: gpio@e6050000 { 74 compatible = "renesas,gpio-r8a77990", 75 "renesas,rcar-gen3-gpio"; 76 reg = <0 0xe6050000 0 0x50>; 77 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 78 #gpio-cells = <2>; 79 gpio-controller; 80 gpio-ranges = <&pfc 0 0 18>; 81 #interrupt-cells = <2>; 82 interrupt-controller; 83 clocks = <&cpg CPG_MOD 912>; 84 power-domains = <&sysc 32>; 85 resets = <&cpg 912>; 86 }; 87 88 gpio1: gpio@e6051000 { 89 compatible = "renesas,gpio-r8a77990", 90 "renesas,rcar-gen3-gpio"; 91 reg = <0 0xe6051000 0 0x50>; 92 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 93 #gpio-cells = <2>; 94 gpio-controller; 95 gpio-ranges = <&pfc 0 32 23>; 96 #interrupt-cells = <2>; 97 interrupt-controller; 98 clocks = <&cpg CPG_MOD 911>; 99 power-domains = <&sysc 32>; 100 resets = <&cpg 911>; 101 }; 102 103 gpio2: gpio@e6052000 { 104 compatible = "renesas,gpio-r8a77990", 105 "renesas,rcar-gen3-gpio"; 106 reg = <0 0xe6052000 0 0x50>; 107 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 108 #gpio-cells = <2>; 109 gpio-controller; 110 gpio-ranges = <&pfc 0 64 26>; 111 #interrupt-cells = <2>; 112 interrupt-controller; 113 clocks = <&cpg CPG_MOD 910>; 114 power-domains = <&sysc 32>; 115 resets = <&cpg 910>; 116 }; 117 118 gpio3: gpio@e6053000 { 119 compatible = "renesas,gpio-r8a77990", 120 "renesas,rcar-gen3-gpio"; 121 reg = <0 0xe6053000 0 0x50>; 122 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 123 #gpio-cells = <2>; 124 gpio-controller; 125 gpio-ranges = <&pfc 0 96 16>; 126 #interrupt-cells = <2>; 127 interrupt-controller; 128 clocks = <&cpg CPG_MOD 909>; 129 power-domains = <&sysc 32>; 130 resets = <&cpg 909>; 131 }; 132 133 gpio4: gpio@e6054000 { 134 compatible = "renesas,gpio-r8a77990", 135 "renesas,rcar-gen3-gpio"; 136 reg = <0 0xe6054000 0 0x50>; 137 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 138 #gpio-cells = <2>; 139 gpio-controller; 140 gpio-ranges = <&pfc 0 128 11>; 141 #interrupt-cells = <2>; 142 interrupt-controller; 143 clocks = <&cpg CPG_MOD 908>; 144 power-domains = <&sysc 32>; 145 resets = <&cpg 908>; 146 }; 147 148 gpio5: gpio@e6055000 { 149 compatible = "renesas,gpio-r8a77990", 150 "renesas,rcar-gen3-gpio"; 151 reg = <0 0xe6055000 0 0x50>; 152 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 153 #gpio-cells = <2>; 154 gpio-controller; 155 gpio-ranges = <&pfc 0 160 20>; 156 #interrupt-cells = <2>; 157 interrupt-controller; 158 clocks = <&cpg CPG_MOD 907>; 159 power-domains = <&sysc 32>; 160 resets = <&cpg 907>; 161 }; 162 163 gpio6: gpio@e6055400 { 164 compatible = "renesas,gpio-r8a77990", 165 "renesas,rcar-gen3-gpio"; 166 reg = <0 0xe6055400 0 0x50>; 167 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 192 18>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 906>; 174 power-domains = <&sysc 32>; 175 resets = <&cpg 906>; 176 }; 177 178 pfc: pin-controller@e6060000 { 179 compatible = "renesas,pfc-r8a77990"; 180 reg = <0 0xe6060000 0 0x508>; 181 }; 182 183 cpg: clock-controller@e6150000 { 184 compatible = "renesas,r8a77990-cpg-mssr"; 185 reg = <0 0xe6150000 0 0x1000>; 186 clocks = <&extal_clk>; 187 clock-names = "extal"; 188 #clock-cells = <2>; 189 #power-domain-cells = <0>; 190 #reset-cells = <1>; 191 }; 192 193 rst: reset-controller@e6160000 { 194 compatible = "renesas,r8a77990-rst"; 195 reg = <0 0xe6160000 0 0x0200>; 196 }; 197 198 sysc: system-controller@e6180000 { 199 compatible = "renesas,r8a77990-sysc"; 200 reg = <0 0xe6180000 0 0x0400>; 201 #power-domain-cells = <1>; 202 }; 203 204 avb: ethernet@e6800000 { 205 compatible = "renesas,etheravb-r8a77990", 206 "renesas,etheravb-rcar-gen3"; 207 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 208 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 233 interrupt-names = "ch0", "ch1", "ch2", "ch3", 234 "ch4", "ch5", "ch6", "ch7", 235 "ch8", "ch9", "ch10", "ch11", 236 "ch12", "ch13", "ch14", "ch15", 237 "ch16", "ch17", "ch18", "ch19", 238 "ch20", "ch21", "ch22", "ch23", 239 "ch24"; 240 clocks = <&cpg CPG_MOD 812>; 241 power-domains = <&sysc 32>; 242 resets = <&cpg 812>; 243 phy-mode = "rgmii"; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 status = "disabled"; 247 }; 248 249 scif2: serial@e6e88000 { 250 compatible = "renesas,scif-r8a77990", 251 "renesas,rcar-gen3-scif", "renesas,scif"; 252 reg = <0 0xe6e88000 0 64>; 253 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cpg CPG_MOD 310>; 255 clock-names = "fck"; 256 power-domains = <&sysc 32>; 257 resets = <&cpg 310>; 258 status = "disabled"; 259 }; 260 261 gic: interrupt-controller@f1010000 { 262 compatible = "arm,gic-400"; 263 #interrupt-cells = <3>; 264 #address-cells = <0>; 265 interrupt-controller; 266 reg = <0x0 0xf1010000 0 0x1000>, 267 <0x0 0xf1020000 0 0x20000>, 268 <0x0 0xf1040000 0 0x20000>, 269 <0x0 0xf1060000 0 0x20000>; 270 interrupts = <GIC_PPI 9 271 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 272 clocks = <&cpg CPG_MOD 408>; 273 clock-names = "clk"; 274 power-domains = <&sysc 32>; 275 resets = <&cpg 408>; 276 }; 277 278 prr: chipid@fff00044 { 279 compatible = "renesas,prr"; 280 reg = <0 0xfff00044 0 4>; 281 }; 282 }; 283 284 timer { 285 compatible = "arm,armv8-timer"; 286 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 287 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 288 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 289 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 290 }; 291}; 292