1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Device Tree Source for the r8a77990 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	compatible = "renesas,r8a77990";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		/* 1 core only at this point */
21		a53_0: cpu@0 {
22			compatible = "arm,cortex-a53", "arm,armv8";
23			reg = <0x0>;
24			device_type = "cpu";
25			power-domains = <&sysc 5>;
26			next-level-cache = <&L2_CA53>;
27			enable-method = "psci";
28		};
29
30		L2_CA53: cache-controller-0 {
31			compatible = "cache";
32			power-domains = <&sysc 21>;
33			cache-unified;
34			cache-level = <2>;
35		};
36	};
37
38	extal_clk: extal {
39		compatible = "fixed-clock";
40		#clock-cells = <0>;
41		/* This value must be overridden by the board */
42		clock-frequency = <0>;
43	};
44
45	pmu_a53 {
46		compatible = "arm,cortex-a53-pmu";
47		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
48		interrupt-affinity = <&a53_0>;
49	};
50
51	psci {
52		compatible = "arm,psci-1.0", "arm,psci-0.2";
53		method = "smc";
54	};
55
56	soc: soc {
57		compatible = "simple-bus";
58		interrupt-parent = <&gic>;
59		#address-cells = <2>;
60		#size-cells = <2>;
61		ranges;
62
63		pfc: pin-controller@e6060000 {
64			compatible = "renesas,pfc-r8a77990";
65			reg = <0 0xe6060000 0 0x508>;
66		};
67
68		cpg: clock-controller@e6150000 {
69			compatible = "renesas,r8a77990-cpg-mssr";
70			reg = <0 0xe6150000 0 0x1000>;
71			clocks = <&extal_clk>;
72			clock-names = "extal";
73			#clock-cells = <2>;
74			#power-domain-cells = <0>;
75			#reset-cells = <1>;
76		};
77
78		rst: reset-controller@e6160000 {
79			compatible = "renesas,r8a77990-rst";
80			reg = <0 0xe6160000 0 0x0200>;
81		};
82
83		sysc: system-controller@e6180000 {
84			compatible = "renesas,r8a77990-sysc";
85			reg = <0 0xe6180000 0 0x0400>;
86			#power-domain-cells = <1>;
87		};
88
89		scif2: serial@e6e88000 {
90			compatible = "renesas,scif-r8a77990",
91				     "renesas,rcar-gen3-scif", "renesas,scif";
92			reg = <0 0xe6e88000 0 64>;
93			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
94			clocks = <&cpg CPG_MOD 310>;
95			clock-names = "fck";
96			power-domains = <&sysc 32>;
97			resets = <&cpg 310>;
98			status = "disabled";
99		};
100
101		gic: interrupt-controller@f1010000 {
102			compatible = "arm,gic-400";
103			#interrupt-cells = <3>;
104			#address-cells = <0>;
105			interrupt-controller;
106			reg = <0x0 0xf1010000 0 0x1000>,
107			      <0x0 0xf1020000 0 0x20000>,
108			      <0x0 0xf1040000 0 0x20000>,
109			      <0x0 0xf1060000 0 0x20000>;
110			interrupts = <GIC_PPI 9
111					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
112			clocks = <&cpg CPG_MOD 408>;
113			clock-names = "clk";
114			power-domains = <&sysc 32>;
115			resets = <&cpg 408>;
116		};
117
118		prr: chipid@fff00044 {
119			compatible = "renesas,prr";
120			reg = <0 0xfff00044 0 4>;
121		};
122	};
123
124	timer {
125		compatible = "arm,armv8-timer";
126		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
127				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
128				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
129				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
130	};
131};
132