1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77990-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77990-sysc.h> 11 12/ { 13 compatible = "renesas,r8a77990"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 i2c6 = &i2c6; 25 i2c7 = &i2c7; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 a53_0: cpu@0 { 33 compatible = "arm,cortex-a53", "arm,armv8"; 34 reg = <0>; 35 device_type = "cpu"; 36 power-domains = <&sysc R8A77990_PD_CA53_CPU0>; 37 next-level-cache = <&L2_CA53>; 38 enable-method = "psci"; 39 }; 40 41 a53_1: cpu@1 { 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <1>; 44 device_type = "cpu"; 45 power-domains = <&sysc R8A77990_PD_CA53_CPU1>; 46 next-level-cache = <&L2_CA53>; 47 enable-method = "psci"; 48 }; 49 50 L2_CA53: cache-controller-0 { 51 compatible = "cache"; 52 power-domains = <&sysc R8A77990_PD_CA53_SCU>; 53 cache-unified; 54 cache-level = <2>; 55 }; 56 }; 57 58 extal_clk: extal { 59 compatible = "fixed-clock"; 60 #clock-cells = <0>; 61 /* This value must be overridden by the board */ 62 clock-frequency = <0>; 63 }; 64 65 pmu_a53 { 66 compatible = "arm,cortex-a53-pmu"; 67 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 68 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&a53_0>, <&a53_1>; 70 }; 71 72 psci { 73 compatible = "arm,psci-1.0", "arm,psci-0.2"; 74 method = "smc"; 75 }; 76 77 /* External SCIF clock - to be overridden by boards that provide it */ 78 scif_clk: scif { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <0>; 82 }; 83 84 soc: soc { 85 compatible = "simple-bus"; 86 interrupt-parent = <&gic>; 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges; 90 91 rwdt: watchdog@e6020000 { 92 compatible = "renesas,r8a77990-wdt", 93 "renesas,rcar-gen3-wdt"; 94 reg = <0 0xe6020000 0 0x0c>; 95 clocks = <&cpg CPG_MOD 402>; 96 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 97 resets = <&cpg 402>; 98 status = "disabled"; 99 }; 100 101 gpio0: gpio@e6050000 { 102 compatible = "renesas,gpio-r8a77990", 103 "renesas,rcar-gen3-gpio"; 104 reg = <0 0xe6050000 0 0x50>; 105 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 106 #gpio-cells = <2>; 107 gpio-controller; 108 gpio-ranges = <&pfc 0 0 18>; 109 #interrupt-cells = <2>; 110 interrupt-controller; 111 clocks = <&cpg CPG_MOD 912>; 112 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 113 resets = <&cpg 912>; 114 }; 115 116 gpio1: gpio@e6051000 { 117 compatible = "renesas,gpio-r8a77990", 118 "renesas,rcar-gen3-gpio"; 119 reg = <0 0xe6051000 0 0x50>; 120 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 121 #gpio-cells = <2>; 122 gpio-controller; 123 gpio-ranges = <&pfc 0 32 23>; 124 #interrupt-cells = <2>; 125 interrupt-controller; 126 clocks = <&cpg CPG_MOD 911>; 127 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 128 resets = <&cpg 911>; 129 }; 130 131 gpio2: gpio@e6052000 { 132 compatible = "renesas,gpio-r8a77990", 133 "renesas,rcar-gen3-gpio"; 134 reg = <0 0xe6052000 0 0x50>; 135 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 136 #gpio-cells = <2>; 137 gpio-controller; 138 gpio-ranges = <&pfc 0 64 26>; 139 #interrupt-cells = <2>; 140 interrupt-controller; 141 clocks = <&cpg CPG_MOD 910>; 142 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 143 resets = <&cpg 910>; 144 }; 145 146 gpio3: gpio@e6053000 { 147 compatible = "renesas,gpio-r8a77990", 148 "renesas,rcar-gen3-gpio"; 149 reg = <0 0xe6053000 0 0x50>; 150 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 151 #gpio-cells = <2>; 152 gpio-controller; 153 gpio-ranges = <&pfc 0 96 16>; 154 #interrupt-cells = <2>; 155 interrupt-controller; 156 clocks = <&cpg CPG_MOD 909>; 157 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 158 resets = <&cpg 909>; 159 }; 160 161 gpio4: gpio@e6054000 { 162 compatible = "renesas,gpio-r8a77990", 163 "renesas,rcar-gen3-gpio"; 164 reg = <0 0xe6054000 0 0x50>; 165 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 166 #gpio-cells = <2>; 167 gpio-controller; 168 gpio-ranges = <&pfc 0 128 11>; 169 #interrupt-cells = <2>; 170 interrupt-controller; 171 clocks = <&cpg CPG_MOD 908>; 172 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 173 resets = <&cpg 908>; 174 }; 175 176 gpio5: gpio@e6055000 { 177 compatible = "renesas,gpio-r8a77990", 178 "renesas,rcar-gen3-gpio"; 179 reg = <0 0xe6055000 0 0x50>; 180 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 181 #gpio-cells = <2>; 182 gpio-controller; 183 gpio-ranges = <&pfc 0 160 20>; 184 #interrupt-cells = <2>; 185 interrupt-controller; 186 clocks = <&cpg CPG_MOD 907>; 187 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 188 resets = <&cpg 907>; 189 }; 190 191 gpio6: gpio@e6055400 { 192 compatible = "renesas,gpio-r8a77990", 193 "renesas,rcar-gen3-gpio"; 194 reg = <0 0xe6055400 0 0x50>; 195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 196 #gpio-cells = <2>; 197 gpio-controller; 198 gpio-ranges = <&pfc 0 192 18>; 199 #interrupt-cells = <2>; 200 interrupt-controller; 201 clocks = <&cpg CPG_MOD 906>; 202 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 203 resets = <&cpg 906>; 204 }; 205 206 i2c0: i2c@e6500000 { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 compatible = "renesas,i2c-r8a77990", 210 "renesas,rcar-gen3-i2c"; 211 reg = <0 0xe6500000 0 0x40>; 212 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cpg CPG_MOD 931>; 214 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 215 resets = <&cpg 931>; 216 i2c-scl-internal-delay-ns = <110>; 217 status = "disabled"; 218 }; 219 220 i2c1: i2c@e6508000 { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 compatible = "renesas,i2c-r8a77990", 224 "renesas,rcar-gen3-i2c"; 225 reg = <0 0xe6508000 0 0x40>; 226 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cpg CPG_MOD 930>; 228 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 229 resets = <&cpg 930>; 230 i2c-scl-internal-delay-ns = <6>; 231 status = "disabled"; 232 }; 233 234 i2c2: i2c@e6510000 { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 compatible = "renesas,i2c-r8a77990", 238 "renesas,rcar-gen3-i2c"; 239 reg = <0 0xe6510000 0 0x40>; 240 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&cpg CPG_MOD 929>; 242 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 243 resets = <&cpg 929>; 244 i2c-scl-internal-delay-ns = <6>; 245 status = "disabled"; 246 }; 247 248 i2c3: i2c@e66d0000 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "renesas,i2c-r8a77990", 252 "renesas,rcar-gen3-i2c"; 253 reg = <0 0xe66d0000 0 0x40>; 254 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&cpg CPG_MOD 928>; 256 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 257 resets = <&cpg 928>; 258 i2c-scl-internal-delay-ns = <110>; 259 status = "disabled"; 260 }; 261 262 i2c4: i2c@e66d8000 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 compatible = "renesas,i2c-r8a77990", 266 "renesas,rcar-gen3-i2c"; 267 reg = <0 0xe66d8000 0 0x40>; 268 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&cpg CPG_MOD 927>; 270 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 271 resets = <&cpg 927>; 272 i2c-scl-internal-delay-ns = <6>; 273 status = "disabled"; 274 }; 275 276 i2c5: i2c@e66e0000 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "renesas,i2c-r8a77990", 280 "renesas,rcar-gen3-i2c"; 281 reg = <0 0xe66e0000 0 0x40>; 282 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&cpg CPG_MOD 919>; 284 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 285 resets = <&cpg 919>; 286 i2c-scl-internal-delay-ns = <6>; 287 status = "disabled"; 288 }; 289 290 i2c6: i2c@e66e8000 { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 compatible = "renesas,i2c-r8a77990", 294 "renesas,rcar-gen3-i2c"; 295 reg = <0 0xe66e8000 0 0x40>; 296 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&cpg CPG_MOD 918>; 298 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 299 resets = <&cpg 918>; 300 i2c-scl-internal-delay-ns = <6>; 301 status = "disabled"; 302 }; 303 304 i2c7: i2c@e6690000 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "renesas,i2c-r8a77990", 308 "renesas,rcar-gen3-i2c"; 309 reg = <0 0xe6690000 0 0x40>; 310 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cpg CPG_MOD 1003>; 312 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 313 resets = <&cpg 1003>; 314 i2c-scl-internal-delay-ns = <6>; 315 status = "disabled"; 316 }; 317 318 pfc: pin-controller@e6060000 { 319 compatible = "renesas,pfc-r8a77990"; 320 reg = <0 0xe6060000 0 0x508>; 321 }; 322 323 cpg: clock-controller@e6150000 { 324 compatible = "renesas,r8a77990-cpg-mssr"; 325 reg = <0 0xe6150000 0 0x1000>; 326 clocks = <&extal_clk>; 327 clock-names = "extal"; 328 #clock-cells = <2>; 329 #power-domain-cells = <0>; 330 #reset-cells = <1>; 331 }; 332 333 rst: reset-controller@e6160000 { 334 compatible = "renesas,r8a77990-rst"; 335 reg = <0 0xe6160000 0 0x0200>; 336 }; 337 338 sysc: system-controller@e6180000 { 339 compatible = "renesas,r8a77990-sysc"; 340 reg = <0 0xe6180000 0 0x0400>; 341 #power-domain-cells = <1>; 342 }; 343 344 dmac0: dma-controller@e6700000 { 345 compatible = "renesas,dmac-r8a77990", 346 "renesas,rcar-dmac"; 347 reg = <0 0xe6700000 0 0x10000>; 348 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 349 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 350 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 351 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 352 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 353 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 354 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 355 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 356 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 357 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 358 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 359 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 360 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 361 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 362 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 363 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 365 interrupt-names = "error", 366 "ch0", "ch1", "ch2", "ch3", 367 "ch4", "ch5", "ch6", "ch7", 368 "ch8", "ch9", "ch10", "ch11", 369 "ch12", "ch13", "ch14", "ch15"; 370 clocks = <&cpg CPG_MOD 219>; 371 clock-names = "fck"; 372 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 373 resets = <&cpg 219>; 374 #dma-cells = <1>; 375 dma-channels = <16>; 376 }; 377 378 dmac1: dma-controller@e7300000 { 379 compatible = "renesas,dmac-r8a77990", 380 "renesas,rcar-dmac"; 381 reg = <0 0xe7300000 0 0x10000>; 382 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 383 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 384 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 385 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 386 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 387 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 388 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 389 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 390 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 391 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 392 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 393 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 394 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 395 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 396 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 397 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 398 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 399 interrupt-names = "error", 400 "ch0", "ch1", "ch2", "ch3", 401 "ch4", "ch5", "ch6", "ch7", 402 "ch8", "ch9", "ch10", "ch11", 403 "ch12", "ch13", "ch14", "ch15"; 404 clocks = <&cpg CPG_MOD 218>; 405 clock-names = "fck"; 406 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 407 resets = <&cpg 218>; 408 #dma-cells = <1>; 409 dma-channels = <16>; 410 }; 411 412 dmac2: dma-controller@e7310000 { 413 compatible = "renesas,dmac-r8a77990", 414 "renesas,rcar-dmac"; 415 reg = <0 0xe7310000 0 0x10000>; 416 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 417 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 418 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 419 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 420 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 421 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 422 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 423 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 424 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 425 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 426 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 427 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 428 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 429 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 430 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 431 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 432 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 433 interrupt-names = "error", 434 "ch0", "ch1", "ch2", "ch3", 435 "ch4", "ch5", "ch6", "ch7", 436 "ch8", "ch9", "ch10", "ch11", 437 "ch12", "ch13", "ch14", "ch15"; 438 clocks = <&cpg CPG_MOD 217>; 439 clock-names = "fck"; 440 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 441 resets = <&cpg 217>; 442 #dma-cells = <1>; 443 dma-channels = <16>; 444 }; 445 446 ipmmu_ds0: mmu@e6740000 { 447 compatible = "renesas,ipmmu-r8a77990"; 448 reg = <0 0xe6740000 0 0x1000>; 449 renesas,ipmmu-main = <&ipmmu_mm 0>; 450 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 451 #iommu-cells = <1>; 452 }; 453 454 ipmmu_ds1: mmu@e7740000 { 455 compatible = "renesas,ipmmu-r8a77990"; 456 reg = <0 0xe7740000 0 0x1000>; 457 renesas,ipmmu-main = <&ipmmu_mm 1>; 458 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 459 #iommu-cells = <1>; 460 }; 461 462 ipmmu_hc: mmu@e6570000 { 463 compatible = "renesas,ipmmu-r8a77990"; 464 reg = <0 0xe6570000 0 0x1000>; 465 renesas,ipmmu-main = <&ipmmu_mm 2>; 466 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 467 #iommu-cells = <1>; 468 }; 469 470 ipmmu_mm: mmu@e67b0000 { 471 compatible = "renesas,ipmmu-r8a77990"; 472 reg = <0 0xe67b0000 0 0x1000>; 473 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 475 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 476 #iommu-cells = <1>; 477 }; 478 479 ipmmu_mp: mmu@ec670000 { 480 compatible = "renesas,ipmmu-r8a77990"; 481 reg = <0 0xec670000 0 0x1000>; 482 renesas,ipmmu-main = <&ipmmu_mm 4>; 483 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 484 #iommu-cells = <1>; 485 }; 486 487 ipmmu_pv0: mmu@fd800000 { 488 compatible = "renesas,ipmmu-r8a77990"; 489 reg = <0 0xfd800000 0 0x1000>; 490 renesas,ipmmu-main = <&ipmmu_mm 6>; 491 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 492 #iommu-cells = <1>; 493 }; 494 495 ipmmu_rt: mmu@ffc80000 { 496 compatible = "renesas,ipmmu-r8a77990"; 497 reg = <0 0xffc80000 0 0x1000>; 498 renesas,ipmmu-main = <&ipmmu_mm 10>; 499 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 500 #iommu-cells = <1>; 501 }; 502 503 ipmmu_vc0: mmu@fe6b0000 { 504 compatible = "renesas,ipmmu-r8a77990"; 505 reg = <0 0xfe6b0000 0 0x1000>; 506 renesas,ipmmu-main = <&ipmmu_mm 12>; 507 power-domains = <&sysc R8A77990_PD_A3VC>; 508 #iommu-cells = <1>; 509 }; 510 511 ipmmu_vi0: mmu@febd0000 { 512 compatible = "renesas,ipmmu-r8a77990"; 513 reg = <0 0xfebd0000 0 0x1000>; 514 renesas,ipmmu-main = <&ipmmu_mm 14>; 515 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 516 #iommu-cells = <1>; 517 }; 518 519 ipmmu_vp0: mmu@fe990000 { 520 compatible = "renesas,ipmmu-r8a77990"; 521 reg = <0 0xfe990000 0 0x1000>; 522 renesas,ipmmu-main = <&ipmmu_mm 16>; 523 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 524 #iommu-cells = <1>; 525 }; 526 527 avb: ethernet@e6800000 { 528 compatible = "renesas,etheravb-r8a77990", 529 "renesas,etheravb-rcar-gen3"; 530 reg = <0 0xe6800000 0 0x800>; 531 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 556 interrupt-names = "ch0", "ch1", "ch2", "ch3", 557 "ch4", "ch5", "ch6", "ch7", 558 "ch8", "ch9", "ch10", "ch11", 559 "ch12", "ch13", "ch14", "ch15", 560 "ch16", "ch17", "ch18", "ch19", 561 "ch20", "ch21", "ch22", "ch23", 562 "ch24"; 563 clocks = <&cpg CPG_MOD 812>; 564 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 565 resets = <&cpg 812>; 566 phy-mode = "rgmii"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 pwm0: pwm@e6e30000 { 573 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 574 reg = <0 0xe6e30000 0 0x8>; 575 clocks = <&cpg CPG_MOD 523>; 576 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 577 resets = <&cpg 523>; 578 #pwm-cells = <2>; 579 status = "disabled"; 580 }; 581 582 pwm1: pwm@e6e31000 { 583 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 584 reg = <0 0xe6e31000 0 0x8>; 585 clocks = <&cpg CPG_MOD 523>; 586 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 587 resets = <&cpg 523>; 588 #pwm-cells = <2>; 589 status = "disabled"; 590 }; 591 592 pwm2: pwm@e6e32000 { 593 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 594 reg = <0 0xe6e32000 0 0x8>; 595 clocks = <&cpg CPG_MOD 523>; 596 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 597 resets = <&cpg 523>; 598 #pwm-cells = <2>; 599 status = "disabled"; 600 }; 601 602 pwm3: pwm@e6e33000 { 603 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 604 reg = <0 0xe6e33000 0 0x8>; 605 clocks = <&cpg CPG_MOD 523>; 606 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 607 resets = <&cpg 523>; 608 #pwm-cells = <2>; 609 status = "disabled"; 610 }; 611 612 pwm4: pwm@e6e34000 { 613 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 614 reg = <0 0xe6e34000 0 0x8>; 615 clocks = <&cpg CPG_MOD 523>; 616 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 617 resets = <&cpg 523>; 618 #pwm-cells = <2>; 619 status = "disabled"; 620 }; 621 622 pwm5: pwm@e6e35000 { 623 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 624 reg = <0 0xe6e35000 0 0x8>; 625 clocks = <&cpg CPG_MOD 523>; 626 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 627 resets = <&cpg 523>; 628 #pwm-cells = <2>; 629 status = "disabled"; 630 }; 631 632 pwm6: pwm@e6e36000 { 633 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; 634 reg = <0 0xe6e36000 0 0x8>; 635 clocks = <&cpg CPG_MOD 523>; 636 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 637 resets = <&cpg 523>; 638 #pwm-cells = <2>; 639 status = "disabled"; 640 }; 641 642 scif2: serial@e6e88000 { 643 compatible = "renesas,scif-r8a77990", 644 "renesas,rcar-gen3-scif", "renesas,scif"; 645 reg = <0 0xe6e88000 0 64>; 646 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&cpg CPG_MOD 310>, 648 <&cpg CPG_CORE R8A77990_CLK_S3D1C>, 649 <&scif_clk>; 650 clock-names = "fck", "brg_int", "scif_clk"; 651 652 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 653 resets = <&cpg 310>; 654 status = "disabled"; 655 }; 656 657 msiof0: spi@e6e90000 { 658 compatible = "renesas,msiof-r8a77990", 659 "renesas,rcar-gen3-msiof"; 660 reg = <0 0xe6e90000 0 0x0064>; 661 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cpg CPG_MOD 211>; 663 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 664 resets = <&cpg 211>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 status = "disabled"; 668 }; 669 670 msiof1: spi@e6ea0000 { 671 compatible = "renesas,msiof-r8a77990", 672 "renesas,rcar-gen3-msiof"; 673 reg = <0 0xe6ea0000 0 0x0064>; 674 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&cpg CPG_MOD 210>; 676 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 677 resets = <&cpg 210>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 status = "disabled"; 681 }; 682 683 msiof2: spi@e6c00000 { 684 compatible = "renesas,msiof-r8a77990", 685 "renesas,rcar-gen3-msiof"; 686 reg = <0 0xe6c00000 0 0x0064>; 687 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cpg CPG_MOD 209>; 689 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 690 resets = <&cpg 209>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 status = "disabled"; 694 }; 695 696 msiof3: spi@e6c10000 { 697 compatible = "renesas,msiof-r8a77990", 698 "renesas,rcar-gen3-msiof"; 699 reg = <0 0xe6c10000 0 0x0064>; 700 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cpg CPG_MOD 208>; 702 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 703 resets = <&cpg 208>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 status = "disabled"; 707 }; 708 709 vin4: video@e6ef4000 { 710 compatible = "renesas,vin-r8a77990"; 711 reg = <0 0xe6ef4000 0 0x1000>; 712 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&cpg CPG_MOD 807>; 714 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 715 resets = <&cpg 807>; 716 renesas,id = <4>; 717 status = "disabled"; 718 719 ports { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 723 port@1 { 724 reg = <1>; 725 726 vin4csi40: endpoint { 727 remote-endpoint= <&csi40vin4>; 728 }; 729 }; 730 }; 731 }; 732 733 vin5: video@e6ef5000 { 734 compatible = "renesas,vin-r8a77990"; 735 reg = <0 0xe6ef5000 0 0x1000>; 736 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&cpg CPG_MOD 806>; 738 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 739 resets = <&cpg 806>; 740 renesas,id = <5>; 741 status = "disabled"; 742 743 ports { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 747 port@1 { 748 reg = <1>; 749 750 vin5csi40: endpoint { 751 remote-endpoint= <&csi40vin5>; 752 }; 753 }; 754 }; 755 }; 756 757 xhci0: usb@ee000000 { 758 compatible = "renesas,xhci-r8a77990", 759 "renesas,rcar-gen3-xhci"; 760 reg = <0 0xee000000 0 0xc00>; 761 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&cpg CPG_MOD 328>; 763 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 764 resets = <&cpg 328>; 765 status = "disabled"; 766 }; 767 768 ohci0: usb@ee080000 { 769 compatible = "generic-ohci"; 770 reg = <0 0xee080000 0 0x100>; 771 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&cpg CPG_MOD 703>; 773 phys = <&usb2_phy0>; 774 phy-names = "usb"; 775 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 776 resets = <&cpg 703>; 777 status = "disabled"; 778 }; 779 780 ehci0: usb@ee080100 { 781 compatible = "generic-ehci"; 782 reg = <0 0xee080100 0 0x100>; 783 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&cpg CPG_MOD 703>; 785 phys = <&usb2_phy0>; 786 phy-names = "usb"; 787 companion = <&ohci0>; 788 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 789 resets = <&cpg 703>; 790 status = "disabled"; 791 }; 792 793 usb2_phy0: usb-phy@ee080200 { 794 compatible = "renesas,usb2-phy-r8a77990", 795 "renesas,rcar-gen3-usb2-phy"; 796 reg = <0 0xee080200 0 0x700>; 797 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&cpg CPG_MOD 703>; 799 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 800 resets = <&cpg 703>; 801 #phy-cells = <0>; 802 status = "disabled"; 803 }; 804 805 gic: interrupt-controller@f1010000 { 806 compatible = "arm,gic-400"; 807 #interrupt-cells = <3>; 808 #address-cells = <0>; 809 interrupt-controller; 810 reg = <0x0 0xf1010000 0 0x1000>, 811 <0x0 0xf1020000 0 0x20000>, 812 <0x0 0xf1040000 0 0x20000>, 813 <0x0 0xf1060000 0 0x20000>; 814 interrupts = <GIC_PPI 9 815 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 816 clocks = <&cpg CPG_MOD 408>; 817 clock-names = "clk"; 818 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 819 resets = <&cpg 408>; 820 }; 821 822 csi40: csi2@feaa0000 { 823 compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2"; 824 reg = <0 0xfeaa0000 0 0x10000>; 825 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cpg CPG_MOD 716>; 827 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; 828 resets = <&cpg 716>; 829 status = "disabled"; 830 831 ports { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 835 port@1 { 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 reg = <1>; 840 841 csi40vin4: endpoint@0 { 842 reg = <0>; 843 remote-endpoint = <&vin4csi40>; 844 }; 845 csi40vin5: endpoint@1 { 846 reg = <1>; 847 remote-endpoint = <&vin5csi40>; 848 }; 849 }; 850 }; 851 }; 852 853 prr: chipid@fff00044 { 854 compatible = "renesas,prr"; 855 reg = <0 0xfff00044 0 4>; 856 }; 857 }; 858 859 timer { 860 compatible = "arm,armv8-timer"; 861 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 862 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 863 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 864 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 865 }; 866}; 867